Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search

1 INTRODUCTION

• NAS search can take days because its large architecture space requires lengthy training to evaluate each candidate, while accuracy-only search does not ensure FPGA timing compliance.Architectures that miss a hardware latency specification may be unusable in those deployment scenarios.Source: §1 · p. 1
• FNAS uses an abstraction model to estimate FPGA latency for irregular NAS architectures, representing task granularity, dependencies, and data accesses from the network and tiling parameters.Extra edges among tasks capture dependencies among DNN layers.Source: §1 · p. 1
• FNAS proposes a flexible multi-FPGA scheduler to exploit parallelism that prior schedulers following single-FPGA designs may not fully use.The framework analyzes execution latency and pipeline stalls to estimate overall latency.Source: §1 · pp. 1–2
• The paper identifies FNAS, an FPGA-implementation-aware architecture graph, and a multi-FPGA schedule paradigm as its main contributions.The framework is described as generating architectures with latency guaranteed on target FPGAs.Source: §1 · p. 2
• 7.81×-over-specification architectures from the state of the art are brought within specification by FNAS with less than 1% accuracy loss and up to 11.13× search speedup.The paper presents this comparison as an experimental result.Source: §1 · p. 2

2 BACKGROUND

• NAS iteratively trains child networks and uses their held-out-set accuracy as the controller's reward, but a reported search trained 20,000 networks across 500 P100 GPUs over four days.The background also notes that searched networks can be complex and slow, failing timing specifications for real-time applications.Source: §2 · p. 2
• FPGA DNN implementations range from one accelerator on one FPGA to multiple accelerators on one or multiple FPGAs, while code-generation-based latency analysis can require human intervention and substantial time.The authors argue that naively using such latency analysis in NAS could make search take even longer.Source: §2 · p. 2
• At a 2-ms inference timing specification on the same dataset, FNAS reduces search time from 190 to 17 minutes (11.13×), yields PYNQ latency 10.94× shorter than NAS, with accuracy degradation within 1%.Source: §2 · p. 2
• FNAS is reported to satisfy target-FPGA timing specifications while maintaining accuracy, including cases with less than 1% accuracy loss.The background states that FNAS can reduce search time and produce architectures with lower latency on PYNQ.Source: §2 · pp. 2–3

3.1 Problem Definition and FNAS Overview

• FNAS seeks the highest-accuracy network for a dataset and target FPGA subject to a required inference latency, and incorporates FPGA performance into child-network search.Its reward uses both accuracy and latency rather than accuracy alone.Source: §3.1 · p. 3

3.2 Reward function

• When latency exceeds the requirement, FNAS returns a negative reward without training the child network; feasible candidates receive performance and accuracy rewards.The performance reward increases as latency approaches the required level; the accuracy baseline is an exponential moving average of previous architecture accuracies.Source: §3.2 · p. 3

3.3 Tiling Parameters: ➀FNAS-Design

• FNAS-Design selects channel and spatial tiling parameters to split convolutional operations into smaller tasks that fit FPGA resources.Each task pairs input- and output-feature-map tiles; tasks are loaded onto processing elements, with their order determined by FNAS-Sched.Source: §3.3 · p. 3, Figure 3 · p. 3

3.4 Tile-based task graph generator: ➁FNAS-GG

• FNAS-GG uses network and design parameters to build a tile-based task graph that represents dependencies among tiles and tasks.The graph captures both dependencies between consecutive layers and dependencies within a layer when adjacent layers use different tiling parameters.Source: §3.4 · pp. 3–4

3.5 Scheduler design: ➂FNAS-Sched

• FNAS-Sched orders input and output tiles and tasks to exploit parallelism, reuse data, and reduce pipeline stalls across processing elements.It favors increasing channel-tile indices first, then alternates output-feature-map and input-feature-map reuse strategies across consecutive layers.Source: §3.5 · p. 4

3.6 Latency analysis: ➃FNAS-Analyzer

• FNAS-Analyzer estimates scheduled FPGA latency from processing, start, and stall times; a ready-to-run queue can replace a stalled task with another ready task.The framework uses the estimate to skip training candidates that miss the timing specification and guide the controller away from insufficiently fast architectures.Source: §3.6 · p. 5

4 EXPERIMENTAL RESULTS

• FNAS achieves up to 11.13×, 10.89×, and 10.38× search speedup on MNIST, CIFAR-10, and ImageNet, respectively, and meets specs with <1% accuracy loss when NAS latency is 9.85× over spec.Source: §4 · p. 5

4.1 Experimental setup

• Experiments use MNIST, CIFAR-10, and ImageNet; ImageNet uses a smaller dataset, and child networks train for 25 epochs.The controller and FPGA configurations vary by dataset; MNIST comparisons use Xilinx 7A50T and 7Z020, while CIFAR-10 and ImageNet use Xilinx ZU9ED.Source: §4.1 · p. 5

4.2 Efficiency and accuracy evaluations of FNAS

• On 7Z020, FNAS reduces search time from 190 minutes to 74, 59, and 17 minutes—2.56×, 3.22×, and 11.13× reductions for loose, medium, and tight specifications.The reported reasons are early pruning of architectures that violate latency targets and the simpler structure of valid networks; tighter specifications further reduce search time.Source: Figure 6 · p. 6, §4.2 · p. 6
• FNAS meets each timing target, while NAS exceeds loose, medium, and tight specifications by 2.54×, 4.19×, and 7.81×, with FNAS accuracy losses of 0.08%, 0.24%, and 0.81%.Source: Figure 6 · p. 6, §4.2 · p. 6
• Across MNIST, CIFAR-10, and ImageNet, accuracy loss is generally below 1% and rises as constraints tighten; CIFAR-10 search time is reduced 11.18×.Source: Figure 7 · p. 6, §4.2 · p. 6

4.3 Improvements from the scheduler

• On four accelerators, the proposed scheduler consistently achieves better performance than fixed scheduling, measured by clock cycles for tested four-layer architectures.The tests use four-layer convolutional architectures on a PYNQ board, with 3×3 filters and 64 or 128 filters per layer.Source: Figure 8 · p. 6, §4.3 · p. 6

• FNAS searches for neural architectures with optimal accuracy while satisfying timing specifications on target FPGAs.Source: §5 · p. 6
• The framework combines a performance abstraction model with a schedule paradigm intended to exploit parallelism among multiple FPGAs.Source: §5 · p. 6
• When NAS latency is 7.81× longer than specification, FNAS meets the specification with less than 1% accuracy loss and up to 11.13× search speedup.Source: §5 · p. 6