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Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers

Yunong Shi, Nelson Leung, Pranav Gokhale, Zane Rossi, David I. Schuster, Henry Hoffman, Fred T. Chong

arXiv:1902.01474v2quant-phcs.CL

TL;DR

Gate-based quantum compilation can leave latency on the critical path because logical instructions do not map efficiently to physical operations. The paper aggregates instructions to improve scheduling and optimize control pulses, achieving a mean speedup of 5× and a maximum of 10× over standard gate-based compilation. Its latency reductions offer an accelerated path to running useful quantum algorithms without waiting for hardware with longer qubit lifetimes.

  • Problem

    The paper addresses latency inefficiency in gate-based compilation, where logical instructions are translated into control pulses despite a mismatch with physical operations.

    Source: §1 · p. 2, §3.2 · p. 5

  • Method

    The compiler aggregates logical instructions, schedules commutative operations, and applies quantum optimal control to the aggregates.

    Source: §1 · p. 2, §3.2 · p. 5, §4.1 · p. 9

  • Results

    The approach achieves a mean speedup of 5× and a maximum speedup of 10× over standard gate-based compilation on near-term quantum algorithms.

    Source: §1 · p. 2

  • Takeaways & Limitations

    By reducing latency 2–10×, the methodology provides an accelerated pathway to running useful quantum algorithms without waiting for hardware with 2–10× longer qubit lifetimes.

    Source: §1 · p. 2

    Compilation can take several hours for circuits with aggregated gates of 10 qubits, which may challenge classical-hybrid applications sensitive to compilation time.

    Source: §9 · p. 12

Abstract

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Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this quantum assembly to electric signals (called control pulses) that implement the specified computation on specific physical devices. However, there is a mismatch between the operations defined by the 1- and 2-qubit logical ISA and their underlying physical implementation, so the current practice of directly translating logical instructions into control pulses results in inefficient, high-latency programs. To address this inefficiency, we propose a universal quantum compilation methodology that aggregates multiple logical operations into larger units that manipulate up to 10 qubits at a time. Our methodology then optimizes these aggregates by (1) finding commutative intermediate operations that result in more efficient schedules and (2) creating custom control pulses optimized for the aggregate (instead of individual 1- and 2-qubit operations). Compared to the standard gate-based compilation, the proposed approach realizes a deeper vertical integration of high-level quantum software and low-level, physical quantum hardware. We evaluate our approach on important near-term quantum applications on simulations of superconducting quantum architectures. Our proposed approach provides a mean speedup of $5\times$, with a maximum of $10\times$. Because latency directly affects the feasibility of quantum computation, our results not only improve performance but also have the potential to enable quantum computation sooner than otherwise possible.

1 Introduction

Near-term quantum applications face a latency challenge because logical gate abstractions do not match physical operations. The paper aggregates logical instructions to optimize schedules and control pulses, reporting speedups over gate-based compilation.

1 Introduction

  • Latency is critical because quantum output fidelity decays at least exponentially with latency, and qubits may decohere before a computation finishes.Source: §1 · pp. 1–2
  • Gate-based compilers translate logical gates into control pulses even though the hardware may implement a different set of operations; direct optimal control is impractical above 10 qubits.Source: §1 · p. 2
  • The framework aggregates 1- and 2-qubit gates, then schedules commutative operations and optimizes custom control pulses for the underlying architecture.It detects diagonal unitaries and blocks circuits to extend optimal control beyond 10 qubits without compromising parallelism.Source: §1 · p. 2
  • The approach achieves a mean speedup of 5× and a maximum speedup of 10× over standard gate-based compilation on near-term quantum algorithms.Source: §1 · p. 2

2 Background

The background introduces qubits, logical gates, and physical control, then explains how gate abstractions can diverge from hardware operations and how gradient-based optimal control searches for control pulses.

2.1 Principles of quantum computation

  • Qubits can occupy superpositions, and an N-qubit system spans exponentially many logical states; a single qubit’s state can be visualized on the Bloch sphere.Source: §2.1 · pp. 2–3

2.2 Quantum gates

  • Logical 1- and 2-qubit gates are represented as unitary matrices; the superconducting benchmarks focus on iSWAP, whose optimized compilation is relatively unexplored.CNOT gates may need decomposition into physical gates because they are not typically directly implemented on a physical platform.Source: §2.2 · p. 3

2.3 Quantum control

  • Physical control fields shape a time-dependent Hamiltonian that determines qubit-state evolution, while quantum gates act as pre-programmed control fields.Source: §2.3 · p. 3

2.4 The mismatch between gates and control

  • Gate decomposition can serialize simultaneously applicable CNOT/Rz controls or expand a SWAP into three CNOTs; larger circuits motivate numerical optimization beyond hand-tuning.The examples concern superconducting platforms for simultaneous controls and quantum dots for direct SWAP implementation.Source: §2.4 · p. 3

2.5 Quantum optimal control

  • GRAPE updates control fields using gradients of a target loss, while gradient methods scale exponentially in runtime and memory; the GPU-accelerated unit optimizes up to 10 qubits.Figure 3 depicts pulse amplitudes by time interval and their fidelity gradients.Source: §2.5 · p. 4, Figure 3 · p. 4

3 Compilation methodology

The methodology replaces direct gate-to-pulse translation with an end-to-end flow that exploits commutativity and aggregates instructions. In a QAOA example, it reduces critical-path pulse duration relative to gate-based compilation.

3.1 An example of QAOA circuit

  • 381.9 ns to 128.3 ns (2.97× shorter): aggregated compilation reduces the QAOA example’s critical-path pulse duration versus gate-based compilation.The gate-based path is 6T(CNOT)+T(SWAP)+T(H)+3T(Rz)+T(Rx); the aggregated path is T(G1)+T(G3)+T(G4).Source: §3.1 · p. 4

3.2 Methodology overview

  • The compiler transforms quantum assembly into a logical schedule, maps and aggregates instructions, then uses optimal control to generate optimized physical schedules and pulses.It explores commutativity in intermediate instructions and limits aggregation size to what the optimal control unit can process.Source: §3.2 · pp. 4–5

3.3 Compilation frontend

  • The frontend lowers quantum programs to logical assembly, performs program-level optimization and scheduling, and represents gate dependencies as a GDG.Its preliminary steps include loop unrolling, module flattening, and commutativity detection.Source: §3.3 · p. 5

Quantum GDG:

  • In a quantum GDG, consecutive commuting gates have no parent-child dependence and can be scheduled in either order.The compiler checks commutation by testing whether the two unitary products are equal in either order.Source: Quantum GDG · p. 5

3.3.1 Commutativity detection:

  • Contracting commuting CNOT-Rz-CNOT blocks exposes scheduling flexibility because the blocks commute even though their constituent gates do not.In the QAOA example, the blocks correspond to diagonal unitaries.Source: §3.3.1 · pp. 6–7

3.3.2 Commutativity-aware Logical Scheduling (CLS):

  • CLS uses commutation groups on qubits to find schedulable candidates, then greedily schedules a maximal matching to avoid simultaneous gates that share qubits.This scheduling strategy targets parallelism rather than minimizing backend SWAP count.Source: §3.3.2 · p. 7

Algorithm 1 CLS

  • CLS repeatedly selects candidate gates, schedules a maximal matching, updates the current commutation groups, and returns the logical schedule.At each iteration, the algorithm takes candidates from the first non-empty commutation groups.Source: Algorithm 1 CLS · p. 8, Figure 7 · p. 8

3.4 Compiler backend

The backend maps and aggregates logically scheduled instructions for the target topology, generates optimized pulses, and schedules the resulting aggregates. Its optimal-control pulses are checked through simulation.

3.4 Compiler backend

  • The backend performs qubit mapping, topological constraint solving, and final instruction aggregation before scheduling aggregated instructions and sending concatenated pulses to hardware.The final schedule uses CLS.Source: §3.4 · p. 8, §3.4.2 · p. 8

3.4.1 Qubit mapping & topological constraint resolution:

  • For the benchmarks, the compiler assumes a rectangular-grid topology where two-qubit operations are allowed only between direct neighbors.It recursively partitions the interaction graph with METIS to place frequently interacting qubits near each other, then inserts SWAP sequences for non-neighboring operations.Source: §3.4.1 · p. 8

3.4.2 Instruction aggregation:

  • The backend iterates instruction aggregation with the optimal control unit, then schedules the aggregated circuit and sends its concatenated pulses to the hardware.The control unit optimizes each instruction individually.Source: §3.4.2 · p. 8

3.5 Optimal control unit

  • The GPU-accelerated optimal-control algorithm uses automatic differentiation and TensorFlow to optimize pulses against criteria including unwanted-level suppression, voltage fluctuation, and latency.The algorithm has been validated against real hardware and used in experimental environments.Source: §3.5 · p. 8

3.6 Verification

  • QuTip simulations verify the unitaries defined by aggregated instructions and their generated pulses; the evaluation samples 10 aggregated instructions per benchmark.The procedure is intended to provide confidence in numerical accuracy.Source: §3.6 · p. 8

4 Instruction aggregation

Instruction aggregation is constrained to preserve continuity and practical pulse optimization, while its search balances larger, faster-to-optimize instructions against parallelism. The algorithm prioritizes monotonic actions and iterates with updated pulse latencies.

4 Instruction aggregation

  • In the illustrated action space, G3 can aggregate with any other gate, but only pairing it with G6 is monotonic.Other pairs serialize the circuit by delaying a dependent aggregated instruction.Source: Figure 8 · p. 9

4.1 Action space for instruction aggregation

  • Two instructions may aggregate when they overlap and are parent-child on shared qubit paths or siblings, with commutation or ordering conditions that keep pulses continuous.Instruction width is also limited by the scalability of the optimal control unit.Source: §4.1 · p. 9

4.2 Diagonal unitaries aggregation for commutativity detection

  • For diagonal-unitary commutativity detection, the compiler searches allowed aggregation actions within 2-qubit blocks, typically no longer than 10 gates.The method limits detection to 2-qubit-wide blocks to preserve parallelism.Source: §4.2 · p. 9

4.3 Instruction aggregation

  • Larger aggregates can yield more optimized pulses, but merging instructions can delay dependent work and compromise circuit parallelism.The paper illustrates this trade-off with merging G5 and G3, which serializes the circuit behind G4.Source: §4.3 · p. 9
  • Monotonic actions do not delay critical paths, and their latency-reduction reward exceeds that of aggregating a subset of the same instructions.The compiler identifies them by comparing original circuit depth with depth after the action.Source: §4.3 · p. 9
  • The algorithm traverses the GDG, records each instruction’s best monotonic action, executes the global best action, and repeats until none remain.It then queries the optimal control unit for updated aggregate latencies and repeats the procedure until the GDG converges.Source: §4.3 · p. 9

5 Evaluation

The evaluation simulates the compilation strategies on superconducting architectures and benchmarks near-term quantum applications with varied program characteristics. Across nine benchmarks, the proposed scheme achieves a 5.07× geometric-mean pulse time reduction.

5.1 Experimental setup

  • The simulations use superconducting architectures with XY interaction, a 0.02 GHz XY control-field limit, and single-qubit rotation fields limited to five times that value.The control-field setting is chosen to model transmon operations with low leakage to higher states.Source: §5.1 · p. 9

5.2 Benchmark methodology

  • The benchmark suite spans MAXCUT QAOA, highly parallel Ising circuits, serialized square-root circuits, and UCCSD, chosen to expose different program characteristics.The UCCSD benchmark addresses whether optimal control can make a machine-unaware ansatz more hardware efficient on superconducting architectures.Source: §5.2 · pp. 9–10, Table 3 · p. 10

5.3 Latency

  • 5.07× geometric-mean pulse time reduction across nine benchmarks, with lower circuit latency than gate-based compilation with hand optimization in every benchmark studied.The comparison strategies include unoptimized gate-based compilation, CLS, aggregation without CLS, CLS plus aggregation, and hand optimization.Source: Figure 9 · p. 10, §5.3 · p. 10
  • The comparison includes unoptimized gate-based compilation, CLS, aggregation without CLS, CLS plus aggregation, and mechanically applied hand optimization methods.The hand-optimization strategy applies documented methods for iSWAP architectures to the authors’ best effort.Source: §5.3 · p. 10

6 Discussion

The discussion examines how commutativity, parallelism, spatial locality, and information encoding relate to the gains from aggregation. Its analysis finds larger gains in serialized, less spatially localized circuits and for more sophisticated encoding schemes.

6.1 Commutativity vs Scheduling

  • In highly commutative MAXCUT circuits, CLS alone reduces circuit length by up to 5×; for circuits with little or no commutativity, it has no effect.CLS also enables a stronger aggregation result on Ising-n15: 3.44× circuit-length reduction with CLS plus aggregation versus 2.22× for aggregation alone.Source: §6.1 · pp. 10–11

6.2 Parallelism vs Instruction width

  • Larger allowed instruction widths do not reduce latency for highly parallel QAOA and Ising circuits, while serialized applications benefit until the optimal-control scalability limit.For serialized applications, total circuit latency reduction approaches the lower bound represented by the most optimized critical-path instruction as width increases.Source: §6.2 · p. 11, Figure 10 · p. 11

6.3 Spatial locality vs Aggregation

  • For the three QAOA instances, MAXCUT-cluster has the lowest latency and MAXCUT-line the highest relative to CLS; aggregation improves more on the less spatially localized instance.After CLS, the instances are highly parallel and have similar instruction sets; less spatial locality requires more SWAP gates.Source: §6.3 · p. 11, Figure 11 · p. 11

6.4 Information encoding scheme vs Pulse optimization

  • For spatially localized benchmarks, hand optimization matches the compilation scheme on MAXCUT-line, while the scheme yields 3.12× greater circuit-latency reduction on UCCSD-n4 and 3.68× more on Square root.The authors observe a trend toward greater advantage over hand optimization as information encoding becomes more complicated.Source: §6.4 · pp. 11–12

7 Related work

Prior work includes gate-level optimization techniques and approaches that move beyond standard ISA abstraction. The paper positions its contribution as systematic instruction aggregation for latency reduction.

7 Related work

  • Gate-level optimization includes hand optimization, template matching, and rule-based rewriting, but template matching depends on manually developed gate-library rules and rewriting has a large strategy search space.The cited literature includes reversible-logic-to-technology-level optimization methods.Source: §7 · p. 12
  • The workflow remains compatible with many logical gate-level optimizations, though some backend optimizations can have no effect inside an aggregate when they preserve its output unitary.Source: §7 · p. 12
  • Other work moves beyond standard ISA abstraction through optimal control of single-qubit rotations or pulse-level random circuits for quantum-supremacy demonstrations.Source: §7 · p. 12
  • Earlier optimal-control compilation reported speedups up to 300% using restricted recursive complex instructions, but did not provide an instruction aggregation algorithm.Source: §7 · p. 12
  • The paper presents its approach as a systematic and universal way to reduce circuit latency while addressing disadvantages of previous work.Source: §7 · p. 12

8 Conclusion

The conclusion presents a quantum-optimal-control compilation methodology that aggregates multi-qubit instructions beyond the standard gate-based ISA. Its evaluation reports up to 10× circuit-latency reduction and identifies circuit characteristics associated with larger advantages.

8 Conclusion

  • The compilation methodology uses quantum optimal control to aggregate multi-qubit instructions, breaking the standard gate-based ISA abstraction.Source: §8 · p. 12
  • The implementation achieves up to 10× circuit-latency reduction on superconducting architectures in several near-term quantum applications.Source: §8 · p. 12
  • The scheme is most advantageous for circuits that are highly serial, have low spatial locality, and use sophisticated information encoding.Source: §8 · p. 12

9 Future work

Future work addresses compilation cost, calibration burden, and scheduling on superconducting architectures, while also exploring circuit transformation and instruction-aggregation improvements.

9 Future work

  • For circuits with 10-qubit aggregated gates, compilation can take several hours, motivating improvement or partial compilation for classical-hybrid applications sensitive to compilation time.The method requires more computational resources and longer compilation than gate-based compilation.Source: §9 · p. 12
  • Circuit-specific customization of aggregated instructions increases experimental calibrations, and realistic error modeling is proposed as a way to address the calibration–latency conflict.Source: §9 · p. 12
  • The authors identify theoretical circuit optimization with iSWAP on superconducting architectures as a direction for future circuit transformation and application-level optimization.Source: §9 · p. 12
  • A precise superconducting-architecture SWAP cost model is proposed as an open problem for improving scheduling and mapping.Source: §9 · p. 12

A Physical quantum gates

The passage maps physical two-qubit gates to interaction architectures, including superconducting and trapped-ion platforms.

A Physical quantum gates

  • Heisenberg-interaction platforms such as quantum dots use a directly implementable SWAP gate, which implements a SWAP when applied twice.Source: A Physical quantum gates · p. 12
  • ZZ-interaction platforms, including superconducting Josephson flux-qubit systems and NMR, use CPhase, equivalent to CNOT up to single-qubit rotations.Source: A Physical quantum gates · p. 12
  • XY-interaction platforms such as transmons use iSWAP, while trapped-ion dipole-chain platforms use geometric-phase or XX gates.Source: A Physical quantum gates · p. 13
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