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MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

Charlotte Frenkel, Jean-Didier Legat, David Bol

arXiv:1904.08513v2cs.NEcs.ET

TL;DR

Binary-weight SNNs need on-chip online learning and scalable connectivity without losing their memory and area advantages. MorphIC addresses this with stochastic SDSP learning and hierarchical routing, achieving high synapse density, an order-of-magnitude MNIST area-accuracy improvement, and no energy-accuracy penalty.

  • Problem

    Power- and area-efficient SNNs still need techniques that support on-chip online learning with binary weights without compromising synapse density.

  • Method

    MorphIC combines stochastic SDSP online learning with a hierarchical routing fabric in a quad-core binary-weight digital neuromorphic processor.

  • Results

    MorphIC achieves an order-of-magnitude improvement in the MNIST area-accuracy tradeoff compared with previously proposed SNNs, with no energy-accuracy penalty using rank order coding.

  • Takeaways & Limitations

    The processor demonstrates binary-weight SNN operation with high-density plastic synapses and embedded online learning for power- and resource-constrained applications.

Abstract

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Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm$^2$ in 65nm CMOS, achieving a high density of 738k synapses/mm$^2$. MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.

I. INTRODUCTION

MorphIC addresses the challenge of combining binary-weight efficiency, SNN event-driven processing, and on-chip online learning without sacrificing synapse density. It combines stochastic SDSP learning with hierarchical routing in a quad-core processor and reports high density, strong MNIST area-accuracy tradeoffs, and online-learning validation.

  • Learning: S-SDSP enables binary-weight online learning using standard high-density SRAMs rather than the custom transpose SRAM required by binary S-STDP.SDSP uses information available in the postsynaptic neuron at presynaptic spike time and avoids local synaptic spike-timing storage.
  • Connectivity: The hierarchical connectivity scheme uses only 27 connectivity bits per neuron while supporting fan-in of 1k and fan-out of 2k neurons.Connectivity information is stored locally in neuron memory, enabling memory-less routers.
  • Contribution: MorphIC combines stochastic SDSP online learning with hierarchical routing to support large-scale plastic connectivity in binary-weight SNNs.The routing fabric uses mesh-based inter-chip, star-based inter-core, and crossbar-based intra-core connectivity.
  • Contribution: 738k 1-bit online-learning synapses/mm^2 are integrated with 2k LIF neurons and more than 2M synapses in 2.86mm^2 of 65nm CMOS.MorphIC is implemented as a quad-core digital neuromorphic processor.
  • Results: MorphIC achieves 97.8% MNIST test accuracy with offline-trained binary weights and an order-of-magnitude area-accuracy improvement over other SNNs.The reported area-accuracy advantage is accompanied by no penalty in the energy-accuracy tradeoff using rank order coding.
  • Results: MorphIC validates embedded online learning by discriminating eight patterns with S-SDSP.The processor also demonstrates its binary-weight architecture and routing fabric in the reported MNIST evaluation.

II. ARCHITECTURE AND IMPLEMENTATION

MorphIC is a synchronous digital quad-core spiking processor combining stochastic SDSP learning with time-multiplexed neuron and synapse updates.

  • MorphIC combines stochastic SDSP learning with a quad-core digital spiking neuromorphic processor.Each core contains 512 leaky integrate-and-fire neurons.
  • Time multiplexing increases neuron and synapse density by sharing update circuits and storing states in local SRAM.

A. Hierarchical event routing

MorphIC uses a heterogeneous, hierarchical routing fabric that combines mesh, star, and crossbar routing for inter-chip, inter-core, and local connectivity.

  • The routing fabric combines deadlock-free mesh-based L2, star-based L1, and crossbar-based L0 routing.L2 is unicast and destination-driven, L1 is multicast and source-driven, and L0 handles local packet decoding and encoding.
  • MorphIC supports local-core, same-chip inter-core, and inter-chip connectivity through L0, L1, and L2 synapses.A neuron can combine these connectivity types for fan-in of 512 + 512 + 32 and fan-out of 512 + 3×512 + 4.
  • 27 connectivity bits per neuron determine the connectivity of a MorphIC-chip network and are stored in local neuron SRAM.Connectivity information is decentralized near neurons and carried in event packets, so routers need no mapping tables.
  • Each neuron stores parameters, state, outward connectivity, and 32 1-bit input L2 synapses in a 128-bit SRAM word.The L2 and L1 connectivity fields occupy 27 bits per neuron.

1) Level-2 (L2) router:

The L2 router provides asynchronous inter-chip event routing using dimension-ordered mesh dispatch and multiplexed AER communication.

  • L2 routes packets across four independent cardinal links using unicast dimension-ordered routing, forwarding them to L1 when dx and dy reach zero.Three-bit signed dx and dy fields support routing up to three MorphIC chips in each direction.
  • Round-robin arbitration guarantees maximum packet-processing latency, whereas priority-based arbitration serves links according to FIFO activity.
  • 32-bit event packets are transmitted as four 8-bit AER transactions over the pad-limited L2 links.Double-latching synchronization barriers reduce metastability issues on asynchronous handshake lines.
  • L2 packet activity should remain sparse because off-chip pads are the speed bottleneck, making L2 events suitable for high-level features.A two-phase handshake could improve L2 routing speed over the standard four-phase AER handshake.

2) Level-1 (L1) router:

The L1 router connects the four cores through source-based multicast, while the L0 interface decodes and schedules local and hierarchical event types.

  • The L1 router uses a star topology to multicast events from local cores to selected destination cores without FIFO buffering.An arbiter supports configurable round-robin or greedy priority-based dispatch.
  • L1 handles ascending events toward other cores or the L2 router and descending L2 events toward selected cores.
  • The L0 interface decodes configuration, monitoring, and scheduler packets before local processing.Scheduler events include L2, L1, L0, virtual, teacher, and leak events.
  • Locally generated L0 events remain in the core scheduler, while upward events are encoded for forwarding through the L1 router.Monitoring replies and L1/L2 events are among the encoded packet types.

B. Stochastic spike-dependent synaptic plasticity (S-SDSP)

S-SDSP adapts SDSP to binary synapses by combining SDSP update conditions with stochastic weight transitions, while using pseudo-random generation for single-cycle updates.

  • B. Stochastic spike-dependent synaptic plasticity (S-SDSP): SDSP avoids per-synapse spike-timing buffers because each update depends on the post-synaptic membrane potential and calcium state at the pre-synaptic spike.The calcium concentration represents recent firing activity and is compared with thresholds alongside the membrane potential.
  • B. Stochastic spike-dependent synaptic plasticity (S-SDSP): S-SDSP combines SDSP update conditions with stochastic binary-synapse transitions, making online learning compatible with time-multiplexed event-driven implementations.The rule uses binary random variables with probabilities q+ and q− to update binary weights under SDSP conditions.
  • B. Stochastic spike-dependent synaptic plasticity (S-SDSP): The implementation stores calcium and S-SDSP parameters in neuron SRAM while time-multiplexed logic shares update circuitry across synapses.This design supports binary online learning without requiring a custom transpose SRAM for STDP updates.
  • B. Stochastic spike-dependent synaptic plasticity (S-SDSP): A 9-bit LFSR-based generator provides the pseudo-random probabilities needed for S-SDSP updates within one clock cycle.The selected resolution supports probabilities down to approximately 0.01 and distance-based modulation across seven distance values.

III. MEASUREMENTS AND BENCHMARKING RESULTS

Measurements show MorphIC’s silicon implementation supports low-energy operation and both offline quantization-aware and online S-SDSP learning benchmarks.

  • III. MEASUREMENTS AND BENCHMARKING RESULTS: 51pJ per synaptic operation is measured at 0.8V and maximum 55MHz clock and 110MSOP/s processing rates when leakage and idle power are included.The reported total energy includes leakage and idle-power contributions.
  • III. MEASUREMENTS AND BENCHMARKING RESULTS: 97.8% MNIST accuracy is reached using all four cores and available neuron resources with conventional rate-based coding.The network uses the topology shown in the MNIST classification setup.
  • III. MEASUREMENTS AND BENCHMARKING RESULTS: 21.8µJ per classification is achieved with rank-order coding, a 10-fold energy reduction from rate coding at the cost of a 1.9% accuracy drop.Rank-order coding operates at 5.45mW for 250 classifications per second at 0.8V and 55MHz.
  • III. MEASUREMENTS AND BENCHMARKING RESULTS: Online S-SDSP learning is demonstrated on an eight-pattern spiking CNN benchmark using fixed-weight convolutional and pooling layers followed by plastic connections.The benchmark maps pooling outputs through L1 connectivity into a flattened layer.

IV. DISCUSSION

The discussion frames MorphIC against prior silicon learning-rule implementations and presents an eight-pattern CNN as an online-learning benchmark.

  • IV. DISCUSSION: The benchmark comparison covers silicon implementations of bottom-up STDP- and SDSP-based learning rules and includes MorphIC’s online-learning demonstration.The discussion references the eight-pattern CNN classification benchmark implemented with S-SDSP.
  • IV. DISCUSSION: The eight-pattern CNN uses four oriented 7×7 line-detection kernels, average pooling, and an eight-neuron fully connected output layer.The test set contains 100 Poisson realizations of each pattern.

A. Hierarchical event routing

MorphIC uses hierarchical routing with compact, memory-less routers, but its crossbar-based connectivity favors fully connected and recurrent networks over convolutional layers.

  • A. Hierarchical event routing: 27 bits per neuron define multichip connectivity while MorphIC routers remain memory-less beyond event buffering, avoiding stored mapping tables.This contrasts with approaches that require external or local mapping-table storage.
  • A. Hierarchical event routing: MorphIC’s all-to-all crossbar routing is well suited to fully connected and recurrent networks but poorly utilizes synaptic fan-in for convolutional layers.Convolutional kernels must be copied into each output neuron’s dendritic tree because efficient weight reuse is absent.
  • A. Hierarchical event routing: Time-multiplexed convolutional processing can spend most controller cycles on dummy zero-weight SOPs, although controller updates can mitigate this overhead.The proposed mitigation is analogous to start-and-end-address optimization for fully connected layers.
  • A. Hierarchical event routing: Clocked MorphIC routers trade design simplicity for bandwidth efficiency because a core-level critical path limits routers that could otherwise operate faster.Asynchronous routers or locally generated high-speed clocks are identified as possible alternatives.

B. S-SDSP online learning

The paper situates S-SDSP within the difficulty of translating local brain-inspired learning into complex applications. It combines dense binary synapses with foundry-SRAM implementation and demonstrates online learning on an eight-pattern benchmark.

  • B. S-SDSP online learning: S-SDSP reaches the highest density of online-learning synapses and is demonstrated on an eight-pattern benchmark.The paper notes that prior silicon implementations had not demonstrated STDP- or SDSP-based learning on the full MNIST dataset without preprocessing.
  • B. S-SDSP online learning: Bottom-up silicon learning designs progress from neuroscience experiments to efficient circuits and then application demonstrations.
  • B. S-SDSP online learning: Top-down approaches begin with application problems and adapt algorithms such as backpropagation toward spiking or biologically inspired computation.
  • B. S-SDSP online learning: Foundry single-port SRAM supports S-SDSP while improving design time and density relative to custom-SRAM-based designs.This implementation enables high-density integration of binary plastic synapses.

C. Tradeoff analysis of energy, area and accuracy

MorphIC offers an order-of-magnitude area-accuracy improvement on full MNIST comparisons while maintaining an energy-accuracy tradeoff comparable to leading reference SNNs. Rank order coding reaches this energy profile, whereas rate coding prioritizes accuracy at higher power cost.

  • C. Tradeoff analysis of energy, area and accuracy: The comparison normalizes silicon area and energy to a 65-nm technology node for one-to-one evaluation across SNN implementations.
  • C. Tradeoff analysis of energy, area and accuracy: Rank order coding brings MorphIC’s energy-accuracy tradeoff close to TrueNorth and Chen et al., unlike rate coding’s higher-power accuracy advantage.The reported rank-order energy per inference is 21.8µJ at 0.8V and 55MHz.
  • C. Tradeoff analysis of energy, area and accuracy: Systematically processing all crossbar neurons for each input spike creates dummy operations that increase energy consumption.A hidden-layer neuron may require only 10+1 SOPs toward the output layer rather than 512.
  • C. Tradeoff analysis of energy, area and accuracy: An order-of-magnitude area-accuracy improvement is achieved over previously proposed SNNs on MNIST, while energy-accuracy remains comparable to TrueNorth and Chen et al.The comparison uses SNNs evaluated on the full 28×28 MNIST dataset without preprocessing beyond pixel-to-spike conversion, with area and energy normalized to 65 nm.

D. Comparison with previously-proposed binary SNNs

MorphIC combines binary weights with embedded online learning and achieves record synapse density among the compared binary SNN processors. Its density advantage is accompanied by energy per SOP similar to other binary SNNs despite using a less advanced process.

  • D. Comparison with previously-proposed binary SNNs: MorphIC and Seo et al. are the only compared binary SNNs demonstrating embedded online learning with binary weights.
  • D. Comparison with previously-proposed binary SNNs: An order-of-magnitude density advantage over Seo et al.’s S-STDP is maintained after normalization to 65 nm.The comparison identifies MorphIC’s binary-weight S-SDSP approach as achieving record density.
  • D. Comparison with previously-proposed binary SNNs: MorphIC’s energy per SOP is similar to other binary SNN processors despite its less advanced CMOS process.
  • D. Comparison with previously-proposed binary SNNs: MorphIC integrates stochastic SDSP, hierarchical routing, and 738k synapses per mm2 in a quad-core processor.The routing fabric uses distance information to modulate synaptic update probabilities in accordance with small-world network modeling.
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