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RowHammer: A Retrospective

Onur Mutlu, Jeremie S. Kim

arXiv:1904.09724v1cs.CRcs.AR

TL;DR

Scaled memory cells are increasingly vulnerable to disturbance errors, exemplified by RowHammer, in which repeated row access flips bits in adjacent rows and can threaten system security. The paper retrospectively analyzes the original problem and defenses, surveys follow-up attacks and mitigations, and concludes that reliability and security research must anticipate related vulnerabilities as memory technologies scale.

  • Problem

    Memory scaling improves density and cost but makes smaller, lower-charge cells more vulnerable to failure mechanisms that can open serious security vulnerabilities.

  • Method

    The paper provides a retrospective of the original RowHammer work and a comprehensive survey of subsequent attacks, defenses, and analyses.

  • Results

    RowHammer was found in 110 of 129 tested DRAM modules, and subsequent work demonstrated practical attacks including user-level privilege escalation on real systems.

  • Takeaways & Limitations

    RowHammer demonstrates that hardware failure mechanisms can become practical and widespread system security vulnerabilities as memory technologies scale.

Abstract

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This retrospective paper describes the RowHammer problem in Dynamic Random Access Memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 conference~\cite{rowhammer-isca2014}. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically-adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called {\em DRAM disturbance errors}, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology. Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this article, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or Phase Change Memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities.

I. INTRODUCTION AND OUTLINE

RowHammer shows how scaled-memory circuit failures can become practical system security vulnerabilities. This retrospective describes the phenomenon, surveys attacks and defenses, and discusses related risks as memory technologies scale.

  • I. INTRODUCTION AND OUTLINE: Memory scaling increases density and lowers cost, but smaller cells and lower charge make modern memories more vulnerable to failure mechanisms and interference.The paper frames memory reliability as important because memory strongly influences system performance, energy efficiency, and reliability.
  • I. INTRODUCTION AND OUTLINE: The original work rigorously analyzed RowHammer and seven solutions, while this article surveys subsequent attacks, defenses, and analyses.The proposed PARA mechanism is described as low-cost, configurable, and adopted in variants by DRAM manufacturers and memory-controller designers.
  • I. INTRODUCTION AND OUTLINE: RowHammer is a circuit-level DRAM failure mechanism in which repeatedly accessing one row causes predictable bit flips in physically adjacent rows.The mechanism is called DRAM disturbance errors and reflects cell-to-cell interference in scaled memory technology.
  • I. INTRODUCTION AND OUTLINE: User-level programs can exploit RowHammer to gain kernel privileges on real systems, and follow-up work demonstrated attacks across servers, virtual machines, and mobile devices.Reported examples include remote server takeover, cross-virtual-machine takeover, and takeover by permissionless mobile applications.
  • I. INTRODUCTION AND OUTLINE: The paper argues that future memory scaling may worsen RowHammer and that related vulnerabilities may exist in DRAM, NAND flash, and Phase Change Memory.These vulnerabilities could threaten secure systems as memory technologies reach higher densities.

II. THE ROWHAMMER PROBLEM: A SUMMARY

The authors experimentally establish RowHammer as a widespread disturbance error in commodity DRAM and describe its physical mechanism and experimental limitations. Vulnerability was observed across manufacturers and was especially prevalent in newer modules.

  • II. THE ROWHAMMER PROBLEM: A SUMMARY: Repeatedly opening and closing a DRAM row within a refresh interval can flip bits in physically adjacent rows.The authors tested 129 modules from three major manufacturers using an FPGA-based DRAM testing infrastructure.
  • II. THE ROWHAMMER PROBLEM: A SUMMARY: 110 of 129 DRAM modules manufactured from 2008–2014 exhibited RowHammer errors, with the earliest vulnerable module dating to 2010.All tested modules manufactured during 2012–2013 were vulnerable.
  • II. THE ROWHAMMER PROBLEM: A SUMMARY: Repeated wordline voltage toggling can accelerate charge leakage in vulnerable cells until they lose data before the next 64ms refresh interval.The paper identifies this process as one disturbance mode affecting commodity DRAM chips from all three major manufacturers.
  • II. THE ROWHAMMER PROBLEM: A SUMMARY: The paper hypothesizes three possible wordline-to-cell interaction mechanisms but cannot make definitive device-level claims without analyzing existing DRAM chips.At least two major DRAM manufacturers confirmed all three hypotheses as potential causes of disturbance errors.
  • II. THE ROWHAMMER PROBLEM: A SUMMARY: The original work surveys circuit-level RowHammer studies, while detailed test setup and module characteristics are reported in the original RowHammer paper.The retrospective omits those detailed analyses and focuses on security vulnerabilities and prevention.

B. User-Level RowHammer

A simple user-level program reliably induces RowHammer errors on vulnerable systems, and the predictable repeatability of affected cells enables controlled attacks against other programs’ memory.

  • B. User-Level RowHammer: A simple user-level program reliably induced RowHammer errors on three commodity AMD and Intel systems with vulnerable DRAM modules.Both read and write accesses could induce errors when a row was repeatedly opened.
  • B. User-Level RowHammer: RowHammer violates memory invariants because accesses to one row can modify data in other rows rather than only at the accessed address.The two violated invariants concern read non-modification and write locality.
  • B. User-Level RowHammer: Software page mappings allowed the program to corrupt specific bits in pages belonging to other programs.The paper connects DRAM row mappings through system software and the memory controller to cross-program corruption.
  • B. User-Level RowHammer: The original paper characterized prevalence, access and data patterns, temperature, address correlations, bit flips, affected rows, and repeatability.The retrospective refers readers to the original paper for the rigorous treatment of these characteristics.
  • B. User-Level RowHammer: RowHammer-induced errors are predictably repeatable, making repeatable security attacks possible in a controlled manner.A cell corrupted once by RowHammer is very likely to be corrupted again through RowHammer.

D. RowHammer as a Security Threat

RowHammer breaches memory isolation and can support attacks that corrupt, crash, or take over systems. The paper compares seven countermeasures and presents PARA as a low-overhead probabilistic defense, while surveying subsequent research.

  • D. RowHammer as a Security Threat: RowHammer breaches memory isolation because accesses to one row can modify data stored in another row, including privileged operating-system memory.The resulting disturbance attacks can corrupt system memory, crash a system, or take over the entire system.
  • E. RowHammer Solutions: The original work analyzed seven countermeasures that trade off feasibility, cost, performance, power, and reliability.The authors identify PARA as the most efficient solution with the lowest overhead among those considered.
  • E. RowHammer Solutions: The first six solutions include better manufacturing, ECC, higher refresh rates, static or dynamic remapping, and runtime identification with neighbor refresh.The retrospective states that these approaches incur significant power, performance, or cost overheads.
  • E. RowHammer Solutions: PARA probabilistically activates adjacent rows whenever a row is opened and closed, so repeatedly accessed rows eventually trigger neighbor refreshes.The mechanism is stateless and has low performance and power overhead because it infrequently activates only adjacent rows.
  • E. RowHammer Solutions: The retrospective surveys RowHammer attacks, defenses, circuit-level studies, and related research while identifying potential future research areas.The survey organizes follow-up work into seven categories and discusses future research in each topic area.

A. Exploits using RowHammer

RowHammer attacks turn predictable DRAM bit flips into practical privilege-escalation and takeover exploits across servers, virtual machines, mobile devices, browsers, and remote-access interfaces.

  • A. Exploits using RowHammer: 2015 Google Project Zero exploits used user-level RowHammer programs to gain kernel privileges and take over all physical memory on real systems.One exploit modified a page-table entry to point to an attacker-controlled page table.
  • A. Exploits using RowHammer: A malicious virtual machine can corrupt deduplicated pages shared with a victim VM, compromising OpenSSH or apt-get without ordinary writes.The attack relies on memory deduplication and RowHammer-induced modifications that the deduplication engine does not detect.
  • A. Exploits using RowHammer: Drammer demonstrated a permissionless RowHammer attack on ARM-based mobile systems using deterministic Android memory allocation patterns.The attacker forces a victim page-table entry into a RowHammer-vulnerable memory region.
  • A. Exploits using RowHammer: JavaScript executed by a website was shown to launch RowHammer remotely and gain root privileges on a visiting system.The proof of concept relies on JavaScript being enabled by default in modern browsers.
  • A. Exploits using RowHammer: Other attacks used WebGL, RDMA, and related interfaces for mobile or remote takeover, establishing broad security implications for RowHammer.Reports also indicate vulnerability in newer DDR4 and other DRAM chips, motivating continued research.

B. Defenses against RowHammer

RowHammer defenses range from immediate software and refresh-rate changes to long-term hardware and controller mechanisms. The retrospective finds important overheads and implementation constraints, while presenting PARA as a low-cost probabilistic alternative.

  • B. Defenses against RowHammer: Immediate defenses target deployed systems through increased refresh rates, software detection, selective victim-row refresh, and physical page isolation.Major manufacturers adopted increased-refresh-rate patches, while ANVIL monitors hardware counters and selectively refreshes rows under attack.
  • B. Defenses against RowHammer: The original work evaluates seven countermeasures, including stronger DRAM, ECC, refresh-rate increases, cell remapping, runtime detection, and neighbor refresh.The first six approaches incur significant power, performance, or cost overheads; SECDED ECC cannot correct cache blocks with two or more bit flips.
  • B. Defenses against RowHammer: Strong ECC for all rows is likely inefficient because RowHammer bit flips depend on access patterns and affect only a small number of simultaneously hammered rows.Universal redundancy adds capacity, cost, and energy overheads that are disproportionate to this access-pattern-dependent failure mode.
  • B. Defenses against RowHammer: PARA probabilistically refreshes adjacent rows when a memory controller closes an activated row, trading protection guarantees against performance overhead through a configurable probability.The paper reports negligible performance and energy overhead, no storage cost, and much higher reliability guarantees than modern hard disks.
  • B. Defenses against RowHammer: PARA is not immediately deployable without controller or DRAM changes, and controller implementations require currently unknown row-adjacency information because manufacturers may remap rows.DRAM-side timing-slack implementations may fail across operating conditions or chips, while performance and energy research seeks to reduce that slack.
  • B. Defenses against RowHammer: The retrospective advocates system-memory co-design to make RowHammer and related reliability vulnerabilities easier to find, mitigate, and prevent.This approach emphasizes cooperation between memory controllers and DRAM chips.

C. Circuit-level Studies of RowHammer

Circuit-level studies attribute RowHammer to charge and interface-trap phenomena and show that technology scaling and irradiation can alter susceptibility. These findings inform both mechanism understanding and mitigation difficulty.

  • C. Circuit-level Studies of RowHammer: Charge pumping, charge capture around aggressor wordlines, and carrier migration to victim wordlines are reported as mechanisms governing or exacerbating RowHammer.Feature-size scaling aggravates the effect, potentially making future DRAM generations harder to mitigate.
  • C. Circuit-level Studies of RowHammer: Gamma-ray irradiation increases the number of DRAM rows vulnerable to RowHammer, while vulnerability shows almost no correlation with low data-retention time.This corroborates the original paper’s separation of RowHammer susceptibility from retention weakness.
  • C. Circuit-level Studies of RowHammer: Irradiated cells can show both lower retention and greater RowHammer susceptibility, and higher susceptibility persists after temperature annealing.Annealing repairs retention-weak cells but does not remove the observed RowHammer susceptibility.
  • C. Circuit-level Studies of RowHammer: Hydrogen annealing during dry etching reduces interface-trap density and is reported to improve DRAM reliability against crosstalk and RowHammer attacks.The proposed explanation is that RowHammer is mainly caused by interface traps.
  • C. Circuit-level Studies of RowHammer: Experiments on DDR3 devices find statistical RowHammer failure distributions and support charge recombination between victim cells and neighboring-cell current channels.The studies identify a physical mechanism involving electrons from neighboring cells and corresponding bitlines.

D. Other Works Exploiting RowHammer

Beyond attacks and defenses, RowHammer can also be repurposed as a security primitive: its device-specific behavior can generate unique identifiers.

  • D. Other Works Exploiting RowHammer: A Physical Unclonable Function uses RowHammer behavior to generate device fingerprints from manufacturing variation.The cited work experimentally demonstrates this use by reserving a memory region.

E. Platforms for Studying RowHammer

Researchers developed platforms and techniques to make RowHammer easier to study, reproduce, and exploit. These tools support address mapping, testing, and maximizing DRAM accesses despite caching.

  • Raspberry Pi systems simplify memory exploration through a direct linear mapping between virtual and physical addresses.This reduces the difficulty of identifying physically adjacent DRAM rows.
  • SoftMC and related platforms provide infrastructure for experimentally studying RowHammer behavior.
  • RowHammer testing was added to MemTest86, enabling users to test their systems for the vulnerability.
  • Reverse-engineering methods identify the DRAM rows surrounding a victim row, enabling more effective hammering.
  • A linear-time cache-eviction-set algorithm helps attackers maximize DRAM accesses when caching cannot be avoided.
  • RowHammer’s visibility helped make hardware security more mainstream in the media and broader security community.

G. Persistence of RowHammer Failures in Modern DRAM

RowHammer remains observable despite mitigation proposals, while technology scaling and related disturbance errors motivate continued research across memory technologies. The paper frames RowHammer as evidence that widespread hardware faults can become exploitable security problems.

  • RowHammer failures remain observable in state-of-the-art DDR4, ECC, LPDDR3, and LPDDR2 DRAM devices.The persistence across generations and standards suggests that current DRAM security vulnerabilities may continue.
  • Disturbance errors are a general reliability problem found in DRAM, SRAM, flash, and hard disk drives.
  • Flash-memory experiments show read-disturb errors are widespread in recent memory chips and can require correction mechanisms.
  • DRAM disturbance errors are especially security-relevant because user programs directly access DRAM and strong error correction is uncommon.
  • Future RowHammer research is expected to address attacks, defenses, and broader modeling and prevention.
  • RowHammer shifted security research toward recognizing general-purpose hardware as fallible and exploitable.

A. Other Potential Vulnerabilities

The paper identifies data retention and other cell-level behaviors as potential security vulnerabilities in increasingly dense memories. It discusses retention challenges in DRAM and flash, recovery-based privacy risks, and variation-driven attack opportunities.

  • Higher memory density makes data retention harder through more cells, smaller charge-storage units, and narrower voltage margins.
  • DRAM Data Retention Issues: DRAM refresh-rate determination is becoming more difficult because retention depends on data patterns and can vary unpredictably over time.Variable Retention Time may be difficult to test before it appears, allowing some retention errors to reach the field.
  • DRAM Data Retention Issues: DRAM data-retention investigations aimed at performance and energy efficiency should also check that their solutions do not open new vulnerabilities.
  • NAND Flash Data Retention Issues: Data-retention errors are the dominant source of flash-memory errors, and refresh needs increase as cells wear out.
  • NAND Flash Data Retention Issues: Variation in flash-cell leakiness enables Retention Failure Recovery, which can reduce bit error rates but may also permit recovery of original data from failed devices.
  • NAND Flash Data Retention Issues: Variation in flash-cell susceptibility to read disturbance may enable probabilistic estimation of original values and create further vulnerabilities.

2) Other Vulnerabilities in NAND Flash Memory:

The paper describes flash-programming vulnerabilities in SSDs and advocates principled, cross-layer methods to anticipate, model, and prevent memory-related security problems. It connects experimental evidence with architectural, design, and testing responses.

  • 2) Other Vulnerabilities in NAND Flash Memory:: Two-step MLC NAND programming exposes intermediate values to disruption from cell-to-cell program interference and read disturbance.
  • 2) Other Vulnerabilities in NAND Flash Memory:: Experiments on contemporary 1Xnm flash chips characterized vulnerabilities that can alter partially programmed data and cause malicious corruption.
  • 2) Other Vulnerabilities in NAND Flash Memory:: Proposed MLC NAND mechanisms mitigate intermediate-value disruption and increase flash lifetime by 16%.
  • Reliability problems in scaled memories can become security problems when they are not anticipated, modeled, accounted for, and corrected.
  • The paper calls for failure modeling based on experimental data from individual devices and larger-scale studies.
  • It advocates co-architecting memory and systems, with principled partitioning of responsibilities across system software, compilers, and applications.
  • Electronic design, automation, and testing should provide predictable failure coverage and work with architectural and cross-stack mechanisms.

V. CONCLUSION

The paper presents RowHammer as a practical security consequence of declining memory reliability under technology scaling. It advocates principled research to anticipate, model, and prevent reliability and security vulnerabilities.

  • RowHammer demonstrates that hardware reliability problems in scaled memory can become practical and widespread system security vulnerabilities.The paper characterizes RowHammer as an example of this broader reliability-to-security failure pattern.
  • The paper surveys the original RowHammer work and the subsequent body of research on the phenomenon and its mitigation mechanisms.The retrospective covers the problem, its context, defenses, and later work built on it.
  • Unanticipated reliability problems discovered in the field can be difficult to defend against while posing serious security risks.The conclusion connects continued scaling toward higher densities with reduced reliability and difficult-to-address vulnerabilities.
  • The paper identifies principled approaches to failure understanding, modeling, prediction, and secure system design, automation, and testing as future research avenues.These approaches target reliable and secure operation in heavily-scaled memory technologies.
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