A Silicon Surface Code Architecture Resilient Against Leakage Errors

1 Introduction

• Silicon spin qubits combine densities as high as 10^9 cm^-2 with the prospect of leveraging the conventional semiconductor industry.The source passage ends mid-sentence after introducing this rationale.Source: §1 · pp. 1–2
• Scaling silicon spin-qubit arrays requires addressing control-line routing, cross-talk, and heat dissipation alongside qubit addressing and readout.The introduction surveys crossbar and shuttling architectures as approaches to these challenges, with trade-offs in control requirements and inter-module operations.Source: §1 · p. 2
• Charge leakage can escape the computational subspace, evade ordinary correction, accumulate, and propagate between dots, making correlated errors especially damaging.Unlike many other leakage types, a leaked charge can move through the quantum-dot array.Source: §1 · p. 2
• The proposed silicon-spin surface-code architecture is designed to be robust against leakage errors and is evaluated for gate- and leakage-error thresholds.The article introduces hardware, analyzes leakage and stabiliser checks, and obtains thresholds.Source: §1 · p. 2

2 Physical Implementation

• Elongated mediator dots mediate data–ancilla interactions and increase spacing for readout devices and electron reservoirs; quantum information resides in data dots.The architecture maps these hardware components onto the surface code.Source: §2 · p. 2, Figure 1 · p. 3

2.1 Data Qubits and Single-qubit Gates

• Data-dot spins use ESR or EDSR control, while strong confinement and Coulomb repulsion suppress extra-electron occupancy in the dots.The cited implementation reports single-qubit control fidelities up to 99.6–99.9%; a 30 nm dot is associated with U ∼2 THz.Source: §2.1 · pp. 2–3

2.2 Ancilla Qubits and Read-out

• Each ancilla is a singlet-initialized electron pair whose singlet–triplet outcome is read through Pauli spin blockade, detectable by charge sensing or dispersive readout.Treating both ancilla dots equally allows parallel data interactions and halves the stabiliser-cycle time.Source: §2.2 · pp. 3–4

2.3 Mediators and Two-qubit Gates

• Even-occupation mediator dots provide exchange between data and ancilla dots without carrying quantum information themselves.For the stated settings, the exchange is 1 MHz when on and 100 Hz when nominally off; the residual-error probability is estimated as approximately 10^-4.Source: §2.3 · pp. 4–5

2.4 Realisations of the Ω≪J and Ω≫J regimes

• The device can realize the Ω≫J regime through data–ancilla field offsets or the Ω≪J regime without micromagnet gradients, with the latter requiring low field or reduced g-factor disorder.Micromagnet gradients support faster EDSR, but the source notes a speed–decoherence balance.Source: §2.3 · p. 5, §2.4 · pp. 5–6

2.5 Charge Reservoirs and Initialisation

• The spacing around mediator dots accommodates reservoirs and planar gate fan-out, with gated reservoir coupling allowing rapid population and slower mediator reset.Reservoir reset can occur during mediator idle periods; the text discusses tuning the coupling to fit within the stabiliser-check schedule.Source: §2.5 · p. 6

3.1 Background

• Leakage means escape from the computational subspace, and ordinary quantum error correction does not correct it directly.In this architecture, the computational subspace has ground charge configurations; data dots allow any spin configuration, while ancilla pairs are restricted to spin zero.Source: §3.1 · pp. 6–7

3.2 Robustness Against Spin Leakage Errors

• Spin leakage is confined to ancillae because data spins remain within the computational subspace, and ancilla reinitialisation removes it each stabiliser round.The authors state that spin leakage therefore does not produce spatially or temporally correlated errors in this architecture.Source: §3.2 · p. 7

3.3 Robustness Against Charge Leakage Errors

• Charge leakage can propagate between qubit dots and cannot be repaired by spin reinitialisation; this section focuses on electrons escaping rather than entering dots.The model treats extra-electron entry as excluded by high repulsion energies in qubit dots.Source: §3.3 · p. 7
• Fast relaxation transfers an electron from a neighbouring mediator into an emptied qubit dot, shifting the charge deficit to the mediator.The authors assume charge relaxation is much faster than gates; the cited measured relaxation time is around 10 ns versus gate times on the microsecond scale.Source: §3.3 · p. 8
• Reservoirs reset mediators after charge transfer, and mediator resets can run during idle periods without adding error-correction runtime.The mediators carry no quantum information, and the proposed approach reuses reservoirs already used for qubit initialization.Source: §3.3 · p. 8

4.1 Surface Code Threshold and Stabiliser Check Circuit

• The circuit omits most explicit Z rotations through virtual phase shifts and removes ancilla Z rotations using symmetric operations on the singlet subspace.Removing single-qubit gates substantially reduces stabiliser-check runtime and depth.Source: §4.1 · p. 9, Figure 3 · p. 9

4.2 Stabiliser Cycle and Error Model

• Four sequential plaquette partitions separate checks sharing no data qubits, while mediator resets during other partitions remove leakage that might persist to a later cycle.The authors state that this arrangement removes spatial and temporal error correlations, making errors in each check Markovian.Source: §4.2 · p. 9, Figure 4 · p. 9
• The error model assumes charge leakage occurs during CZ gates and treats each event as depolarising the entire stabiliser half after mediator restoration.Readout error is assumed equal to p2; one-qubit gates and initialisation use a common depolarising error probability p1.Source: §4.2 · p. 10

4.3 Surface Code Threshold Results

• 0.86% using S gates and 0.76% using √SWAP are the p2 thresholds without charge leakage, comparable to 0.75% for a simple depolarising-noise model.The lower √SWAP threshold is primarily attributed to the additional Zπ needed to construct CZ; gate errors include ancilla spin leakage.Source: §4.3 · p. 10, Figure 5 · p. 11
• 0.27% with S gates and 0.23% with √SWAP are the charge-leakage thresholds at p2 = 0.5%, with both values on the same order as the assumed gate error rate.With no gate errors, the leakage threshold reaches 0.66%; the authors conclude charge leakage can be reduced to computational errors no more damaging than conventional gate errors.Source: §4.3 · pp. 10–11, Figure 6 · p. 12

4.4 Decoherence Errors

• For the parameters considered, 2T2 ≈ 2 × 10^-4 to 10^-3 is well within the per gate error threshold obtained in Section 4.3, according to the authors.The authors conclude that finite spin decoherence times measured in silicon devices to date can be tolerated by their surface code architecture.Source: §4.4 · p. 12

• Fast charge relaxation transfers leaked charge to mediator dots for removal by reservoirs, while single-dot data qubits constrain spin leakage to ancillae.The stabiliser cycle removes correlations in residual physical errors; ancilla reinitialisation removes spin leakage during correction.Source: §5 · pp. 12–13
• 0.66% without gate errors and 0.23–0.27% with 0.5% gate errors are the simulated charge-leakage thresholds, limiting leakage damage to depolarising-noise levels.The stabiliser-check cycle removes time and space correlations in residual computational errors.Source: §5 · p. 13
• Elongated mediators create in-plane room for measuring devices, charge reservoirs, and control lines, while relaxing qubit-dot density.The added space also facilitates CMOS-compatible fabrication.Source: §5 · p. 13
• A stabiliser cycle approaching the MHz domain is expected to suppress environmental decoherence, but mediated exchange is slower than direct exchange.Shuttling spins to mediators could increase speed, although micromagnet-induced gradients may introduce dephasing that is challenging to correct.Source: §5 · p. 13
• The architecture assumes charge relaxation is fast compared with gates; otherwise empty qubit dots may persist after a cycle and cause non-Markovian errors.The authors suggest studying these effects and note that active leakage-detection or leakage-reduction protocols could be used when relaxation is non-negligible.Source: §5 · p. 13
• Shared control lines and modularity could be adopted if quantum-dot inhomogeneity and shuttling noise challenges can be minimized.Source: §5 · p. 13

A.1 Hamiltonian

• The two-spin Hamiltonian separates into Zeeman and exchange terms, with the Zeeman term further split into an average-field component.Source: §A.1 · p. 14

A.2 Ω≪J: simple exchange interaction

• When Ω≪J, exchange has the same form in the rotating and lab frames, and a SWAP-based construction implements CZ.A SWAP corresponds to Jt = π/4.Source: §A.2 · p. 14

A.3 Ω≫J: dipole-dipole interaction

• When Ω≫J, first-order exchange shifts produce a dipole-dipole interaction that commutes with H0, and a CZ can be built from S.Source: §A.3 · p. 14

A.4 Virtual Z gate and symmetric operations on ancilla

• Virtual Z rotations remove most explicit Z gates, but singlet/triplet ancilla measurement bars their use on ancillae; singlet symmetry lets other rotations be moved or omitted.Source: §A.4 · pp. 14–15

• The dipole-dipole CZ takes TJ, while the exchange CZ takes TJ + TZ.The extra TZ is the explicitly implemented Zπ gate required by the exchange construction.Source: §A.5.1 · p. 15

• A full S gate’s Z1Z2 error probability is twice the √SWAP swap-error probability under the described two-stage phase accumulation.Source: §A.5.2 · p. 15
• Higher-order exchange terms shift the exchange strength and can be addressed through careful calibration, while neglected eigenstate perturbations may lead to leakage.Source: §A.5.2 · p. 15
• The S gate also has higher-order corrections from the J ≪ Ω assumption, of magnitude J/Ω.Source: §A.5.2 · p. 15

B.1 General theory

• The general model treats imprecise timing or interaction strength as symmetric over- and under-rotation by ϵ around the intended angle θ = Et.The Hamiltonian is decomposed in its Pauli basis, with real coefficients because H is Hermitian.Source: §B.1 · p. 16

B.1.1 h is unitary

• For unitary h, symmetric over- and under-rotations yield an h error with probability ϵ^2 on top of the intended operation.This includes exchange and dipole-dipole interactions, producing SWAP and Z1Z2 errors, respectively.Source: §B.1.1 · p. 16, §B.2.1 · p. 17, §B.2.2 · p. 17

B.1.2 Twirling

• Twirling leaves Pauli errors whose probabilities follow the Pauli decomposition of h, while non-identity components of the twirled noise scale as O(ϵ^4).Similar channels arise for other symmetric over- and under-rotation distributions centered on the correct rotation angles.Source: §B.1.2 · p. 16

B.2.1 Exchange Interaction

• For exchange interaction, the resulting unitary-error model assigns probability p_sw to a SWAP error on top of the intended exchange operation.The exchange interaction has h = SWAP.Source: §B.2.1 · pp. 16–17

B.2.2 Dipole-dipole Interaction

• For dipole-dipole interaction, the resulting unitary-error model assigns probability p to a Z1Z2 error.The interaction has h = Z1Z2.Source: §B.2.2 · p. 17

C Background exchange interaction

• Mediated exchange suppresses residual exchange and next-nearest-neighbour interactions more strongly than direct exchange, supporting their omission from the analysis.The device parameters can be engineered, and the mediated off-state interaction is more suppressed when tuning on-site energies.Source: C Background exchange interaction · p. 17

D Comparison of leakage resilience to architectures without mediators

• Leakage-reduction units can require many additional ancillae, while data–ancilla swapping depends on charge-reservoir initialization and is incompatible with single-dot data and double-dot ancilla architectures.Integrating reservoirs at every dot is challenging in dense arrays without mediators.Source: D Comparison of leakage resilience to… · p. 17
• Leakage detection can demand extra ancillae or circuit depth, and physical charge detectors face spatial and charge-state discrimination challenges in dense arrays.Shuttling leaked charge back is insufficient because leakage can propagate; correction circuits also assume gates do not induce or transfer leakage.Source: D Comparison of leakage resilience to… · pp. 17–18
• Modular architectures may ease component integration, but shuttling across many dots trades leakage suppression against processing speed and requires additional protection against shuttling leakage.The comparison also notes that direct exchange can have lower leakage probability at similar speed, yet leakage still accumulates without active correction.Source: D Comparison of leakage resilience to… · p. 18
• The proposed architecture handles leakage by resetting idle mediators, without additional components or complex correction schemes.The authors contrast this with leakage-correction approaches that bring runtime, qubit, or integration costs.Source: D Comparison of leakage resilience to… · pp. 17–18

E Resultant Computational Error from Leakage and Restoration

• Leakage and charge restoration during exchange can depolarize the leaked-and-restored qubit and also induce a random depolarising error on its partner.A faulty mediator can participate in the resulting interaction.Source: E Resultant Computational Error from… · p. 18
• A leaked ancilla restored from the mediator used in the next stage can leave that mediator electron random, depolarising the ancilla and the next data qubit during the following interaction.The five-dot example sequences the ancilla’s interactions with D1 and D2 through separate mediators.Source: E Resultant Computational Error from… · p. 18
• The main calculations assume probability 1−2p of no leakage and otherwise full depolarisation of all three qubits, a more severe model than the detailed account.The detailed account gives probability (1−p)^2 of no leakage, with partial or full depolarisation otherwise.Source: E Resultant Computational Error from… · p. 19

F.1 Three-dot system

• In the three-dot system, tunnelling mixes the ground charge configuration with excited charge states, allowing decoherence to produce leakage outside the computational subspace.Perturbation theory relates the excited-state amplitude to t/∆, and leakage is significant during exchange when |∆L,R| is small.Source: §F.1 · p. 19

F.2 Two-dot system

• In the two-dot analysis, the off-diagonal tunnelling term mixes |S⟩ with |ion+⟩, while leaving |T⟩ and |ion−⟩ unchanged.The ratio r is the off-diagonal tunnelling energy t divided by diagonal detuning energy ∆.Source: §F.2 · p. 19

F.2.2 Perturbation theory

• The perturbation-theory analysis distinguishes state changes that produce leakage from ground-state energy changes that produce exchange interaction.The displayed leading energy shift is identified as U.Source: §F.2.2 · p. 20

F.2.3 Leakage oscillation

• Leakage probability has magnitude r^2 and oscillates with frequency U, the leading-order energy difference between the relevant states.Figure 7 plots spin/charge-state probabilities over one exchange-interaction period; its overlapping green and red curves both represent leakage probability.Source: §F.2.3 · p. 20, Figure 7 · p. 20

G Threshold Simulation Details

• Figure 8 presents surface-code leakage-error pleak threshold calculations, assuming use of S-gates; the stated gate-error condition begins with p2 or and is incomplete in the excerpt.Source: Figure 8 · p. 21
• Threshold simulations generate error patterns for X and Z stabiliser checks, repeat measurements for d rounds, and decode the resulting three-dimensional parity grid with MWPM.The simulations assume equal spatial and temporal edge weights; optimising their ratio or using more advanced decoders may improve thresholds.Source: G Threshold Simulation Details · pp. 20–21

H Charge Leakage Threshold Under Different Gate Error Rates

• Table 1 summarizes the charge-leakage threshold pleak under a range of gate-error rates p2.The supplied passages do not include the threshold values.Source: H Charge Leakage Threshold Under… · p. 21
• Figure 8 provides additional plots of the charge-leakage threshold under different gate-error rates.Source: H Charge Leakage Threshold Under… · p. 21
• The table caption states an S-gate error rate of p2, and the stated SWAP-gate error rate is p2/2.Source: Table 1 · p. 21, H Charge Leakage Threshold Under… · p. 21