Establishing the Quantum Supremacy Frontier with a 281 Pflop/s Simulation

Benjamin Villalonga; Dmitry Lyakh; Sergio Boixo; Hartmut Neven; Travis S. Humble; Rupak Biswas; Eleanor G. Rieffel; Alan Ho; Salvatore Mandrà

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Establishing the Quantum Supremacy Frontier with a 281 Pflop/s Simulation

Benjamin Villalonga, Dmitry Lyakh, Sergio Boixo, Hartmut Neven, Travis S. Humble, Rupak Biswas, Eleanor G. Rieffel, Alan Ho, Salvatore Mandrà

arXiv:1905.00444v2May 1, 2019quant-phcs.CCphysics.comp-ph

TL;DR

The paper addresses how to compare NISQ devices with state-of-the-art classical computation for hard random circuit sampling. It develops qFlex, a tensor-network simulator and benchmark framework, achieving 281 Pflop/s on Summit and quantifying large energy differences between quantum and classical systems.

Problem
Comparing NISQ platforms and their progress against classical computing remains challenging, motivating a benchmark based on random circuit sampling and equivalent classical resources.
Method
The paper develops qFlex, a flexible tensor-network simulator for hard random circuits and a systematic NISQ benchmark based on fidelity and equivalent classical metrics.
Results
281 Pflop/s single precision is sustained on Summit, while superconducting quantum computing shows an additional 5 orders of magnitude improvement in energy consumption over Summit in the reported comparison.
Takeaways & Limitations
qFlex can benchmark NISQ devices and classical supercomputers while supporting calibration, performance evaluation, and estimation of quantum-versus-classical computational requirements.

Abstract

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Noisy Intermediate-Scale Quantum (NISQ) computers are entering an era in which they can perform computational tasks beyond the capabilities of the most powerful classical computers, thereby achieving "Quantum Supremacy", a major milestone in quantum computing. NISQ Supremacy requires comparison with a state-of-the-art classical simulator. We report HPC simulations of hard random quantum circuits (RQC), which have been recently used as a benchmark for the first experimental demonstration of Quantum Supremacy, sustaining an average performance of 281 Pflop/s (true single precision) on Summit, currently the fastest supercomputer in the World. These simulations were carried out using qFlex, a tensor-network-based classical high-performance simulator of RQCs. Our results show an advantage of many orders of magnitude in energy consumption of NISQ devices over classical supercomputers. In addition, we propose a standard benchmark for NISQ computers based on qFlex.

I. INTRODUCTION AND MOTIVATIONS

The paper motivates NISQ quantum supremacy and presents qFlex as a classical simulator and benchmark for comparing quantum and classical computation.

Motivation: NISQ devices of about 50–100 qubits may perform tasks surpassing classical high-performance computers, despite supporting only shallow circuits.Fault-tolerant universal quantum computing remains a long-term goal, while current devices operate under noise and limited circuit depth.
Contribution: qFlex uses tensor-network simulation to support large random quantum circuits and systematic NISQ benchmarking.The proposed benchmark compares quantum-device fidelity and equivalent classical computational metrics.
Results: 281 Pflop/s single precision is sustained on Summit with 68% absolute performance efficiency across the entire supercomputer.The implementation reaches 92% peak performance efficiency without mixed-precision acceleration.
Motivation: Random circuit sampling provides a theoretically supported task for comparing quantum processors with classical computation, but its classical simulation cost grows exponentially with qubit count.A 40-qubit output wave function requires 8.8 TB at single precision.
Benchmark scope: Quantum supremacy benchmarking must account for the point at which fidelity estimation and equivalent classical simulation can no longer be performed on the same hard instances.Beyond the threshold, fidelity can be estimated only using easier random-circuit instances.

B. Motivation for RCS as a Standard Benchmark

The paper argues that random circuit sampling is a suitable standard benchmark because it measures multi-qubit computational performance across architectures and relates quantum results to classical resources.

Benchmark goals: RCS is intended to rank NISQ computers and express their computational power through equivalent classical capabilities.The benchmark considers qubits, gates and fidelity, connectivity, multi-qubit operations, and parallel executions.
Benchmark properties: RCS measures NISQ fidelity with cross-entropy benchmarking and works with universal gate sets.The computation is well defined and requires coordinated control of multiple qubits.
Classical comparison: RCS estimates time-to-solution, floating-point operations, and power usage while incorporating the target sampling fidelity into qFlex resource requirements.Its complexity-theoretic basis is intended to resist replacement by an efficient classical algorithm.
Calibration: RCS supports calibration across different qubit subsets and circuit depths, exposing multi-qubit issues such as cross-talk.Other methods can efficiently benchmark restricted gate sets but do not measure computational power.

C. Energy Advantages of Quantum Computing

The paper compares the energy demands of quantum and classical computation and motivates tensor-network simulation as a scalable alternative to full-state simulation for large random circuits.

Energy motivation: 14 MW powers Summit’s 200 Pflop/s double-precision design, making energy availability a constraint on scaling classical HPC systems.A 10x scale-up would require approximately 140 MW.
Quantum systems: Superconducting quantum computers operate at approximately 10–100 kHz circuit execution rates, a necessary input for fair energy comparisons.Their energy use includes refrigeration and electronic control systems.
Classical simulation: Direct full-state simulation becomes impractical near 50 qubits because memory requirements grow as 2^n and node-to-node communication adds overhead.This limitation motivates alternatives such as tensor-network contractions.
Classical simulation: Tensor-network methods represent gates as tensors and contract the resulting network to simulate quantum circuits.One-, two-, and n-qubit gates correspond to rank-2, rank-4, and rank-2n tensors, respectively.
Alternative methods: Hybrid simulation can reduce computation by matching the target fidelity, while cuts introduce costs exponential in the number of entangling gates crossing them.These approaches trade memory and computation through circuit partitioning and fidelity control.

A. qFlex

qFlex is a scalable tensor-contraction simulator designed for hard random circuits, combining communication avoidance, regularized contraction structure, and fidelity-controlled sampling.

Applications: qFlex’s communication-avoiding, memory-conscious design supports benchmarking both NISQ devices and classical high-end parallel computers.Its configurable resource use can match available memory and desired arithmetic intensity.
Design: qFlex is optimized for generic worst-case random circuits and is insensitive to randomness in single-qubit gate choices.This design avoids performance fluctuations between circuits in the same ensemble.
Contraction strategy: Contracting first in the time direction reduces a random circuit to a regular 2D tensor grid suited to cache, vectorization, and parallel hardware.The resulting regularity increases arithmetic intensity for modern classical architectures.
Sampling: Fine-grained tensor cuts balance memory requirements against concurrent computations and allow qFlex to mimic NISQ sampling fidelity.The simulator computes an appropriate fraction of paths to produce samples with a target fidelity.
Performance: 281 Pflop/s single precision is sustained on Summit at 68% efficiency, with 92% peak performance while simulating 49- and 121-qubit square-grid circuits.Earlier simulations reached 20 Pflop/s on NASA systems at 64% efficiency.

A. Systematic tensor slicing technique: Communication avoiding and memory footprint reduction

qFlex uses tensor cuts to reduce memory demands and eliminate inter-process communication, enabling independent, highly parallel contractions of large random quantum circuits.

7 × 7 random quantum circuits exceed terabytes of single-node memory, motivating cuts that limit the memory footprint.
A cut decomposes one tensor contraction into lower-complexity networks covering slices over selected indexes.
Each sliced network can be contracted independently, making the resulting computation embarrassingly parallelizable.
The selected 7 × 7 circuit cut fits six contractions on each Summit node, with one FPR assigned to each GPU.

B. Fast sampling technique

qFlex accelerates random-circuit sampling by recycling expensive intermediate contractions and by trading computed paths or amplitudes against sampling fidelity.

Recycling a large intermediate contraction across many amplitudes reduces sampling time by an order of magnitude for sufficiently deep random circuits.The method contracts tensors for one input subset, reuses the resulting tensor, and varies another subset across amplitudes.
For chaotic random circuits, computing a fraction f of paths simulates noisy amplitudes with fidelity f.
The product of the computed amplitude fraction and its fidelity equals the fidelity of the simulated sampling.
Computing fewer amplitudes at higher fidelity provides an alternative speedup to computing fewer paths.

D. Optimization of the tensor contraction order for optimal time-to-solution

qFlex combines contraction-order optimization, asynchronous heterogeneous execution, and out-of-core decomposition to improve tensor-network time-to-solution on GPUs.

Contraction ordering and cut placement jointly determine flop count and time-to-solution, but finding the optimum is NP-Hard.
Prioritizing a few large, high-arithmetic-intensity contractions often outperforms many smaller contractions.
The TTGT algorithm converts tensor contractions into matrix-matrix multiplications, with optimized transposes limiting overhead for arithmetic-intensive contractions.
The simulations use complex FP32 CGEMM without tensor-core acceleration and normalize tensors to avoid single-precision underflow.
Tensor slicing recursively decomposes contractions that exceed GPU memory into smaller operations on tensor slices.
TAL-SH overlaps asynchronous transfers, tensor transposes, and GEMM execution while managing CPU and GPU resources.

IV. HOW PERFORMANCE WAS MEASURED

Performance was measured from analytical complex-FP32 flop counts and synchronized execution times across Summit simulations, with results reported against GPU peak performance and machine power.

8 times each contraction’s tensor-volume product gives its complex multiply-add flop count.The factor 8 represents four real multiplications plus four real additions.
Initialization, job launching, and final result writing are excluded from reported simulation timings.
Average SP flop/s divides total simulation flops by execution time, while peak SP flop/s uses the largest contraction’s node-scaled performance.
92% peak performance was achieved for large out-of-core contractions, reaching 96% efficiency on some contractions.

B. Sustained performance

qFlex sustains high performance across full-scale Summit simulations, with communication-avoiding execution preserving strong scaling and substantial energy efficiency.

68% sustained performance efficiency corresponds to 281 Pflop/s on 100% of Summit for the 7 × 7 × (1 + 40 + 1) simulation.Less arithmetically intensive tensor contractions limit the average efficiency.
Communication-avoiding execution makes communication impact negligible, keeping performance stable as the node count changes.The resulting behavior demonstrates excellent strong scaling.
34.8 Pflop/s/MW was achieved for the 7 × 7 × (1 + 40 + 1) simulation, versus 35.8 Pflop/s/MW for the 11×11×(1+24+1) simulation.Reported power is an upper bound because it includes the entire machine, including unused components.

VI. IMPLICATIONS AND CONCLUSIONS

The paper positions qFlex and random circuit sampling as tools for benchmarking NISQ devices against classical systems, quantifying computational and energy requirements while defining practical supremacy thresholds.

Benchmarking NISQ devices: qFlex provides a systematic NISQ benchmark that compares quantum and classical computational capability using random circuit sampling.The benchmark measures equivalent classical computation and supports comparisons across architectures.
Benchmarking NISQ devices: qFlex calculates the fidelity, qubit count, and gate depth required for a quantum computer to exceed the most powerful available supercomputer on random circuit sampling.The paper notes that the quantum supremacy demonstration of Ref. surpasses this threshold.
Benchmarking NISQ devices: Random circuit sampling enables objective comparison of quantum architectures by relating qubit number, gate types, fidelity, connectivity, and execution parallelism to classical metrics.The comparison includes architectures such as ion traps and superconducting qubits.
Near-term design guidance: The proposed benchmark establishes a multi-qubit comparison framework for non-Clifford devices and allows vendors to calibrate NISQ hardware through cross-entropy benchmarking.qFlex enables XEB at large qubit counts and circuit depths.
Classical architecture and energy comparisons: qFlex enables cross-architecture comparisons of classical simulation, including NASA Electra’s Intel Skylake CPUs and ORNL Summit’s NVIDIA Volta GPUs.The comparison uses random circuit sampling as a common task.
Classical architecture and energy comparisons: Sampling 10^6 bitstrings required 96.8 MWh on Electra and 21.1 MWh on Summit, while a 10 kHz superconducting quantum computer offered an additional 5 orders of magnitude in energy improvement.The authors caution that random circuit sampling is particularly favorable to quantum computers and that this advantage does not currently generalize to most other problems.
Near-term design guidance: qFlex supports near-term algorithm and hardware design by verifying implementations, evaluating algorithms, and identifying suitable architectures when full-state simulation is infeasible.For random circuit sampling, qFlex computes amplitudes of selected outputs for rejection sampling.

APPENDIX A. Comparison with variable elimination algorithms

The appendix estimates variable-elimination simulation costs using graph representations, projected variables, and calibrated benchmark constants. qFlex is compared with these estimates under Summit-equivalent computational resources and circuit complexities.

Algorithm: Tensor-network contraction is represented as an undirected graphical model whose vertices are binary indices and whose cliques encode shared tensors.Variable elimination contracts indices by eliminating variables and forming new cliques.
Algorithm: The contraction width is the largest clique formed during elimination, and the largest tensor size scales as 2^contraction width.Elimination time is dominated by the largest resulting clique, while minimizing width is an NP-hard treewidth problem.
Algorithm: Projecting variables can reduce computational resources by splitting the simulation into subgraphs, at the cost of doubling the number of contractions per projected variable.The appendix uses a heuristic projected-variable selection procedure based on prior benchmarks.
Algorithm: The simulated circuits have contraction complexity between Bristlecone depths (1 + 32 + 1) and (1 + 40 + 1) under the referenced projection algorithm.The comparison uses contraction widths as a function of the number of projected variables.
Methodology: D = 52.7 MHz is selected to calibrate runtime estimates from Bristlecone benchmarks using 127,512 CPU cores.The value is chosen because it produces slightly lower computation times than the alternative calibrated constant.
Methodology: The Summit-equivalent comparison models 4,600 Summit nodes as ncores = 2,595,377 CPU cores based on delivered FLOPs.The mapping equates the estimated variable-elimination simulator with the full Summit machine in peak computational capability.

3) Results:

qFlex outperforms the compared variable-elimination simulator on the evaluated circuits, using less memory. The runtime comparison is optimistic for variable elimination because it omits batching penalties and assumes efficient GPU implementation.

Results: qFlex is somewhat faster and requires about half the memory for the 7 × 7 × (1 + 40 + 1) circuit.The comparison concerns sampling 1M bitstrings at fidelity 0.5%.
Results: qFlex is about 3× faster and halves memory requirements for the 11 × 11 × (1 + 32 + 1) circuit.The reported comparison is against the variable-elimination simulator of Refs. [30], [61].
Results: Variable-elimination runtime estimates omit the 3–10× sampling-time increase associated with the inability to compute correlated amplitude batches at the cost of a single amplitude.Including this factor would increase the estimated runtimes for variable elimination.
Results: The comparison also assumes that variable elimination can be implemented efficiently on GPUs despite the low arithmetic intensity of contracting variables one at a time.This assumption is identified as optimistic in the runtime estimates.