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Expressibility and entangling capability of parameterized quantum circuits for hybrid quantum-classical algorithms

Sukin Sim, Peter D. Johnson, Alan Aspuru-Guzik

arXiv:1905.10876v1quant-ph

TL;DR

Parameterized quantum circuits must balance solution-space coverage against circuit depth and parameter count, but effective circuit characteristics remain insufficiently understood. This paper introduces statistically estimable expressibility and entangling-capability descriptors and applies them to circuit structures, gate choices, connectivity, and depth. The simulations identify favorable fragments, including CRX-based sequences and ring or all-to-all two-qubit arrangements, while showing that expressibility saturates at template-dependent rates and values.

  • Problem

    Choosing compact parameterized circuits that represent solution spaces effectively remains difficult because the characteristics of an effective training circuit are not generally understood.

  • Method

    The paper defines expressibility and entangling capability and estimates them from classical simulations of sampled parameterized quantum-circuit states across gate and connectivity configurations.

  • Results

    CRX circuits showed more favorable expressibility and entangling capability than corresponding CRZ circuits, while all-to-all connectivity produced the most favorable expressibility and expressibility saturated at template-dependent depths and values.

  • Takeaways & Limitations

    Saturation rate and saturated value, together with gate choice and two-qubit connectivity, may help design and select parameterized circuits for applications.

Abstract

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Parameterized quantum circuits play an essential role in the performance of many variational hybrid quantum-classical (HQC) algorithms. One challenge in implementing such algorithms is to choose an effective circuit that well represents the solution space while maintaining a low circuit depth and number of parameters. To characterize and identify expressible, yet compact, parameterized circuits, we propose several descriptors, including measures of expressibility and entangling capability, that can be statistically estimated from classical simulations of parameterized quantum circuits. We compute these descriptors for different circuit structures, varying the qubit connectivity and selection of gates. From our simulations, we identify circuit fragments that perform well with respect to the descriptors. In particular, we quantify the substantial improvement in performance of two-qubit gates in a ring or all-to-all connected arrangement compared to that of those on a line. Furthermore, we quantify the improvement in expressibility and entangling capability achieved by sequences of controlled X-rotation gates compared to sequences of controlled Z-rotation gates. In addition, we investigate how expressibility "saturates" with increased circuit depth, finding that the rate and saturated-value appear to be distinguishing features of a parameterized quantum circuit template. While the correlation between each descriptor and performance of an algorithm remains to be investigated, methods and results from this study can be useful for both algorithm development and design of experiments for general variational HQC algorithms.

I. PARAMETERIZED QUANTUM CIRCUITS

Parameterized quantum circuits are tunable unitaries whose structures vary by application, motivating operational descriptors that quantify circuit capabilities independently of a specific algorithm. Expressibility is constructed by comparing sampled PQC states with Haar-random states through fidelity statistics and frame potentials.

  • A parameterized quantum circuit is a tunable unitary Uθ applied to a reference state, producing a parameterized quantum state.
  • PQC parameters are optimized classically from objective-function measurements obtained by executing the circuit on a quantum computer.
  • The framework characterizes PQCs through operational descriptors rather than generating pseudorandom circuits, supporting comparisons of circuit capability.
  • Expressibility measures how well a circuit generates pure states representative of the Hilbert space, using Haar-random states as the reference ensemble.
  • The expressibility construction samples parameters uniformly, compares induced state distributions with Haar statistics, and uses frame potentials derived from overlap moments.

1. Estimating expressibility

Expressibility is estimated by comparing fidelities from independently sampled PQC state pairs with the fidelity distribution of Haar-random states. The resulting KL divergence gives an operational score, with lower values indicating greater expressibility.

  • Expressibility estimation samples pairs of parameterized states and compares their fidelity distribution with the analytical Haar-random fidelity distribution.
  • The Haar fidelity density is PHaar(F) = (N −1)(1 −F)N−2, where F is fidelity and N is the Hilbert-space dimension.
  • The PQC fidelity distribution is estimated with a histogram because the method uses a finite sample of state fidelities.
  • Lower KL divergence between the estimated PQC and Haar fidelity distributions indicates more favorable expressibility.
  • Expressibility quantifies the information lost when the PQC fidelity distribution is approximated by the Haar distribution, although zero divergence has not been proven equivalent to Haar sampling.

2. Expressibility: single qubit demonstration

A single-qubit demonstration compares circuits with different abilities to explore the Bloch sphere using sampled states, fidelity histograms, and frame-potential estimates. More expressible circuits have lower KL divergence and frame potentials closer to Haar values.

  • The single-qubit examples range from an idle circuit to circuits with progressively greater ability to explore the Bloch sphere.
  • Circuit A explores only around the equator, whereas Circuit B gains broader coverage through an additional X-rotation degree of freedom.
  • Figure 1 compares four circuit types using sampled Bloch-sphere states, fidelity histograms, and frame-potential estimates against Haar-distributed states.
  • The idle circuit has an expected KL divergence of ln(75) ≈4.3, while lower KL divergence denotes more favorable expressibility.
  • More expressible circuits show frame-potential values lower or closer to the corresponding Haar-distributed ensemble values.

B. Entangling capability

Entangling capability measures a parameterized circuit’s ability to generate entangled states independently of the target problem. The study uses the scalable Meyer-Wallach measure for pure states, while acknowledging that it does not fully characterize entanglement.

  • Low-depth entangling circuits can efficiently represent solution spaces and capture nontrivial correlations in quantum data.
  • Entangling capability is defined as a circuit’s ability to generate entangled states independently of the problem being solved.
  • The Meyer-Wallach measure Q is used as a scalable, easily computed global measure of multipartite entanglement for pure states.
  • The selected entanglement measure is only one method and does not fully characterize entanglement in the system.

1. Meyer-Wallach measure

The Meyer-Wallach measure Q quantifies entanglement using generalized distances between reduced state components. It ranges from 0 for product states to 1 for maximally characterized examples, but does not distinguish all entanglement types.

  • The generalized distance D is the squared area of the parallelogram formed by vectors |u⟩ and |v⟩.
  • Q is invariant under local unitaries and satisfies 0 ≤ Q ≤ 1.
  • Q equals 0 exactly for product states, while representative entangled states can attain Q = 1.
  • Q is also the average linear entropy of all single-qubit reduced states.
  • The measure is relatively undiscerning: distinct entanglement structures, including a two-term state and a four-qubit GHZ state, can both have Q = 1.
  • The authors nevertheless use Q because it has served as an effective entanglement probe across quantum-information applications.

2. Estimating entangling capability

Entangling capability is estimated as the average Meyer-Wallach entanglement of states generated by sampled circuit parameters. The comparison also tracks implementation and optimization costs relevant to near-term hybrid algorithms.

  • Entangling capability is the average Meyer-Wallach Q value over states produced by a parameterized circuit.
  • The estimate samples parameter vectors and computes the sample average of the output states’ Meyer-Wallach measures.
  • A circuit producing only product states scores 0, whereas one consistently producing highly entangled states scores close to 1.
  • Circuit comparisons account for depth, connectivity, parameter count, and the number of two-qubit operations.
  • Nearest-neighbor, ring, and all-to-all two-qubit connectivities are considered, with parameter count serving as a rough optimization-difficulty measure.

III. NUMERICAL EXPERIMENTS

Numerical experiments evaluate expressibility and entangling capability across four-qubit circuit templates with varied gates, connectivity, and repeated layers. The results show strong dependence on circuit structure, topology, and depth, alongside a cost–performance trade-off.

  • III. NUMERICAL EXPERIMENTS: The simulations evaluate four-qubit templates composed of different single- and two-qubit gate configurations, using RX, RY, and RZ parameterized gates.
  • III. NUMERICAL EXPERIMENTS: 5000 state fidelities are sampled per circuit instance, with unit layers repeated up to Lmax = 5 to estimate expressibility.
  • A. Expressibility observations: Circuits 17, 4, and 11 reach expressibility near 0.09 and outperform circuit 15, potentially because they use parametric two-qubit gates instead of static CNOTs.
  • A. Expressibility observations: Circuits 5, 13, 14, and 6 have favorable expressibility with DKL < 0.02, while circuit 6 is most expressible at L = 1 but costly in depth and parameters.
  • A. Expressibility observations: Adding layers generally improves expressibility, but rates differ: fourteen of nineteen templates improve by more than 60% from L = 1 to L = 2.
  • A. Expressibility observations: Circuit 11 catches up to circuit 6 after three layers, illustrating that a less favorable shallow template can become competitive through multi-layering.

B. Entangling capability observations

Entangling capability varies with circuit structure and depth: local-only circuits cannot generate entanglement, while deeper circuits can approach Haar-random-state behavior and selectively sample highly entangled states.

  • Circuit 1 has zero entangling capability because it contains only local unitaries.
  • Circuit 9’s expressibility increases monotonically with circuit layers, while other circuits’ mean Q values approach the Haar-random-state average.
  • For circuit 9, increased depth improves expressibility, whereas entangling capability can oscillate while converging toward the Haar mean.
  • Some circuits selectively explore highly entangled regions of Hilbert space rather than sampling states uniformly across it.

C. Cost estimate observations

The study evaluates circuit cost through parameters, two-qubit operations, depth, and connectivity, then compares these costs with descriptor quality and saturation behavior to guide compact circuit selection.

  • Circuit costs are estimated using depth, the number and topology of two-qubit gates, and the number of parameters.
  • Nearest-neighbor templates map naturally to linear qubit arrays, whereas other templates use ring or non-local interactions for hardware supporting them.
  • Circuits 5 and 6 have favorable expressibility and entangling capability but require many parameters and two-qubit gates, greater depth, and higher connectivity.
  • Circuits 11, 12, and 19 become comparable to circuits 5 and 6 with added layers while maintaining more reasonable circuit costs.
  • Expressibility saturation: Each circuit has a depth beyond which expressibility saturates, with different templates reaching different layer numbers and saturation values.
  • Expressibility saturation: To maximize expressibility at low depth, choose a circuit that avoids a poor saturation value and use layers below its saturation point.
  • Expressibility saturation: Adding layers increases both depth and parameters, which can enlarge the explored state manifold but make optimization more challenging.
  • Types of two-qubit operations: CRX-based circuit pairs have more favorable expressibility and entangling capability than corresponding CRZ-based pairs.

CRZ CRX

The paper compares controlled-Z and controlled-X rotations and evaluates nearest-neighbor, circuit-block, and all-to-all two-qubit arrangements using expressibility, entangling capability, and implementation cost.

  • CRZ and CRX: Table II reports descriptors for six n = 4, L = 1 circuit pairs using identical templates with either CRZ or CRX two-qubit operations.
  • Two-qubit configurations: All-to-all gives the lowest KL-divergence expressibility, while circuit-block is close and nearest-neighbor has the worst expressibility.
  • Two-qubit configurations: Table III compares n = 4 circuits using nearest-neighbor, circuit-block, and all-to-all two-qubit configurations.
  • Two-qubit configurations: All-to-all provides favorable expressibility and entangling capability but requires greater parameters, depth, and qubit connectivity; circuit-block is a cheaper alternative.
  • Descriptor–cost trade-offs: The circuit landscape can expose descriptor–cost trade-offs, such as choosing circuit 6 for expressibility or circuit 14 for fewer parameters and lower depth.
  • Limitations: As system size grows, estimating descriptors requires many more state samples because expected state overlap decreases exponentially with qubit number.

V. CONCLUSION AND OUTLOOK

The paper presents a framework for comparing parameterized quantum circuits independently of algorithm or application, while identifying descriptor-based design opportunities and unresolved links to algorithm performance.

  • The framework characterizes and compares parameterized quantum circuits independently of the algorithm or application.
  • Expressibility can saturate with sufficient circuit depth, and its saturation rate and value may help guide circuit design and selection.
  • The descriptors identify useful circuit fragments involving both gate choice and two-qubit-operation configuration, including arrangements natural for particular hardware.
  • A deeper benchmark study is still needed to quantify correlations between expressibility and algorithm-specific performance metrics such as energy errors or function evaluations.
  • Descriptor generalization to subspace expressibility may be needed when circuits are designed to output states only within a proper particle-number subspace.
  • The descriptors have so far been explored only through pure-state classical simulations, motivating noisy simulations and experimental estimation protocols.
  • Expressible circuits must be used carefully because random starting points in VQE can encounter barren-plateau-related optimization difficulties.

APPENDIX

The appendix tests descriptor estimation and expressibility saturation across larger circuits, sample sizes, and depths, revealing distinct saturation behaviors and connectivity-related trade-offs.

  • Appendix: n = 6 and n = 8 qubit instances are evaluated at depths L = 1 and L = 2 for expressibility and entangling capability.
  • Appendix: Consistent descriptor trends across qubit numbers may allow smaller-circuit simulations to inform expectations for larger instances.
  • Appendix: 5000 pairs of states provide approximately 0.1 relative precision for mean fidelities and 0.07 for average MW measure, each with 98% confidence.
  • Appendix: Expressibility estimation shows pronounced bias at low sample sizes, while descriptor estimates converge as the sample size increases.
  • Appendix C: Expressibility saturation: Expressibility saturation differs in both rate and saturated value across circuit templates.
  • Appendix C: Expressibility saturation: Circuits 6, 10, and 15 saturate near the first layer, but circuits 10 and 15 reach less favorable expressibility values than circuit 6.
  • Appendix C: Expressibility saturation: Circuits 11 and 12 reach favorable expressibility using 10–20 nearest-neighbor two-qubit operations, whereas circuit 6 does so in one layer with 12 operations including non-local gates.
  • Appendix: Finite sampling biases expressibility estimates even when the true Haar-distribution value is zero, as illustrated by the 5000-sample estimator bias.
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