Source-linked AI summary
In-memory hyperdimensional computing
Geethan Karunaratne, Manuel Le Gallo, Giovanni Cherubini, Luca Benini, Abbas Rahimi, Abu Sebastian
TL;DR
HDC offers a robust, memory-centric approach for learning and classification, but prior memristive implementations were limited in scope and hardware scale. This paper develops a complete in-memory HDC system using memristive crossbars and CMOS logic, and experimentally demonstrates software-comparable accuracy across prototypical tasks using 760,000 PCM devices.
Problem
Prior memristive HDC architectures supported limited applications and relied on small prototypes or costly repeated device programming, motivating a more complete in-memory system.
Method
The paper implements HDC encoding and associative-memory search across two planar memristive crossbars with peripheral CMOS circuits, including in-memory binding and dot-product operations.
Results
Comparable accuracies to software baselines were achieved across three classification tasks using 760,000 phase-change memory devices performing analog in-memory computing.
Takeaways & Limitations
HDC robustness enables approximate analog in-memory operations without significantly degrading output accuracy, supporting a complete memristive HDC implementation.
Abstract
from arXiv · showhide
Hyperdimensional computing (HDC) is an emerging computational framework that takes inspiration from attributes of neuronal circuits such as hyperdimensionality, fully distributed holographic representation, and (pseudo)randomness. When employed for machine learning tasks such as learning and classification, HDC involves manipulation and comparison of large patterns within memory. Moreover, a key attribute of HDC is its robustness to the imperfections associated with the computational substrates on which it is implemented. It is therefore particularly amenable to emerging non-von Neumann paradigms such as in-memory computing, where the physical attributes of nanoscale memristive devices are exploited to perform computation in place. Here, we present a complete in-memory HDC system that achieves a near optimum trade-off between design complexity and classification accuracy based on three prototypical HDC related learning tasks, namely, language classification, news classification, and hand gesture recognition from electromyography signals. Comparable accuracies to software implementations are demonstrated, experimentally, using 760,000 phase-change memory devices performing analog in-memory computing.
I. INTRODUCTION
HDC uses high-dimensional, distributed hypervectors to represent and classify data, making it robust to defects and well suited to in-memory computing. The paper develops a complete memristive implementation that performs encoding and associative-memory search in or near memory.
- HDC framework: HDC represents symbols with high-dimensional, pseudorandom hypervectors whose component-wise operations preserve dimensionality and produce quasiorthogonal representations.The framework uses binding, bundling, and permutation to construct new d-dimensional hypervectors.
- Motivation: HDC is intrinsically robust because failures in individual hypervector components do not propagate through its distributed representations.This robustness, together with memory-centric manipulation of large patterns, motivates implementation with nanoscale memristive devices.
- Proposed system: The proposed system implements HDC operations on two planar memristive crossbars with peripheral CMOS, using in-memory read logic for binding and dot products for associative-memory search.The encoder forms query or prototype hypervectors, which are compared against stored class prototypes in associative memory.
- Motivation: Prior memristive HDC architectures were limited to narrow tasks and small simulated or emulated hardware, with repeated device programming creating endurance concerns.Earlier systems included single-language or restricted binary classification and prototypes as small as 256 ReRAM cells.
- HDC pipeline: The system maps item and associative memories onto crossbars, encodes n-grams and class prototypes from basis hypervectors, then classifies queries by maximum similarity to stored prototypes.Binding is represented as component-wise exclusive-NOR, bundling as majority-based addition, and permutation as pseudorandom coordinate shuffling.
- Validation: The complete architecture is designed to balance implementation complexity and output accuracy and is validated with PCM hardware and a 65 nm CMOS system-level design.The paper describes prototype-chip validation alongside synthesis of the full architecture.
III. THE ASSOCIATIVE MEMORY SEARCH MODULE
The associative memory module performs HDC classification by comparing query and prototype hypervectors with in-memory dot products, while coarse-grained randomization mitigates deterministic PCM variations. Across three datasets, partitioning improves accuracy, with dotp offering a lower-cost trade-off than invHamm.
- Associative memory search: Classification compares query and prototype hypervectors using inverse Hamming distance or a dot-product similarity metric.Inverse Hamming distance is decomposed into two dot-product terms; because hypervectors contain nearly equal zeros and ones, dotp can also serve as the similarity metric.
- Associative memory search: Two PCM crossbar arrays store prototype hypervectors and their complements for in-memory similarity computation.The query hypervector and its complement are applied as voltages, and peripheral adders plus a winner-take-all circuit select the most similar class.
- Variation mitigation: Classification accuracy increases with the number of randomized partitions under both dotp and invHamm simulations.The randomization strategy addresses deterministic spatial conductance variation in the crystalline PCM state.
- Variation mitigation: 82.5% to 96%: language-classification accuracy improves with dotp when the partition factor increases from 1 to 10.The cited result is for dotp on the language task.
- Results and trade-offs: The experimental on-chip accuracy is close to the 10-partition simulation and software baseline across both similarity metrics and all three datasets.InvHamm provides slightly higher accuracy at the same partition size but nearly doubles area and energy consumption, making dotp with partition factor 10 a low-power trade-off.
IV. THE N-GRAM ENCODING MODULE
The n-gram encoding module rewrites the standard representation into minterms for in-memory logical operations, then uses a fixed 2-minterm approximation to reduce hardware cost. Simulations evaluate this approach on language and news classification, while EMG encoding is excluded because its spatial hypervectors do not fit a practical fixed item memory.
- Evaluation: Figure 3 compares 2-minterm and all-minterm classification performance for language classification with n = 4 and news classification with n = 5.The figure also depicts mapping basis hypervectors and their complements to two crossbar arrays and generating the approximated n-gram hypervector.
- Minterm formulation: The standard n-gram representation is rewritten as a component-wise sum of 2^n−1 minterms to enable hardware-friendly in-memory operations.The minterm representation maps onto memristive crossbars using in-memory bitwise AND operations.
- Minterm formulation: 2^n−1 −1 minterms grow exponentially with n, making all-minterm hardware computations costly and motivating a fixed-minterm design.The stated goal is to reduce the number of minterms independently of n.
- 2-minterm encoding: For even n, a 2-minterm approximation is available and is used for in-memory HDC.The approximation is implemented by programming basis hypervectors and complements on two crossbars and applying component-wise logical AND operations in memory.
- Evaluation: Simulations implement both the encoder and associative memory with modeled PCM crossbars for inference on the language and news datasets.The EMG dataset is excluded because spatially encoded hypervectors cannot be mapped entirely into a fixed item memory of reasonable size.
V. THE COMPLETE IN-MEMORY HDC SYSTEM
The complete in-memory HDC system combines a 2-minterm encoder with associative-memory search using a dot-product metric, and evaluates software, PCM-model, and on-chip inference. The architecture trades classification accuracy against hardware complexity while improving energy efficiency and area relative to an all-CMOS design.
- Architecture: The architecture uses a 2-minterm encoder and dot-product associative-memory search with partition factor f = 10.It comprises three PCM crossbar arrays and peripheral buffers, bundling, comparison, and control circuits.
- Inference: Inference generates query hypervectors through encoding and then performs associative-memory search using two in-memory computing primitives.The prototype hardware stores item-memory and associative-memory components in PCM devices before inference.
- Accuracy evaluation: Figure 4b compares classification accuracy for software, a PCM statistical model, and on-chip experiments on language and news benchmarks.The full-chip experiment shows similar accuracy to the earlier on-chip associative-memory experiment and close accuracy to software under the same model configuration.
- Hardware efficiency: 6.01× improvement in total energy efficiency and 3.74× reduction in area are obtained with PCM crossbar modules versus an all-CMOS implementation.The encoder’s query-processing energy also decreases by a factor of 3.5.
VI. CONCLUSION
The paper presents in-memory HDC as a brain-inspired framework implemented with memristive devices for memory-centric computation. Its prototype achieves software-comparable accuracy across language and news classification while supporting programmable representations and task configurations.
- System contribution: The system performs HDC’s main computations in memristive memory using logical and dot-product operations.Its two main components are an encoder and an associative-memory search engine.
- Programmability: The architecture supports different hypervector representations, dimensionalities, input-symbol counts, and output-class counts.This programmability is intended to accommodate a variety of applications.
- Results: Software-comparable accuracies were obtained on language and news classification using 10,000-dimensional hypervectors.The experiments used a prototype PCM chip, described as the largest experimental demonstration of HDC with memristive hardware to date.
- Future direction: Future work extends in-memory HDC toward advanced cognitive tasks, data compression and retrieval, and more power-efficient peripheral hardware.These directions are stated as goals beyond learning and classification.
PCM-based hardware platform
The experimental platform centers on a 90 nm CMOS prototype PCM chip and supporting analog, FPGA, and host-control electronics. The chip integrates large-scale PCM storage with circuitry for addressing, programming, and readout.
- Chip platform: The prototype PCM chip integrates d-GST PCM cells with addressing, on-chip ADC readout, and voltage- or current-mode programming in 90 nm CMOS.The broader platform also includes analog-front-end and FPGA boards.
- Support electronics: The analog-front-end board provides DACs, power supplies, and voltage and current reference sources.
- Support electronics: The first FPGA board performs data acquisition and digital interfacing between the PCM device, analog-front-end electronics, and control logic.
- Support electronics: A second FPGA board with an embedded processor and Ethernet connection manages system control, data management, and host-computer interfacing.
- PCM array: 3 million PCM cells are organized in a 512-word-line by 2048-bit-line array and read through an 8-bit on-chip ADC.Selected cells are biased at 300 mV during readout, with current integrated by a capacitor.
Datasets to evaluate in-memory HDC
The evaluation benchmarks cover language classification, news classification, and hand-gesture recognition from EMG signals. Together, they vary inputs, classes, data types, and hyperparameters for testing a programmable in-memory HDC architecture.
- Benchmark tasks: The benchmark suite contains three learning and classification tasks: language classification, news classification, and EMG-based hand-gesture recognition.The tasks require support for different numbers of inputs, classes, and data types.
- Language classification: Language classification uses 22 European languages, with Wortschatz text for training and 1,000 Europarl sentences per language for testing.The item memory contains 27 symbols: the 26 Latin letters plus whitespace.
- News classification: News classification uses Reuters articles spanning 8 genres, with more than 5,400 training documents and more than 2,100 testing documents.The preprocessing removes frequent stop words and words shorter than three letters.
- News classification: The news experiments use dimensionality d = 10,000 and n-gram size n = 5 with a 27-symbol item memory.Documents in each class are merged into a single training text.
- EMG gesture recognition: EMG data are sampled at 500 Hz from four forearm-muscle channels, with each channel quantized into 22 intensity levels.The task assigns a label to each time sample.
- Architecture configurations: The task configurations vary hypervector dimension, alphabet size, n-gram size, and class count, while EMG encoding uses item and continuous item memories.Hardware item and associative memories may be distributed across narrower crossbars when electrical or physical limits require it.
Coarse grained randomization
The associative-memory search uses coarse-grained randomized partitioning to distribute prototype subvectors across crossbar partitions and collect query partial dot products during inference.
- Coarse grained randomization: Prototype hypervectors are split into f equal-length subvectors, and the crossbar is divided into f partitions with d/f rows and c columns.Each partition stores one subvector from every class.
- Coarse grained randomization: A random permutation e of the c classes determines the column order for programming subvectors in each partition.The same procedure is repeated across all partitions.
- Coarse grained randomization: During inference, the query hypervector is split into f subvectors, translated into voltage levels, and applied to the crossbar partitions.Enabled bitlines produce class-specific partial dot products that are accumulated in destination buffers.
Experiments on associative memory search
Associative-memory prototypes are trained in software, programmed onto a PCM chip, and searched by analog in-memory dot products during inference.
- Experiments on associative memory search: Prototype hypervectors for language, news, and EMG tasks are learned in software before being programmed onto the prototype PCM chip.Language and news use XOR-based encoding with n = 4 and n = 5, while EMG uses spatial and temporal encoding.
- Experiments on associative memory search: The invHamm experiment allocates d × c × 2 PCM devices for prototype and complementary prototype hypervectors.The first d × c devices store prototype components, while the second half stores complementary components.
- Experiments on associative memory search: Only Section III experiments generate query hypervectors with the software HD encoder used for training.Section V instead generates queries with in-memory encoding using the prototype PCM chip.
- Experiments on associative memory search: Query components valued 1 trigger 300 mV reads on stored prototype components, implementing analog multiplications for in-memory dot products.The complementary query is processed similarly on complementary prototype devices.
More details on the 2-minterm encoder
The 2-minterm encoder generates n-gram hypervectors over n cycles, combines two minterm paths with an OR array, and binarizes accumulated outputs.
- More details on the 2-minterm encoder: During each cycle, the encoder activates the selected symbol and crossbar gate lines to begin n-gram encoding.The stored left-side minterm value is expressed as a product over permuted basis hypervectors.
- More details on the 2-minterm encoder: The complementary product is stored in right-side minterm buffers, producing two minterms by the end of the n-th cycle.Matching indices from both minterm vectors are passed to the OR gate array.
- More details on the 2-minterm encoder: The OR gate array outputs the desired n-gram hypervector from the two minterm vectors.This implements the 2-minterm n-gram encoding described for the hardware encoder.
- More details on the 2-minterm encoder: After encoding, generated n-grams are accumulated and binarized inside the bundler module.The binarization threshold is defined for the sum hypervector components.
- More details on the 2-minterm encoder: The threshold expression uses l for sequence length, n for n-gram size, and k for the number of binding-operation minterms.These parameters determine the threshold applied during bundling.
Experiments on the complete in-memory HDC system
The complete in-memory HDC experiments combine PCM storage and in-memory encoding with software-emulated peripheral operations, then benchmark the architecture against a CMOS design.
- Experiments on the complete in-memory HDC system: For complete-system experiments, software training uses 2-minterm encoding with n = 4 for language and n = 5 for news.The resulting representations are used for subsequent PCM-based inference.
- Experiments on the complete in-memory HDC system: The PCM chip stores IM, complementary IM, and associative-memory prototypes using separate device allocations.IM and complementary IM are programmed in a single shot with RESET/SET pulses for binary components.
- Experiments on the complete in-memory HDC system: During inference, IM and complementary IM are read from PCM, while in-memory AND is emulated by software thresholding of on-chip ADC currents.Other unsupported encoder operations, including a 1-bit right shift, are handled outside the prototype PCM logic.
- Experiments on the complete in-memory HDC system: A cycle-accurate RTL model of an equivalent-throughput CMOS design is synthesized in UMC 65 nm technology to benchmark energy efficiency.The model is verified with a testbench before synthesis.
- Experiments on the complete in-memory HDC system: The proposed architecture’s energy and area combine common CMOS modules with PCM crossbars and exclusive analog/digital peripheral circuits.PCM-exclusive estimates use parameters from the 90 nm prototype chip and include estimated sense-amplifier parameters.