Source-linked AI summary
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM
K. Garello, F. Yasin, H. Hody, S. Couet, L. Souriau, S. H. Sharifi, J. Swerts, R. Carpenter, S. Rao, W. Kim, J. Wu, K. K. V. Sethu, M. Pak, N. Jossart, D. Crotti, A. Furnémont, G. S. Kar
TL;DR
The paper addresses field-free switching for manufacturable SOT-MRAM. It introduces a magnetic-hard-mask integration approach and demonstrates reliable sub-ns switching, including 300 ps operation and endurance to 10^11 cycles at 1 ns.
Problem
Field-free switching must be integrated into SOT-MRAM while preserving manufacturability and device performance.
Method
A magnetic hard mask embedded in the SOT hard-mask module generates a homogeneous in-plane field on the free layer using a CMOS-compatible integration approach.
Results
FFS devices switch reliably down to 300 ps, with 1 ns endurance up to 10^11 cycles and stable SOT and MTJ resistances.
Takeaways & Limitations
The integration-friendly design preserves sub-ns writing and low-energy performance, supporting SOT-MRAM development for low-level-cache applications.
Abstract
from arXiv · showhide
We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOS-compatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development.