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High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS

Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo

arXiv:1909.07514v1cs.ETcs.NE

TL;DR

Large DNNs stress hardware memory and communication, while SRAM density, leakage, and row-by-row access constrain memory capacity and parallelism. XNOR-RRAM integrates a 128×64 RRAM array with CMOS peripherals and flash ADCs; prototype measurements report high binary-DNN accuracy, 24 TOPS/W, and 158 GOPS.

  • Problem

    Large DNNs create hardware challenges in computation, memory, and communication, while SRAM density, leakage, limited capacity, and row-by-row operation constrain implementation.

    Source: Introduction · p. 2

  • Method

    XNOR-RRAM uses binary RRAM bitcells and a monolithically integrated array with CMOS peripherals to perform binarized DNN in-memory computing.

    Source: Introduction · p. 4, Discussion · p. 13

  • Results

    Prototype measurements report 24 TOPS/W, 158 GOPS, 98.5% MNIST accuracy, 83.5% CIFAR-10 accuracy, and 3.2X EDP and 14.1X ED2P improvements over state-of-the-art literature.

    Source: Discussion · p. 14

  • Takeaways & Limitations

    The monolithically integrated array and peripheral circuits demonstrate scalability of XNOR-RRAM toward large-scale deep neural networks.

    Source: Discussion · p. 13

    The current design supports only binarized DNNs; multi-bit precision could use bit-serial operation and additional digital peripherals or DACs, at the cost of energy-efficiency.

    Source: Discussion · p. 14

Abstract

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Deep learning hardware designs have been bottlenecked by conventional memories such as SRAM due to density, leakage and parallel computing challenges. Resistive devices can address the density and volatility issues, but have been limited by peripheral circuit integration. In this work, we demonstrate a scalable RRAM based in-memory computing design, termed XNOR-RRAM, which is fabricated in a 90nm CMOS technology with monolithic integration of RRAM devices between metal 1 and 2. We integrated a 128x64 RRAM array with CMOS peripheral circuits including row/column decoders and flash analog-to-digital converters (ADCs), which collectively become a core component for scalable RRAM-based in-memory computing towards large deep neural networks (DNNs). To maximize the parallelism of in-memory computing, we assert all 128 wordlines of the RRAM array simultaneously, perform analog computing along the bitlines, and digitize the bitline voltages using ADCs. The resistance distribution of low resistance states is tightened by write-verify scheme, and the ADC offset is calibrated. Prototype chip measurements show that the proposed design achieves high binary DNN accuracy of 98.5% for MNIST and 83.5% for CIFAR-10 datasets, respectively, with energy efficiency of 24 TOPS/W and 158 GOPS throughput. This represents 5.6X, 3.2X, 14.1X improvements in throughput, energy-delay product (EDP), and energy-delay-squared product (ED2P), respectively, compared to the state-of-the-art literature. The proposed XNOR-RRAM can enable intelligent functionalities for area-/energy-constrained edge computing devices.

Introduction

Large DNNs challenge embedded hardware, while SRAM density, leakage, and row-by-row operation constrain memory capacity and parallelism. The paper proposes monolithically integrated XNOR-RRAM for binarized DNN in-memory computing.

Introduction

  • Binarizing weights and neuron activations to +1 or -1 converts multiplication to XNOR operations and accumulation to bitcounting, reducing computational complexity and weight memory.These algorithms target deep-learning hardware constraints in performance, power, and area.Source: Introduction · p. 2
  • SRAM density, capacity, leakage, and row-by-row operation constrain DNN hardware, while adding transistors for simultaneous-row computing can worsen density and leakage.SRAM-based in-memory designs perform MAC computations along bitlines with analog current or voltage.Source: Introduction · pp. 2–3
  • RRAM neural-computing hardware remains limited by device non-idealities, negative-value representation, and monolithic integration of arrays with CMOS peripheral circuits.Prior work mostly implemented MLPs, with limited mainstream CNN or RNN implementations.Source: Introduction · p. 3
  • XNOR-RRAM maps binarized weights and neurons to XNOR functionality and integrates a 128×64 RRAM array with CMOS peripheral circuits for in-memory DNN computing.The array includes row and column decoders/drivers and flash ADCs.Source: Introduction · p. 4

Results

The measured XNOR-RRAM prototype achieves high binary-network accuracy on MNIST and CIFAR-10, alongside reported throughput and energy-efficiency improvements. Its results depend on parallel XNOR computation, quantization, and ADC reference-voltage calibration.

Results

  • Each XNOR-RRAM bitcell uses two 1T1R cells for positive and negative weights, enabling embedded XNOR computation when differential wordlines are asserted in parallel.The 128×64 array represents 64×64 XNOR-RRAM bitcells.Source: Results · pp. 4–5
  • 86.70% CIFAR-10 accuracy with 3-bit confined-range quantization exceeded 85.84% with 4-bit full-range quantization in ideal-quantization software simulation.The confined reference-bitcount range was -13 to 11, where workload bitcounts were centered around 0.Source: Results · p. 7
  • More than 99% of LRS cells fell within 5.7–6.3 kΩ after iterative write-verify, and the estimated read-disturb probability was <0.00046*0.01.The LRS target range was 5.9–6.1 kΩ; the read-disturb estimate accounts for the rare high-bitline-voltage inputs and low-resistance HRS outliers.Source: Results · pp. 6, 7, 9
  • 98.5% MNIST and 83.5% CIFAR-10 classification accuracy were measured with 8 reference-voltage sets, versus software baselines of 98.7% and 88.6%, respectively.The tested networks were an MLP for MNIST and a CNN for CIFAR-10.Source: Results · p. 11
  • Per-ADC reference sets improved benchmark accuracy over one uncalibrated shared set, while 64 per-column sets yielded little difference from eight per-ADC sets.The authors attribute the improvement to local ADC transistor mismatch and report that column-by-column variation did not noticeably affect accuracy.Source: Results · p. 11
  • Lowering supply voltage reduced divider current and improved energy efficiency, but reduced ADC sensing margin and benchmark accuracy.MNIST accuracy fell to 97.28% at 0.9 V, and CIFAR-10 accuracy fell to 80.65% at 1.1 V.Source: Results · p. 12
  • 24.1 TOPS/W at 1.2 V and 29.2 TOPS/W at 1.1 V were reported at 154 MHz, alongside 157.7 GOPS throughput.The operating frequency is based on post-layout simulation; chip measurements were limited by slow I/O pads.Source: Results · p. 12
  • 5.6X higher throughput per ADC operation than Xue et al.30, 3.2X higher FoM1, and 14.1X higher FoM2 were reported against state-of-the-art literature30.FoM1 and FoM2 represent the inverse of EDP and ED2P, respectively.Source: Results · pp. 12–13

Discussion

XNOR-RRAM combines parallel analog MAC computation with monolithically integrated RRAM and CMOS peripherals. The discussion reports efficiency, throughput, and accuracy results while identifying ADC-area tradeoffs and design scope limits.

  • The design turns on all differential wordlines simultaneously for analog MAC computation along bitlines and integrates flash ADCs and 90nm CMOS peripherals with RRAM arrays.Source: Discussion · p. 13
  • 24 TOPS/W energy efficiency, 158 GOPS throughput, and 98.5%/83.5% accuracy on MNIST/CIFAR-10 accompany 3.2X EDP and 14.1X ED2P improvements over state-of-the-art literature.Source: Discussion · p. 14
  • ADCs impose large overhead for dense NVMs; flash-ADC area grows exponentially with precision, while SAR ADCs trade longer latency for smaller area.Source: Discussion · p. 14
  • Further energy-efficiency improvement depends largely on RRAM LRS resistance, and the current design supports only binarized DNNs; multi-bit operation would sacrifice efficiency.Source: Discussion · p. 14

Methods

The methods describe a monolithically integrated prototype, its cell-programming and electrical-characterization procedures, and a software-emulation approach for evaluating large binary networks.

  • The prototype combines a Winbond 128×64 1T1R array with manually laid-out column multiplexers and flash ADCs and digitally synthesized CMOS decoder, level-shifter, and scan-chain modules.Source: Methods · pp. 14–15
  • Cells were programmed to HRS or a 5.9–6.1 kΩ LRS target using iterative SET/RESET pulses, then switched to XNOR read mode for functionality checks.Source: Methods · p. 15
  • The team scanned 2,000 MNIST input vectors to compare measured ADC outputs with ideal outputs and used on-chip random vectors for power measurement.Source: Methods · p. 16
  • Large-network evaluation used measured ADC-output probabilities to stochastically quantize partial sums to 3-bit values, with 20 seeded runs each for MNIST MLP and CIFAR-10 CNN.Source: Methods · p. 16

Additional Information

The additional information describes the prototype layout, XNOR-RRAM computing operation, device-resistance distributions, and ADC calibration comparisons.

  • Figure 1 depicts RRAM integrated between M1 and M2, the pad-limited chip and core, and the array, multiplexers, and eight flash ADCs.Source: Figure 1 · p. 21
  • Figure 2 shows differential programmed resistances encoding weights and differential wordlines encoding inputs; all 128 rows operate together, forming a column resistive divider.Source: Figure 2 · p. 22
  • Figure 3 presents LRS and HRS programming distributions; resistance is plotted on a log x-axis against a fitted Gaussian-CDF y-axis, with 4,096 cells in each state.Source: Figure 3 · p. 23, Additional Information · p. 23
  • Figure 4 compares ideal partial sums with measured ADC results across reference-calibration schemes, including separate calibration for each column.Source: Figure 4 · p. 24, Additional Information · p. 24
  • The network diagrams label convolutional layers as Conv. and fully connected layers as FC; BN denotes batch normalization and Act. binary activation.Source: Additional Information · p. 25

MLP for MNIST CNN for CIFAR-10

The evaluation tests XNOR-RRAM on MNIST and CIFAR-10 and examines quantization, ADC calibration, and programming variability. It also compares throughput and energy-delay figures with prior work.

MLP for MNIST CNN for CIFAR-10

  • The MNIST MLP has layers 784-512-512-512-10, while the CIFAR-10 CNN has six convolution layers and three fully connected layers; reported accuracies use 20 runs with stochastic 3-bit partial-sum quantization.The quantization is based on the probability distribution of the 2-D histogram.Source: Figure 5 · p. 25
  • Accuracy increases substantially from one to eight ADC reference-voltage sets, while the difference between eight and 64 sets is negligible.The latter result indicates column-by-column variation from LRS/HRS or interconnects does not noticeably affect accuracy.Source: MLP for MNIST CNN for CIFAR-10 · p. 25
  • For the MNIST MLP workload, the 3-bit flash ADC uses seven quantization edges at -13, -9, -5, -1, 3, 7, and 11, with linear quantization confined to -15 through 11.The chosen range reflects scarce data near -64 and +64.Source: Figure 1 · p. 26
  • ADC reference voltages are iteratively adjusted using comparator errors until they can distinguish adjacent bitcount values; calibrated values vary across VSAs because their offsets differ.The correction step decays exponentially, and no correction is made when actual and ideal ADC outputs match.Source: Figure 2 · p. 27
  • From the first to sixth programming iteration, LRS resistance standard deviation falls from 105 Ω to 63 Ω, and its ratio to the mean drops from 1.31% to 0.79%.Repeatedly programming the same weights further tightens the LRS resistance distribution.Source: Figure 3 · p. 28
  • The MLP and CNN evaluations execute XNOR-and-accumulate operations on XNOR-RRAM arrays and other element-wise operations in a fixed-point digital simulator.A 512×512 fully connected layer maps to 64 arrays, while a 128×128×3×3 convolutional layer maps to 36 arrays.Source: Figure 4 · p. 29
  • Power was measured from 1.2 V down to 0.9 V across frequency values to characterize energy efficiency, and simulation traces report 1.5 ns word-line delay, 5 ns RBL settling, and 0.1 ns ADC sensing delay.The timing values are clock-to-word-line, RBL-voltage-settling, and flash-ADC-sensing delays, respectively.Source: Figure 5 · p. 30, Figure 6 · p. 31
  • 5.6X higher throughput per ADC operation, 3.2X improvement in FoM1 (EDP), and 14.1X improvement in FoM2 (ED2P) are reported versus the 55nm CMOS chip with embedded RRAM.At the same binary precision, XNOR-RRAM also achieves higher CIFAR-10 accuracy than Xue et al.30.Source: Figure 7 · p. 32
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