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Low-voltage 2D materials-based printed field-effect transistors for integrated digital and analog electronics on paper
Silvia Conti, Lorenzo Pimpolari, Gabriele Calabrese, Robyn Worsley, Subimal Majee, Dmitry K. Polyushkin, Matthias Paur, Simona Pace, Dong Hoon Keum, Filippo Fabbri, Giuseppe Iannaccone, Massimo Macucci, Camilla Coletti, Thomas Mueller, Cinzia Casiraghi, Gianluca Fiori
TL;DR
Flexible, reliable fabrication of paper-based electronics remains limited. This paper combines CVD-patterned MoS2 with inkjet-printed device layers to fabricate paper FETs and circuits, achieving mobility up to 26 cm2 V-1 s-1 and ION/IOFF up to 5x10^4.
Problem
Reliable fabrication techniques for flexible devices remain lacking, limiting their exploitation.
Method
The approach patterns and transfers CVD MoS2 to paper, then prints device layers to complete field-effect transistors and circuits.
Results
Field-effect mobility reached 26 cm2 V-1 s-1 and ION/IOFF reached 5x10^4, with integrated inverters, logic gates, and current mirrors demonstrated.
Takeaways & Limitations
The demonstrated transistors and circuits support the suitability of this approach for complete integrated circuits on paper.
Takeaways & Limitations
Schottky contacts likely increase contact resistance.
Abstract
from arXiv · showhide
Paper is the ideal substrate for the development of flexible and environmentally sustainable ubiquitous electronic systems, which, combined with two-dimensional materials, could be exploited in many Internet-of-Things applications, ranging from wearable electronics to smart packaging. Here we report high-performance MoS2 field-effect transistors on paper fabricated with a channel-array approach, combining the advantages of two large-area techniques: chemical vapor deposition and inkjet-printing.The first allows the pre-deposition of a pattern of MoS2; the second, the printing of dielectric layers, contacts, and connections to complete transistors and circuits fabrication. Average ION/IOFF of 8 x 10^3 (up to 5 x 10^4) and mobility of 5.5 cm2 V-1 s-1 (up to 26 cm2 V-1 s-1) are obtained. Fully functional integrated circuits of digital and analog building blocks, such as logic gates and current mirrors, are demonstrated, highlighting the potential of this approach for ubiquitous electronics on paper.
Introduction
The introduction motivates paper-based electronics as a sustainable, flexible platform while identifying paper’s material and fabrication challenges. It presents a channel-array approach combining CVD-grown MoS2 with inkjet printing to enable low-voltage transistors and integrated circuits.
- Motivation and challenges: Paper-based electronics offers lightweight, flexible, low-cost, and potentially more sustainable devices, but paper’s porosity, roughness, instability, hygroscopicity, and limited fabrication reliability hinder adoption.These limitations motivate approaches that can exploit paper without relying on coating or laminating layers.
- Prior limitations: Fully printed TMDC transistors have shown mobility of the order of under 0.5 cm2 V-1 s-1 and ION/IOFF ratios of hundreds, using liquid electrolytes as insulating layers.Solution-processed MoS2 devices reached average mobility around 7–11 cm2 V−1 s−1, but required acid cleaning and annealing above 200 °C, incompatible with paper substrates.
- Channel-array approach: The proposed channel-array method transfers strips of CVD-grown MoS2 onto paper and inkjet-prints customized contacts, dielectric, gates, and connections.This combines high-quality pre-positioned channels with the design flexibility of inkjet fabrication and uses two bottom-up, large-area processes.
- Device performance: 5.5 cm2 V−1 s−1 average field-effect mobility, 26 cm2 V−1 s−1 best mobility, smaller than 5 nA leakage currents, and 8 x 103 average ION/IOFF ratio are achieved below 2 V.The highest reported ION/IOFF ratio reaches 5 x 104.
- Integrated circuits: The channel-array method is extended to more complex circuits, including NOT and NAND logic gates and analog circuits, demonstrating integrated functionality on paper.The authors position the approach for applications requiring flexible and/or disposable electronics.
Results
The channel-array process transfers patterned CVD MoS2 to paper and completes top-gated FETs and circuits by inkjet-printing contacts, hBN dielectric, gates, and interconnects. The resulting devices operate below 2 V with low leakage, average mobility of 5.5 cm2 V−1 s−1, ION/IOFF of 8x103, and functional logic and analog circuits.
- Fabrication: Patterned CVD MoS2 is transferred to paper, then silver or graphene contacts, hBN dielectric, top gates, and interconnects are inkjet-printed.The channel-array approach uses routes between MoS2 stripes to connect FETs into integrated circuits.
- Material characterization: Comparable Raman-mode softening rules out strain and is attributed mainly to heating from poor heat dissipation in paper.The E2g FWHM increases from ~3 cm-1 before transfer to ~7 cm-1 after transfer, while A1g increases from ~4 cm-1 to ~6 cm-1.
- Electrical performance: 5.5 cm2 V−1 s−1 average mobility and 8x103 average ION/IOFF demonstrate the electrical performance of the paper MoS2 FETs.The methodology enables inkjet-printing device fabrication without affecting the electronic properties of CVD-grown MoS2.
- Integrated circuits on paper: 30 inverter gain under a 5 V bias and NAND operation demonstrate integrated digital circuits on paper.A current mirror further produces an output current about 10 times larger than the reference current for sufficiently high output voltages.
Discussion
The study demonstrates high-performance MoS2 transistors on paper that combine paper’s substrate advantages, inkjet-printing versatility, and the electrical properties of CVD-grown MoS2. The channel-array approach supports strain-robust devices and integrated analog and digital circuits for practical paper electronics.
- Fabrication approach: The transistors combine paper’s substrate advantages with inkjet-printing versatility and CVD-grown MoS2 electrical properties.The fabrication approach uses the advantages of paper, inkjet printing, and CVD-grown MoS2 together.
- Device performance: 26 cm2 V-1 s-1 maximum field-effect mobility and up to 5x104 ION/IOFF ratio were achieved.These results were obtained while maintaining the good electrical properties of CVD-grown MoS2.
- Mechanical robustness: Bending tests showed robust electrical properties under applied strain up to a bending radius of 8 mm.The result demonstrates mechanical robustness under the tested bending condition.
- Integrated circuits: The fabrication approach enabled complete integrated circuits including high-gain inverters, logic gates, and current mirrors.The demonstrated circuit types span both digital and analog building blocks.
- Application potential: Channel-array technology shows potential for cost-efficient and practical paper electronics ranging from analogic to digital circuits.The stated application scope is next-generation electronics on paper.
Methods
The study grows single- and few-layer MoS2 by CVD on sapphire, patterns and transfers it to paper, then fabricates top-gate/top-contact transistors by inkjet printing. Printed contacts and hBN dielectrics are deposited under ambient conditions without post-printing annealing, followed by electrical characterization.
- Growth of MoS2 and transfer on paper: The MoS2 film is patterned by Ar/SF6 plasma etching, transferred from sapphire to paper with a polystyrene carrier, and released by dissolving the polymer in toluene.The patterned film is defined before transfer, then dried, placed on paper, baked at 150 °C, and stripped of the carrier.
- Devices fabrication: Top-gate/top-contact MoS2 transistors are fabricated on paper by inkjet printing contacts and insulator layers with a Dimatix Materials Printer 2850.Printing is performed under ambient conditions, and no annealing or post-treatment follows any printing step.
- Devices fabrication: 20 printing passes define graphene source and drain contacts, while 6 passes define graphene top-gate contacts at a 2.5 mg ml-1 graphene-ink concentration.Both graphene contact types use 20 μm drop spacing and 10 pL droplets; fewer top-gate passes reduce overlap and leakage-current risk.
- Electrical characterization: All electrical measurements are performed in ambient conditions using a Keithley SCS4200 parameter analyzer for transistor characterization and dedicated instruments for capacitance measurements.Capacitance measurements use an R&S®RTO2014 oscilloscope and HP 33120A function/arbitrary waveform generator.