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COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators

Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni

arXiv:1912.10823v1cs.DC

TL;DR

Integrating specialized hardware blocks is difficult because current HLS tools optimize components independently. COSMOS coordinates HLS and memory optimization for compositional DSE, achieving broader WAMI trade-off spans while reducing HLS invocations.

  • Problem

    Current HLS tools optimize single components independently, leaving complex accelerator integration difficult at the system level.

  • Method

    COSMOS is an automatic compositional DSE methodology that coordinates HLS and memory optimization for complex hardware accelerators.

  • Results

    COSMOS reduces HLS-tool invocations by up to 14.6× and provides WAMI average performance and area spans of 4.06× and 2.58×.

  • Takeaways & Limitations

    For WAMI, COSMOS broadens explored performance-cost trade-offs compared with standard dual-port memories while reducing HLS-tool invocations.

  • Takeaways & Limitations

    The λ-constraint is not guaranteed to obtain a Pareto-optimal point because of intrinsic variability.

Abstract

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Hardware accelerators are key to the efficiency and performance of system-on-chip (SoC) architectures. With high-level synthesis (HLS), designers can easily obtain several performance-cost trade-off implementations for each component of a complex hardware accelerator. However, navigating this design space in search of the Pareto-optimal implementations at the system level is a hard optimization task. We present COSMOS, an automatic methodology for the design-space exploration (DSE) of complex accelerators, that coordinates both HLS and memory optimization tools in a compositional way. First, thanks to the co-design of datapath and memory, COSMOS produces a large set of Pareto-optimal implementations for each component of the accelerator. Then, COSMOS leverages compositional design techniques to quickly converge to the desired trade-off point between cost and performance at the system level. When applied to the system-level design (SLD) of an accelerator for wide-area motion imagery (WAMI), COSMOS explores the design space as completely as an exhaustive search, but it reduces the number of invocations to the HLS tool by up to 14.6x.

1 INTRODUCTION

COSMOS addresses the difficulty of exploring complex accelerator designs by coordinating HLS and memory optimization compositionally. It characterizes components, then searches system-level combinations for performance–cost trade-offs.

  • System-Level Design: Complex accelerators must be partitioned into components because current HLS tools cannot efficiently synthesize and explore entire accelerators.Independent component optimization can miss system-level interactions among implementation choices.
  • Design-Space Exploration: Memory optimization is essential because private memories can occupy 40% to 90% of accelerator area and must sustain parallel datapaths.Current HLS tools provide limited support for memory generation and optimization.
  • COSMOS Methodology: COSMOS coordinates HLS and memory generators to characterize each component and identify regions containing Pareto-optimal implementations.Its first stage uses coordinated tool runs for component characterization.
  • COSMOS Methodology: COSMOS then uses compositional design techniques and linear programming to identify Pareto-optimal solutions for the entire accelerator.The approach focuses exploration on critical components and converges toward a system-level cost–performance trade-off.
  • Evaluation: WAMI achieved average performance and area spans of 4.1× and 2.6×, versus 1.7× and 1.2× without memory optimization.The broader spans reflect the additional design points produced through datapath–memory co-design.
  • Evaluation: 14.6× fewer HLS invocations were required per component than with exhaustive exploration while achieving the target WAMI data-processing throughput.The evaluation used a WAMI accelerator comprising approximately 7000 lines of SystemC code.

2 PRELIMINARIES

The paper targets loosely-coupled accelerators composed of multiple components and models them in SystemC for compositional design-space exploration. This model suits coarse-grain computations on large datasets.

  • Accelerator Models: Accelerators can be tightly or loosely coupled to processing cores; the paper focuses on loosely-coupled accelerators.The stated reason is that their design complexity requires a compositional approach.
  • Accelerator Models: Tightly-coupled accelerators suit fine-grain computations on small datasets, whereas loosely-coupled accelerators suit coarse-grain computations on large datasets.
  • Accelerator Architecture: The accelerators are designed in SystemC and consist of multiple individually designed components.Component decomposition addresses current HLS tool limitations.

Architecture.

COSMOS represents complex accelerators as collections of separately synthesized components connected through on-chip channels and supported by private local memories. This structure allows components to be exchanged across Pareto-optimal implementations while coordinating datapath and memory design.

  • Architecture: Complex accelerators are partitioned into separately specified SystemC components that HLS tools can synthesize independently.Each component represents a computational block within the accelerator.
  • Architecture: Components communicate through an on-chip interconnect implementing transaction-level modeling channels.The channels synchronize components by absorbing differences in computational latency.
  • Architecture: Latency-insensitive communication allows components to be replaced with different Pareto-optimal implementations without affecting accelerator correctness.
  • Architecture: COSMOS uses fixed 256-bit communication channels and does not explore alternative implementations for inter-component communication.The communication design space could be extended with XKnobs or buffer-restructuring techniques.
  • Architecture: Private local memories are multi-bank architectures that provide multiple read and write ports for parallel data accesses.COSMOS generates optimized memories with Mnemosyne.
  • Architecture: Private local memories can occupy 40% to 90% of a component’s total area, making memory architecture important to accelerator design.

Execution.

Accelerator components execute load, compute, and store phases that may be pipelined, overlapped, or serialized according to dependencies. COSMOS models their timing and throughput compositionally with timed marked graphs.

  • Execution: Each component loads input data into private local memories, computes on that data, and stores the resulting output.
  • Execution: Load, compute, and store phases can be pipelined using ping-pong or circular buffers.
  • Execution: Components execute fully overlapped when independent, but execution is serialized when one component depends on another’s input.
  • Computational model: COSMOS models loosely-coupled accelerators with timed marked graphs, a subclass of Petri nets used for compositional performance analysis.
  • Computational model: Timed marked graphs do not capture data-dependent behavior, but they are practical for stream-processing accelerators such as image and signal processing systems.
  • Computational model: System throughput is the reciprocal of the minimum cycle time for strongly connected graphs, or the minimum throughput among strongly connected components otherwise.The minimum cycle time is max {Dk/Nk}, where Dk is cycle firing delay and Nk is the cycle’s token count.
  • Computational model: A component is represented by a transition whose firing delay equals its effective latency, defined as clock cycle count multiplied by target clock period.
  • Computational model: Area is the cost metric for both individual components and the complete system.

3 MOTIVATIONAL EXAMPLES

System-level accelerator DSE is difficult because memory optimization, HLS heuristics, and combinations of multiple components expand the search space. COSMOS addresses these issues by coordinating memory and HLS exploration with compositional prioritization.

  • Motivation: Accurate, exhaustive DSE is difficult because HLS tools have limited memory-generation support, heuristic knob behavior, and no simultaneous multi-component optimization.
  • 3.1 Memories: COSMOS generates optimized private local memories with Mnemosyne while exploring datapath configurations.
  • 3.1 Memories: Increasing memory ports can improve latency and area trade-offs by enabling more data accesses per cycle, but multi-port memories may require more area.
  • 3.1 Memories: 7.9× latency span and 3.7× area span are obtained with optimized memories, compared with 1.4× latency span and 1.2× area span using standard dual-port memories.
  • 3.2 HLS unpredictability: HLS heuristics can make some loop-unrolling configurations worsen both latency and area instead of producing the expected parallelization benefit.
  • 3.3 Compositionality: An exhaustive system-level search evaluates O(k^n) combinations when n components each have k Pareto-optimal points.
  • 3.3 Compositionality: COSMOS reduces synthesized knob combinations and prioritizes components according to their contribution to total effective throughput.

4 THE COSMOS METHODOLOGY

COSMOS performs component characterization and system-level DSE as coordinated stages. It identifies Pareto-optimal regions while accounting for memories and HLS variability, then uses system modeling and synthesis planning to guide additional implementations.

  • Component Characterization: Component Characterization analyzes each component individually and identifies regions containing Pareto-optimal implementations.
  • Component Characterization: COSMOS automatically coordinates HLS and memory-generator configurations from each component’s SystemC implementation.
  • Component Characterization: Component characterization accounts for accelerator memories and HLS-tool unpredictability.
  • Design-Space Exploration: System-level DSE models the complete accelerator with a timed marked graph to identify components most critical to throughput.
  • Design-Space Exploration: Synthesis Planning formulates a linear-programming problem to determine component latency requirements that satisfy a specified system throughput while minimizing system cost.
  • Design-Space Exploration: Synthesis Mapping converts linear-programming solutions into component knob settings and runs additional synthesis to obtain RTL implementations.

5 COMPONENT CHARACTERIZATION

COSMOS characterizes component design regions by exploring combinations of memory ports and loop unrolling, using the λ-constraint to limit HLS scheduling and remove dominated points. It then generates optimized private local memories tailored to each component’s access patterns.

  • Algorithm 1 characterizes components using the designer-provided clock period, memory-port limits, and loop-unrolling choices.The resulting points represent the component design space used for system-level exploration.
  • Regions group design points with the same number of ports and are bounded by upper-left and lower-right latency-area extremes.The extremes are denoted (λmin, αmax) and (λmax, αmin), respectively.
  • The λ-constraint bounds the maximum number of HLS states inserted in a loop, making synthesis more deterministic and removing some Pareto-dominated points.Its state bound is estimated from read accesses, write accesses, and non-memory-operation latency inferred from the CDFG.
  • In the example, unrolling two times with two memory ports fits within h2(2) = 3 clock cycles, whereas unrolling three times requires at least five cycles and is discarded.The latter exceeds the bound h2(3) = 4 clock cycles.
  • The λ-constraint is not guaranteed to produce a Pareto-optimal point and cannot directly handle loops using blocking sub-component interfaces or lacking PLM accesses.COSMOS can instead synthesize near the maximum unroll count or use a local Pareto-optimal point as the upper-left extreme.
  • Mnemosyne generates PLMs tailored to required ports and access patterns, combining SRAMs or FPGA BRAMs into multi-bank architectures.COSMOS adds the generated memory area to the logic area reported by HLS.

6 DESIGN-SPACE EXPLORATION

COSMOS performs system-level DSE by optimizing characterized component choices under throughput constraints, then maps target component latencies to HLS knob settings. Its formulation reduces system exploration to repeated optimization over discretized throughput targets.

  • 6 DESIGN-SPACE EXPLORATION: COSMOS formulates system-level DSE as finding a Pareto curve of system cost α versus throughput θ while limiting spacing between consecutive points and HLS invocations.The formulation assumes characterized components, an HLS tool, and a target granularity δ > 0.
  • 6.1 Synthesis Planning: The θ-constrained LP minimizes component implementation costs while satisfying system throughput requirements.Unknown component cost functions are approximated with convex piecewise-linear functions, and the LP can be solved in polynomial time.
  • 6.1 Synthesis Planning: Iterating throughput targets from θmin to θmax by a ratio of (1+δ) finds component latencies that solve the system-level optimization.Components not critical to throughput are selected to minimize their cost.
  • 6.2 Synthesis Mapping: COSMOS maps each optimized component latency λtarдet within its region to an estimated number of loop unrolls using a modified Amdahl’s Law mapping function.Because each region has a fixed port count, only the unroll count must be estimated for intermediate points.
  • 6.2 Synthesis Mapping: The mapping function models diminishing returns in latency as unrolling increases, then synthesis obtains actual latency, area, and the component RTL implementation.The function returns an integer unroll count using a ceiling operation.
  • 6.2 Synthesis Mapping: For a region spanning latencies from 40 s to 10 s and unroll counts from 1 to 30, a requested latency of 20 s maps to 11 unrolls.The mapping returns minimum unrolling at maximum latency and maximum unrolling at minimum latency.
  • 6.2 Synthesis Mapping: If mapping violates the λ-constraint, COSMOS increases unrolling; if the target falls outside a region, it uses a synthesized slower point from the next higher-port region.This conservative fallback trades area to preserve throughput and avoids another synthesis run for the previously synthesized point.

7 EXPERIMENTAL RESULTS

COSMOS is evaluated on the heterogeneous WAMI accelerator, where memory-aware characterization expands component trade-offs and compositional exploration reduces synthesis effort. The study reports richer design spaces and substantial reductions in HLS invocations compared with memory-unaware or exhaustive exploration.

  • Experimental setup: COSMOS evaluates WAMI, a heterogeneous accelerator containing Debayer, Grayscale, Lucas-Kanade, and Change-Detection components.Lucas-Kanade is partitioned into sub-components to increase hardware parallelism.
  • Component characterization: Memory-aware characterization provides significant gains in area and latency spans over designs using standard dual-port memories.For WAMI, average performance and area spans are 4.06× and 2.58× with COSMOS, versus 1.73× and 1.22× without memory optimization.
  • Component characterization: Increasing memory ports improves latency initially, but diminishing returns can make additional ports increase area without latency gains.Loop unrolling also has a local effect within each port-defined region.
  • System-level exploration: COSMOS reduces WAMI HLS-tool invocations by 6.7× on average and up to 14.6× for single components compared with exhaustive exploration.The method first finds system-level solutions, then maps them to component knob settings and synthesizes the necessary implementations.
  • Summary: COSMOS combines memory generation with compositional DSE to provide a richer exploration than approaches that omit memory optimization.Its compositional nature is intended to preserve these performance gains as accelerator designs grow larger.

8 RELATED WORK

Related methods separately address HLS design-space exploration, memory optimization, or system-level composition. COSMOS differs by coordinating HLS and memory generators while mapping system-level solutions to feasible RTL implementations.

  • Single-component DSE: Prior HLS DSE methods use probabilistic, heuristic, iterative, genetic, or machine-learning-based approaches to identify relevant knobs and Pareto curves.These methods generally focus on scheduled RTL implementations in a multi-objective design space.
  • Memory optimization: Existing approaches either omit optimized memory generation or focus on memory architectures without exploring other HLS knobs.Memory-focused work addresses accelerator memory subsystems but does not cover the full HLS design space.
  • COSMOS’s distinction: COSMOS coordinates memory generators and HLS tools to find Pareto-optimal accelerator implementations rather than optimizing either domain alone.It includes memory generation and optimization within the DSE process.
  • COSMOS’s distinction: Unlike loop-transformation methods, COSMOS focuses on configuring HLS knobs after loop transformations have been applied.Its compositional approach targets Pareto-optimal implementations of the entire system, not only individual components.
  • Compositional DSE: COSMOS uses synthesis constraints based on specification dependencies and memory references to identify larger regions of Pareto-optimal implementations.It also correlates theoretical LP solutions with feasible high-level knob settings and memory parameters.

9 CONCLUDING REMARKS

COSMOS coordinates HLS and memory-generator tools through an intrinsically compositional DSE flow. In the WAMI case study, it finds more Pareto-optimal implementations than PLM-unaware methods and reduces HLS invocations versus exhaustive search.

  • Contribution: COSMOS is an automatic compositional DSE methodology that coordinates HLS and memory-generator tools.It treats the components’ PLMs as an essential part of design-space exploration.
  • Method: The workflow characterizes components, uses a linear-programming formulation for system-level Pareto solutions, and maps them to RTL knob settings.The mapping identifies component configurations that realize the selected system-level implementations.
  • Results: COSMOS finds a larger set of Pareto-optimal implementations than methods that do not consider PLMs.The comparison is demonstrated using the WAMI accelerator case study.
  • Results: COSMOS reduces HLS-tool invocations by up to one order of magnitude compared with exhaustive search methods.This result is reported for the WAMI evaluation.
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