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Solid-state qubits integrated with superconducting through-silicon vias
Donna-Ruth W. Yost, Mollie E. Schwartz, Justin Mallek, Danna Rosenberg, Corey Stull, Jonilyn L. Yoder, Greg Calusine, Matt Cook, Rabindra Das, Alexandra L. Day, Evan B. Golden, David K. Kim, Alexander Melville, Bethany M. Niedzielski, Wayne Woods, Andrew J. Kerman, Willam D. Oliver
TL;DR
Interconnect crowding and material-related coherence concerns complicate scaling superconducting qubit arrays. This work integrates compact superconducting TSVs into a two-chip qubit architecture and demonstrates baseband control, microwave readout, and qubits fabricated on the interposer. The results support TSV-based control and readout for 3D-integrated qubit arrays.
Problem
Planar interconnect crowding constrains larger qubit arrays, while common 3D-integration materials can reduce qubit lifetimes or performance.
Source: INTRODUCTION · pp. 1–2Method
The work integrates superconducting TSVs into a two-chip bump-bonded architecture and fabricates coherent qubits directly on the TSV-integrated interposer surface.
Source: INTRODUCTION · p. 2, DISCUSSION · p. 6Results
The TSV transitions route high-fidelity control and readout signals through the stack, and qubits thermalize effectively in the multi-chip architecture.
Source: DISCUSSION · p. 5Takeaways & Limitations
The demonstrated TSV design and fabrication support readout and control of 3D-integrated qubit arrays.
Source: DISCUSSION · p. 5Common industry-standard amorphous dielectrics can decrease qubit lifetimes, while normal-metal currents can heat devices and excite performance-degrading quasiparticles.
Source: INTRODUCTION · pp. 1–2
Abstract
from arXiv · showhide
As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays -- provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs -- 10 $\mu$m wide by 20 $\mu$m long by 200 $\mu$m deep -- with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
INTRODUCTION
Planar interconnect crowding and loss from conventional 3D-integration materials motivate superconducting TSV approaches for larger qubit arrays. This work introduces a compact TSV interposer architecture for control, readout, and qubits fabricated on the interposer surface.
INTRODUCTION
- Lateral interconnect crowding limits planar arrays as they grow, while larger architectures may require multiple qubit and routing layers and through-substrate ground connections.These challenges motivate more capable 3D integration for superconducting qubits.Source: INTRODUCTION · p. 1
- Conventional 3D integration can compromise coherence through lossy amorphous dielectrics, and normal-metal currents can heat devices and excite performance-degrading quasiparticles.Monolithic multilayer superconducting routing can also be associated with low coherence due to lossy integrated dielectric films.Source: INTRODUCTION · pp. 1–2
- The proposed three-chip stack uses a superconducting TSV interposer between the qubit chip and routing chip, while the two-chip demonstration routes control and readout through the interposer.The interposer's silicon separates qubits from routing-chip dielectrics and spreads the qubit electromagnetic field over a larger mode volume to reduce sensitivity to loss modes.Source: INTRODUCTION · p. 2, Figure 1 · p. 2
- The TSVs measure 10 µm × 20 µm across and pass through a 200 µm chip, with a 100 µm pitch supporting up to 10,000 interconnects on a 10 mm × 10 mm chip.The work also reports 10–20 µs T1 relaxation times for separately fabricated qubits in the two-stack and for qubits fabricated directly on the interposer surface.Source: INTRODUCTION · pp. 2–3
RESULTS
The work benchmarks TSV integration using capacitively shunted flux qubits (CSFQs), designed for quantum annealing applications. It demonstrates TSV-integrated baseband and microwave control of those qubits.
RESULTS
- CSFQs benchmark the TSV integration, and the devices are designed for quantum annealing applications requiring tunable magnetic fields, large qubit-to-qubit coupling, and high connectivity.Planar equivalents have T1 = 10–20 µs.Source: RESULTS · p. 3
- Annealing-qubit control requires several mA of baseband current below 100 MHz, while qubit excitation and readout require high-fidelity microwave signals in the 3–10 GHz range.Source: RESULTS · p. 3
- The study demonstrates baseband and microwave control of CSFQs using TSV-integrated bias and readout elements.Source: RESULTS · p. 3
Qubit control and readout through interposer chip
Two-stack devices route qubit bias and readout through TSV transitions in the interposer. The demonstrations show full-flux-quantum control, high-fidelity microwave readout, and effective qubit thermalization.
Qubit control and readout through interposer chip
- A mean T1 of 10 µs was measured across separately fabricated devices testing TSV-integrated baseband and microwave control.The devices used 50 Ω TSV transitions in flux-bias lines and coplanar-waveguide resonators.Source: Qubit control and readout through… · p. 3
- Approximately 5 mA through the TSV-integrated flux-bias line tuned the CSFQ's first transition frequency over a full flux quantum.The demonstrated current was below the typical TSV critical current, which exceeds 10 mA; persistent application produced no observed dilution-refrigerator heating.Source: Qubit control and readout through… · p. 3
- A microwave-optimized TSV transition supported single-shot readout with separation infidelity εS = 2.1 × 10^-5 at a 2.5 µs integration time.The readout resonator was split across the two interposer planes and capacitively coupled to the CSFQ.Source: Qubit control and readout through… · pp. 3–4
- A sample CSFQ passively prepared in its thermal state had excited-state probability Pe = 3.3%, corresponding to effective qubit temperature Tq = 52.5 mK at transition frequency ωq/2π = 3.718 GHz.The result was extracted from a histogram of 21,000 single-shot measurements.Source: Figure 3 · p. 4
Qubit thermalization in multi-chip architectures
The authors test whether qubits thermalize adequately in two- and three-stack architectures despite weak thermal paths through the stacked chips. In the 2-stack, single-shot readout measures an effective qubit temperature of 52.5 mK under 2.3 mA bias, and the authors conclude performance is on par with single-chip architectures.
Qubit thermalization in multi-chip architectures
- Thermalization must be verified because the qubit chip connects to the interposer through superconducting indium bumps, while the interposer is separated from the copper bath by a silicon ring and aluminum wirebonds.The authors describe none of these paths as canonically good thermal conductors.Source: Qubit thermalization in multi-chip… · p. 4
- At 2.3 mA bias, the measured excited-state probability was 3.3%, corresponding to a 52.5 mK qubit temperature at 3.718 GHz.No dilution-refrigerator heating was observed during the experiment.Source: Qubit thermalization in multi-chip… · p. 4
- The 52.5 mK result compares favorably with single-qubit-chip temperatures of 35–40 mK, and the authors conclude 2-stack performance is on par with single-chip architectures.They note that established techniques can initialize a pure quantum state at these temperatures.Source: Qubit thermalization in multi-chip… · p. 4
Integration of qubits on TSV interposer surfaces
The authors fabricate coherent capacitively shunted flux qubits directly on the interposer surface despite the substantial processing required for TSV integration. Four such qubits have a mean relaxation time of 12.5 µs, consistent with comparable qubits on silicon without TSV processing.
Integration of qubits on TSV interposer surfaces
- Fabricating active Josephson-junction elements on the interposer is challenging because its top surface undergoes substantially more mechanical and chemical processing than a standard qubit chip.Deposition and patterning processes must be optimized for those additional steps.Source: Integration of qubits on TSV… · p. 4
- An interposer surface compatible with active qubits and tunable couplers could support denser qubit packing and novel coupling schemes.The authors frame these as architectural possibilities opened by overcoming the processing constraints.Source: Integration of qubits on TSV… · p. 4
- The demonstrated devices place coherent CSFQs, TSVs, control and readout circuitry, and Josephson junctions directly on the interposer surface.The figure shows the qubit, readout resonator, TSV-integrated flux-bias line, and junction loop.Source: Integration of qubits on TSV… · p. 4, Figure 4 · p. 5
- 12.5 µs was the mean T1 across four qubits fabricated on the TSV-processed interposer surface, consistent with similar annealing qubits on silicon without TSV processing.The authors say these qubits are sufficient for off-chip coupling elements in gate-model quantum computing and on par with devices being developed for high-coherence annealing.Source: Integration of qubits on TSV… · p. 5, Figure 4 · p. 5
DISCUSSION
The discussion presents compact superconducting TSVs as a route to vertical signal delivery in qubit stacks, combining dense routing with baseband and microwave control and readout. The demonstrated capabilities support multilayer architectures, while full 3-stack integration remains future work.
DISCUSSION
- Compact TSVs integrate into qubit readout and control circuitry, provide densely packed ground connections, and route baseband and microwave signals through the stack without degrading signal performance.The transitions are designed for 50 Ω signals; the authors also report effective qubit thermalization despite added thermal resistance from multiple chips.Source: DISCUSSION · p. 5
- These TSVs combine high aspect ratio with the critical current needed for full qubit readout and control, unlike previously demonstrated TSV approaches described by the authors.Earlier sloped-wall TSVs were qubit-sized, while high-aspect-ratio bolometer-array TSVs lacked critical current for qubit-frequency flux control.Source: DISCUSSION · pp. 5–6
- A second qubit plane on the interposer could increase density beyond a single-tier architecture, while separate chips for components with different junction critical-current densities could increase design flexibility.The authors also describe interposer-mounted tunable couplers as a route to novel, stronger, more compact coupling schemes.Source: DISCUSSION · p. 6
- The 2-stack demonstrations establish signal delivery through compact TSVs, but full integration of qubits, interposer, and multilayer signal routing is left for future work.The authors describe that full 3-stack integration as a future demonstration.Source: DISCUSSION · p. 6
TSV-integrated interposer fabrication
The interposer fabrication uses a via-first process on 200 mm wafers, forming superconducting TiN-lined TSVs before revealing and patterning the opposite surface. The process then adds circuit layers and Josephson junctions before dicing and releasing the wafer.
TSV-integrated interposer fabrication
- A via-first process etches blind TSVs deeper than 200 µm into 725 µm high-resistivity silicon wafers, with sidewall slopes above 89° and smooth Bosch-etched walls.An optimized CVD TiN film coats the via sidewalls and wafer surface to form the superconducting layer.Source: TSV-integrated interposer fabrication · p. 6
- After temporary-carrier bonding, grinding and chemical-mechanical polishing thin the wafer to reveal the opposite TSV ends, which receive a PVD TiN layer.Interconnects, bias lines, resonators, and qubit capacitors are then defined by subtractive etching.Source: TSV-integrated interposer fabrication · p. 6
- Al/AlOx/Al Josephson junctions are fabricated by electron-beam-defined Dolan bridges and double-angle shadow evaporation before the wafer is diced and released from its carrier.Further interposer fabrication details are deferred to a forthcoming work.Source: TSV-integrated interposer fabrication · p. 6
Qubit chip fabrication
Qubit devices are fabricated on high-resistivity silicon using aluminum base metallization and shadow-evaporated Josephson junctions. Indium bumps are added over underbump metallization for electrical contact.
Qubit chip fabrication
- Qubit devices are patterned on 50-mm high-resistivity silicon substrates with resistivity greater than 10,000 Ω-cm.The device stack includes silicon hard-stop spacers, base metal, superconducting qubits, underbump metal, and indium bumps.Source: Qubit chip fabrication · p. 6
- Aluminum base metallization forms capacitive shunts, ground planes, and on-chip control and readout circuitry.These components are patterned by subtractive etching.Source: Qubit chip fabrication · p. 6
- Josephson junctions are defined by double-angle shadow evaporation through Dolan-style bridges after in-situ ion milling removes native aluminum oxide.Source: Qubit chip fabrication · p. 6
Flip-chip integration
Qubit and interposer chips are thermocompression-bonded, with indium bumps connecting only the ground planes in the devices used here.
Flip-chip integration
- Indium bumps connect the ground planes of the two chips, but do not carry active signals in the devices used here.Source: Flip-chip integration · p. 6
- Thermocompression bonding at 105°C produces post-bond lateral alignment accuracy below 1 µm and vertical chip spacing of 3 µm.Alignment is verified by post-bond infrared imaging of alignment structures.Source: Flip-chip integration · p. 6
- The measured lateral alignment accuracy has a negligible effect on coupling between qubits and interposer-chip elements.Source: Flip-chip integration · p. 6
Measurement
The measurements use dispersive readout of flux-tunable qubits coupled to resonators, with single-shot data used to assess readout separation and qubit temperature. The section also reports relaxation-time measurements and contextualizes coherence measurements against planar devices.
Measurement
- Planar-equivalent devices typically have T1=10-20 µs, while the measured T1 differences between qubits on the qubit chip and interposer chip are not statistically significant.Source: Table I · p. 7
- Qubit and resonator frequencies, T1, and T2,Ramsey and T2,Echo are recorded at the flux-insensitive point, but rough calibration scans make most T2 measurements underestimates.The reported T2 values are therefore not the devices’ true coherence; samples b and f were fine-tuned for optimal phase coherence.Source: Table I · p. 7, Measurement · p. 7
- Single-shot measurements of 21,000 preparations each of |0⟩ and |1⟩ are fit with Gaussian distributions to extract separation fidelity.The |0⟩-prepared data is also used to extract qubit temperature.Source: Measurement · p. 7
- Four qubits fabricated on the interposer chip are sequentially measured at their flux-insensitive points, with T1 recorded 100 times over approximately two hours.The relaxation-time measurements are histogrammed.Source: Measurement · p. 7
- The resonator measurements use standard dispersive techniques with a CSFQ coupled to a CPW λ/4 resonator, and vacuum Rabi splitting is observed at avoided crossings.The periodicity of the crossings provides the effective inductive coupling between the TSV-integrated bias line and qubit.Source: Measurement · pp. 6–7