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FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing

Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini

arXiv:2007.01530v1cs.AR

TL;DR

FPnew addresses the limited precision choices of conventional CPUs and GPUs amid growing demand for energy-efficient computation. It provides an open-source configurable transprecision FPU with RISC-V extensions, and the paper reports energy savings in an embedded-core case study and measured silicon results.

  • Problem

    FP precision modulation in CPUs and GPUs had largely been limited to double and float despite the emergence of many other FP formats.

    Source: §I · p. 1

  • Method

    FPnew is a configurable open-source transprecision FPU supporting multiple FP formats, paired with RISC-V extensions for transprecision operations.

    Source: §I · p. 2, §VI · p. 13

  • Results

    34% lower system energy than the FP32 implementation while achieving FP32 precision without performance overhead versus an optimal scalar FP16 baseline; 8×FP8 SIMD reaches 2.95 Tflop/s W and 25.33 Gflop/s.

    Source: §VI · p. 13

  • Takeaways & Limitations

    FPnew achieves better energy-efficiency scaling than other multi-mode FMA designs, and its open design has found use in embedded IoT applications and high-performance vector accelerators.

    Source: §VI · p. 13

Abstract

from arXiv · show

The slowdown of Moore's law and the power wall necessitates a shift towards finely tunable precision (a.k.a. transprecision) computing to reduce energy footprint. Hence, we need circuits capable of performing floating-point operations on a wide range of precisions with high energy-proportionality. We present FPnew, a highly configurable open-source transprecision floating-point unit (TP-FPU) capable of supporting a wide range of standard and custom FP formats. To demonstrate the flexibility and efficiency of FPnew in general-purpose processor architectures, we extend the RISC-V ISA with operations on half-precision, bfloat16, and an 8bit FP format, as well as SIMD vectors and multi-format operations. Integrated into a 32-bit RISC-V core, our TP-FPU can speed up execution of mixed-precision applications by 1.67x w.r.t. an FP32 baseline, while maintaining end-to-end precision and reducing system energy by 37%. We also integrate FPnew into a 64-bit RISC-V core, supporting five FP formats on scalars or 2, 4, or 8-way SIMD vectors. For this core, we measured the silicon manufactured in Globalfoundries 22FDX technology across a wide voltage range from 0.45V to 1.2V. The unit achieves leading-edge measured energy efficiencies between 178 Gflop/sW (on FP64) and 2.95 Tflop/sW (on 8-bit mini-floats), and a performance between 3.2 Gflop/s and 25.3 Gflop/s.

I. INTRODUCTION

FPnew addresses the need for energy-efficient computation across emerging FP formats with a configurable, open-source transprecision FPU and RISC-V extensions. The paper demonstrates the design in embedded and application-class RISC-V cores.

I. INTRODUCTION

  • Energy efficiency is an increasingly important hardware goal as Moore’s law falters and workloads such as machine learning demand higher performance under constant or lower power budgets.Source: §I · p. 1
  • Transprecision computing aims to fine-tune precision and performance to application requirements, while FP precision modulation had largely been limited to common double and float formats in CPUs and GPUs.Source: §I · p. 1
  • The design extends RISC-V with operations on additional FP formats, leveraging the ISA’s openness and extensibility.Source: §I · p. 2
  • The silicon implementation in a RISC-V application-class core supports FP64, FP32, FP16, FP16alt, and FP8, plus SIMD vectorization and vectorial conversions and packing.Source: §I · p. 2
  • The RI5CY case study reports 1.67× speedup over an FP32 baseline without sacrificing result precision, while reducing processor energy by 37%.Source: §I · p. 2

II. ARCHITECTURE

  • FPnew is a flexible, open-source hardware IP block that supports arbitrary FP formats and targets general-purpose cores as well as domain-specific accelerators.Source: §II · p. 2

A. Requirements

FPnew’s requirements span IEEE 754-oriented custom formats, broad FP operations, SIMD vectors, configurable pipeline depths, and synthesis-friendly implementation. These choices are intended to support diverse systems, applications, and technologies.

1) FP Format Encoding:

2) Operations:

  • The unit aims to support RISC-V FP operations, including arithmetic, comparisons, and conversions, as well as multi-format FMA operations.Source: 2) Operations · pp. 2–3

3) SIMD Vectors:

  • SIMD vectors pack narrow operands into a wide datapath, supporting vectorized data needed for flexible conversions and multi-format operations.Source: 3) SIMD Vectors · p. 3

4) Variable Pipeline Depths:

  • Pipeline depths must be configurable because operation latency requirements vary by system architecture and implementation technology.Source: 4) Variable Pipeline Depths · p. 3

5) Design Tool Flow:

  • The design is expressed to enable target-specific synthesis optimizations, including clock-gating and pipelining, across ASIC and FPGA flows.Source: 5) Design Tool Flow · p. 3

B. Building Blocks

  • The architecture description separates general building blocks from concrete configurations used for processor integration and silicon implementation.Source: B. Building Blocks · p. 3

1) FPU Top Level:

The TP-FPU routes operands through operation-group blocks and format slices, with configurable width and support for scalar and SIMD-vector operation. Parallel and merged slice organizations trade flexibility against area and energy or latency overheads.

1) FPU Top Level:

  • Up to three FP operands enter per cycle, and routing to operation groups plus output arbitration allows unused branches to be clock- and datapath-gated.Source: 1) FPU Top Level · p. 3

2) Operation Group Blocks:

  • Four operation groups cover addition, multiplication and FMA; division and square root; comparisons and bit manipulation; and conversions among FP formats and integers.Source: 2) Operation Group Blocks · p. 3

3) Format Slices:

  • Format slices host functional units and can provide SIMD lanes; parallel slices duplicate format-specific datapaths, while merged slices share hardware with reduced flexibility and possible energy or latency overheads.Merged slices determine lane count from the smallest supported format; conversion slices also distribute and collect vector data across differing widths.Source: 2) Operation Group Blocks · p. 3, 3) Format Slices · pp. 3–4

4) Functional Units:

Functional units use pipelined or iterative implementations, while handshake-based control supports variable-latency results and fine-grained gating. SystemVerilog configuration parameters tune formats, slice organization, SIMD, and pipeline stages.

4) Functional Units:

  • The ADDMUL block uses pipelined IEEE 754-2008 FMA units, while DIVSQRT uses an iterative divider whose iteration count can be reduced to trade throughput for accuracy.Multi-format FMA performs multiplication in the source format and addition in the destination format; conversion units cast among FP formats and integers.Source: 4) Functional Units · p. 4

5) Unit Control Flow:

  • Round-robin arbitration and valid-ready handshaking manage outputs from different-latency paths, allowing fine-grained clock gating within pipeline stages.Source: 5) Unit Control Flow · p. 4

6) Configuration:

  • SystemVerilog parameters configure arbitrary formats, parallel or merged slices, SIMD, and pipeline stages independently by format and operation group.Formats support IEEE 754-2008 rounding modes; merged slices use the highest stage count among their containing formats.Source: 6) Configuration · pp. 4–5

III. INTEGRATING FPNEW IN RISC-V CORES

FPnew is integrated into the RI5CY and Ariane RISC-V cores with ISA extensions for transprecision operations. The extensions cover multiple FP formats, scalar and vector operations, and auxiliary operations for precision scaling and packing.

A. ISA Extensions:

  • The unit is integrated into the 32-bit RI5CY and 64-bit Ariane RISC-V cores, with ISA extensions added to leverage the TP-FPU in general-purpose processors.The ISA extensions use RISC-V's support for custom operations.Source: §III · p. 5, A. ISA Extensions · p. 5

1) FP Formats:

  • The extensions support binary64, binary32, binary16, binary16alt, and binary8 formats, with narrow values handled like standard RISC-V FP formats.The formats include IEEE 754 double, single, and half precision, custom half precision, and custom quarter-precision minifloat.Source: 1) FP Formats · p. 5

2) Operations:

  • Scalar extensions add arithmetic, comparisons, conversions, and data movement for the new formats, including conversions among all supported FP types.The conversions support runtime precision scaling in transprecision applications.Source: 2) Operations · p. 5
  • SIMD instructions cover formats narrower than the FP register width, with vector-scalar variants replicating the scalar operand across vector elements.For FLEN = 32, one example is a packed vector of 2 × FP16.Source: 2) Operations · p. 5
  • Vector conversions use separate instructions for the lower or upper vector portion when source and destination lengths differ.This handles cases where conversion would otherwise leave destination elements unused or produce a result too wide for the register.Source: 2) Operations · p. 5
  • Auxiliary instructions add expanding FMA, which multiplies in one format and sums in a larger format, and cast-and-pack, which converts two scalars and packs them into a vector.The expanding FMA maps to multi-precision operations of the merged FMA slice.Source: 2) Operations · p. 5

3) Encoding:

The RISC-V extensions are encoded using available non-standard instruction space, and compiler support exposes the formats and operations to user programs. RI5CY implements selected extensions using its existing core resources and a configurable TP-FPU.

3) Encoding:

  • The new instructions use brown-field non-standard RISC-V encodings, reusing standard FP instruction encodings for scalar formats and unused opcode space for vector and auxiliary operations.Reserved encodings distinguish FP16, FP8, and FP16alt.Source: 3) Encoding · p. 5

4) Compiler Support:

  • The RISC-V GCC toolchain supports the new formats and operations as native C/C++ types, including the float8 type for FP8 variables.This provides high-level support for transprecision operations in user programs.Source: 4) Compiler Support · p. 5

B. RI5CY with Transprecision FPU

  • RI5CY is an open-source 32-bit, four-stage, in-order RISC-V core intended for embedded and DSP applications.The implementation targets non-standard transprecision operations in an MCU-class core.Source: B. RI5CY with Transprecision FPU · p. 5

1) ISA Extension Support:

  • RI5CY adds FP16 and FP16alt operations, packed SIMD, cast-and-pack, and expanding FMA, reusing the general-purpose register file for FP values.The integer datapath's DSP-extension SIMD shuffling functionality is leveraged for those values.Source: 1) ISA Extension Support · p. 6

2) Core Modifications:

  • Core changes include decoder and load/store extensions for new instructions and narrow FP data; NaN-boxing is not checked in operation units so SIMD data can be treated as scalars.The passage says these core changes are not substantial relative to the existing ‘F’ extension infrastructure.Source: 2) Core Modifications · p. 6

3) FPU Configuration:

  • The RI5CY TP-FPU uses a 32-bit width and adds formats without extra pipeline stages; its merged ADDMUL slice supports multi-format operations among FP16[alt] and FP32.The DIVSQRT block is disabled for the case study, while the two-lane merged CONV slice supports cast-and-pack from two FP32 operands.Source: 3) FPU Configuration · p. 6, Table I · p. 6

C. Ariane with Transprecision FPU

Ariane extends transprecision support to a 64-bit RISC-V core, while the RI5CY-based PULPissimo implementation is placed and routed in Globalfoundries 22FDX technology. The Ariane TP-FPU uses format-dependent configuration choices, including parallel ADDMUL and iterative division hardware.

C. Ariane with Transprecision FPU

  • Ariane is an open-source 64-bit, six-stage, partially in-order RISC-V RV64GC processor.The core also has hardware support for operating systems and private instruction and data caches.Source: C. Ariane with Transprecision FPU · p. 6

1) ISA Extension Support:

  • Ariane adds FP16, FP16alt, and FP8 operations plus SIMD for these formats and FP32, but does not implement expanding FMA.Flexible cast-and-pack operations are supported.Source: 1) ISA Extension Support · p. 6

2) Core Modifications:

  • Ariane's core changes replace its FPU, extend the decoder, and modify load/store circuitry for one-extending narrower FP data for NaN-boxing.The added control-circuitry changes are described as not timing-critical and negligible in cost relative to the rest of the core resources.Source: 2) Core Modifications · p. 6

3) FPU Configuration:

  • Ariane's 64-bit TP-FPU configuration uses format-specific pipeline depths and a parallel ADDMUL implementation to avoid unnecessary energy and latency overheads for narrow formats.DIVSQRT latency ranges from 4 cycles for FP8 to 21 for FP64; divisions take three cycles for pre- and post-processing, with three mantissa bits produced per cycle.Source: 3) FPU Configuration · p. 6, Table II · p. 6

A. PULPissimo: RI5CY with Transprecision FPU

  • The PULPissimo RI5CY system was synthesized, placed, and routed in Globalfoundries 22FDX; at nominal low-voltage conditions it runs at 370 MHz.The stated nominal conditions are TT, 0.65 V, and 25 °C.Source: A. PULPissimo: RI5CY with… · p. 7

1) Implementation:

The TP-FPU is integrated into RI5CY and Ariane systems, with silicon implementation of the Ariane design in GLOBALFOUNDRIES 22FDX. The added FP capability has modest system-level costs, while the fabricated Ariane core is evaluated across several implementation conditions.

1) Implementation:

  • PULPissimo provides a single-core SoC platform with 512 kB of memory and standard peripherals for the extended RI5CY with a single-cycle TP-FPU.The complete system includes UART, I2C, and SPI peripherals.Source: 1) Implementation · p. 7

2) Impact of the TP-FPU:

  • 76% of the RI5CY FPU area is the ADDMUL block hosting merged multi-format FMA units; COMP and CONV occupy 4% and 18%, respectively.The core with TP-FPU is 147 kGE, including a 69 kGE FPU, while PULPissimo including memories is 5.1 MGE.Source: 2) Impact of the TP-FPU · p. 7
  • 29% more area and 37% more static energy than an FP32-only RI5CY correspond to 0.7% and 0.9% system-level increases, respectively.Memories account for 92% of system area and 96% of leakage.Source: 2) Impact of the TP-FPU · p. 7
  • 3.9 pJ for FP32 FMA and 1.0 pJ for integer MAC are execution-unit costs; at system level, their filtering-kernel costs are 22.2 pJ and 21.2 pJ per cycle at equal performance.The authors conclude that these small system-level differences make FP computations affordable even in an MCU context.Source: 2) Impact of the TP-FPU · p. 7

B. Kosmodrom: Ariane with Transprecision FPU

  • Two functionally identical Ariane cores with TP-FPU were fabricated in GLOBALFOUNDRIES 22FDX, with different cell technologies and target frequencies, sharing 1.25 MB of L2 memory and common periphery.The design supports five FP formats with dedicated datapaths.Source: 1) Silicon Implementation · p. 7, Figure 5 · p. 7

1) Silicon Implementation:

  • The high-performance Ariane implementation reaches 0.96 GHz worst-case, 1.29 GHz nominal, and 1.76 GHz best-case backend frequencies.Synthesis used a 1 GHz worst-case constraint, and automated clock gates cover over 96% of FPU registers.Source: 1) Silicon Implementation · pp. 7–8

2) Static Impact of the TP-FPU:

FPnew combines a multi-format Ariane implementation with measurements of operation-level and core-level energy. The measurements show energy scaling across formats, while the size of whole-core savings depends on operation and vectorization.

2) Static Impact of the TP-FPU:

  • 9.3% more area and 11.1% more static energy than scalar FP32/FP64 Ariane accompany support for three additional formats and SIMD, which improves FP throughput by up to 8× on FP8 vectors.The TP-FPU Ariane core is 742 kGE, or 1.4 MGE including caches.Source: 2) Static Impact of the TP-FPU · p. 8

3) Silicon Measurements:

  • Synthetic tests use random normal FP inputs constrained to avoid overflow, with full pipelines operating at peak performance for operation-level energy measurements.Core and memory power measurements use matrix-matrix multiplication; voltage-scaling results come from manufactured-silicon measurements.Source: 3) Silicon Measurements · p. 8
  • 26.7 pJ for FP64 scalar FMA falls by 65% for FP32, with further format-width reductions also lowering scalar arithmetic energy.The reported reductions versus the next larger format include 48%, 54%, and 49% for FP16, FP16alt, and FP8 FMA; FP16alt uses 12% less energy than FP16.Source: 3) Silicon Measurements · p. 8
  • 20.0 pJ for FP32 SIMD FMA is accompanied by per-instruction energy gains of 20%, 31%, and 20% for FP16, FP16alt, and FP8.Per-datum gains for SIMD FMA are 60%, 66%, and 58%, respectively; format-specific execution slices allow idle slices to be clock-gated.Source: 3) Silicon Measurements · pp. 8–9
  • 30% and 35% energy reductions when halving FP cast widths are weaker than arithmetic scaling, while FP16/FP8 SIMD casts cost 9.5% less than FP32/FP16 casts.The merged conversion unit makes unused datapath portions harder to turn off; SIMD cast lanes for small formats are narrower and support fewer formats.Source: 3) Silicon Measurements · p. 9
  • Two FP64 values can be converted and packed into two destination-vector elements for roughly 30% more energy than one scalar FP64 conversion.Without cast-and-pack functionality, this would require two scalar casts and an additional packing operation not directly available in the ISA.Source: 3) Silicon Measurements · p. 9
  • Up to 25% energy gain is measured for FP16alt/int32 versus FP32/int32 scalar conversions, while shared vector lanes can make narrow-format SIMD casts costlier per datum.The authors attribute the vector-cast scaling to shared lanes across formats.Source: 3) Silicon Measurements · p. 9
  • 25.33 Gflop/s and 2.95 Tflop/s W are achieved on FP8, while FP8 FMA uses 10.5× less FPU energy than FP64 but reduces total core energy by 38%.Executing FP8 FMA vectorially requires a further 6.2× less total core energy.Source: 3) Silicon Measurements · p. 9, Figure 8 · p. 9, Figure 9 · p. 9

C. Performance and Programming of Transprecision Kernels

The case study compares precision, instruction count, and energy for element-wise products of FP16 input streams accumulated in FP16 or FP32. Expanding multi-format FMA recovers FP32-level precision at FP16 output with lower energy than the FP32 implementation.

1) Transprecision Application Case Study:

  • The workload accumulates element-wise products of two FP16 input streams, a pattern found in signal processing and SVM applications.The complete application repeats the operation over the input data using hardware loops and post-incrementing loads.Source: 1) Transprecision Application Case Study · p. 10
  • The five implementations range from three instructions per input pair for FP16-only to five for FP32 with casts; expanding multi-format FMA returns to three.SIMD accelerates the FP16 portion in 3.5 instructions; the FP32-only version provides 22 bits of precision, while FP16-only provides 9 correct bits versus 12 for the exact result rounded to FP16.Source: 1) Transprecision Application Case Study · p. 10
  • 37% lower core and system energy than the FP32 code, with the same performance as FP16-only and 14.6× greater accuracy after FP16 conversion.The comparison uses the expanding multiply-accumulate implementation in Fig. 11(e).Source: 1) Transprecision Application Case Study · p. 10, Table III · p. 10
  • SIMD reduces core energy by 3% and system energy by 25% versus FP32, while FP16 multiplication in the mixed-precision variant costs more energy than the casts it replaces.That mixed-precision variant uses 16% more core energy and 3% more system energy than FP32, with 19-bit accuracy.Source: 1) Transprecision Application Case Study · p. 10

2) Compiler Support:

Compiler support exposes scalar FP types, basic operations, and vector operations, but some efficient transprecision patterns still require intrinsics. Commercial and draft vector ISAs differ in their format support and vector semantics.

2) Compiler Support:

  • Scalar types and basic operations can use compiler-supported FP types and operators, and GCC vector extensions infer vector operations on custom formats.The compiler can generate SIMD code like Fig. 11(d) from the C code in Fig. 10(b).Source: 2) Compiler Support · p. 10, Figure 11 · p. 11
  • FMA and optimized SIMD access or conversion patterns often do not map cleanly to high-level operators, so cast-and-pack and expanding FMA can require intrinsics.The intrinsics can produce the expanding-FMA assembly shown in Fig. 11(e).Source: 2) Compiler Support · p. 10

A. SIMD and Transprecision in Commercial ISAs

  • x86-64 SSE/AVX supports FP32 and FP64 SIMD and dot products, while ARM NEON and SVE add FP16 or optional BF16 support with different vector and conversion semantics.SVE converts BF16 inputs to FP32 for computation; the RISC-V V draft supports FP16, FP32, FP64, FP128, and widening FMA, with target width exactly twice the source width.Source: A. SIMD and Transprecision in… · pp. 10–11
  • ARM MVE supports FP16 and FP32 with fixed 128-bit vectors that implementations may compute in one, two, or four beats, but it lacks multi-format operations.The passage contrasts MVE's predication, interleaving, and scatter-gather support with the described RISC-V extension.Source: A. SIMD and Transprecision in… · p. 11

B. Open-Source Configurable FPU Blocks

Existing configurable FPU components offer different trade-offs in format flexibility and IEEE 754 behavior, while RISC-V implementations emphasize consistent behavior. The related work also spans specialized reduced-precision accelerators and alternative number systems.

B. Open-Source Configurable FPU Blocks

  • FloPoCo permits configurable exponent and mantissa widths but omits IEEE 754 encodings for infinity and NaN, subnormals, and FMA; Hardfloat provides IEEE 754-compliant parametric functions including FMA.Both offer function blocks rather than fully featured FPUs, although the TP-FPU's hierarchical architecture can incorporate external implementations.Source: B. Open-Source Configurable FPU Blocks · p. 11

C. FPUs for RISC-V

  • Because IEEE 754 leaves some behavior implementation-defined, RISC-V precisely specifies open points—including NaN result bit patterns and rounding—to reduce hardware-related portability and reproducibility problems in floating-point code.Source: C. FPUs for RISC-V · pp. 11–12

D. Novel Arithmetics / Transprecision FP Accelerators

  • Google TPU and NVIDIA Tensor Cores accelerate reduced-precision neural-network operations, but omit some IEEE 754 features such as denormals or faithful rounding.The passage describes these optimizations as orthogonal to FPnew's focus on IEEE 754-like capabilities.Source: D. Novel Arithmetics / Transprecision… · p. 12
  • Other explored number systems include UNUMs, Posits, and LNS; the TP-FPU architecture could incorporate their dedicated functional units alongside its current FP functions.The passage also describes the datapath for posit arithmetic as similar to a merged functional unit with many possible input formats.Source: D. Novel Arithmetics / Transprecision… · p. 12

E. Multi-Mode Arithmetic Blocks

FPnew's parallel datapaths deliver energy-efficiency gains across formats, and the design has been adopted in other processors and vector systems. The conclusion reports embedded-core and silicon results alongside implementation overheads.

E. Multi-Mode Arithmetic Blocks

  • The authors report no previously published fully featured TP-FPU supporting multiple formats; the RISC-V FMA design in has 49% lower energy efficiency than FPnew on the same FP64 FMA operation.The comparison measures the complete TP-FPU for FPnew and contrasts it with standalone FMA blocks.Source: E. Multi-Mode Arithmetic Blocks · p. 12
  • Compared with the FP64 operation, FP8 reaches 16.6× lower energy, and voltage scaling increases that efficiency gain by another 2.3×.The passage attributes improved energy scaling over other multi-mode FMA designs to FPnew's parallel datapaths.Source: E. Multi-Mode Arithmetic Blocks · pp. 12–13, §VI · p. 13

F. Other uses of our TP-FPU

  • FPnew instances are used in Ara's vector processor, Snitch, GAP913, and hardware in the European Processor Initiative project.The cited uses span vector processing, FP64 and SIMD FP32 compute, and sub-32-bit transprecision computation.Source: F. Other uses of our TP-FPU · p. 13

VI. CONCLUSION

  • The embedded-core case achieves FP32 precision without performance overhead versus an optimal scalar FP16 baseline while reducing system energy by 34%; 8×FP8 SIMD reaches 25.33 Gflop/s.The application-class implementation supports five FP formats in GLOBALFOUNDRIES 22FDX; processor area and static energy rise by 9.3% and 11.1%, respectively.Source: §VI · p. 13
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