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A universal 3D imaging sensor on a silicon photonics platform
Christopher Rogers, Alexander Y. Piggott, David J. Thomson, Robert F. Wiser, Ion E. Opris, Steven A. Fortune, Andrew J. Compston, Alexander Gondarenko, Fanfan Meng, Xia Chen, Graham T. Reed, Remus Nicolaescu
TL;DR
Existing solid-state 3D imagers had not simultaneously achieved long range and millimetre-class accuracy for demanding applications. This work presents a scalable solid-state architecture with parallel coherent detection and demonstrates 3.1 mm precision at 75 m using 4 mW, while pointing toward large camera-scale arrays.
Problem
Existing solid-state 3D imaging systems were limited in simultaneously achieving long range and millimetre-class accuracy for demanding applications.
Method
The system combines transmitter and receiver focal-plane arrays, parallel heterodyne readout, and scalable switching-tree beam steering on a silicon-photonic platform.
Results
3.1 mm precision was achieved at 75 m with 4 mW of transmitted power, an order of magnitude more accurate than existing solid-state 3D imagers at these ranges.
Takeaways & Limitations
The architecture could support compact 3D imaging cameras spanning applications from robotics and autonomous navigation to consumer augmented-reality products.
Takeaways & Limitations
The prototype has a 280 MHz packaged-chip receiver bandwidth limited by the test setup, a 4× transmitter–receiver position mismatch, and transmission losses that constrain range.
Abstract
from arXiv · showhide
Accurate 3D imaging is essential for machines to map and interact with the physical world. While numerous 3D imaging technologies exist, each addressing niche applications with varying degrees of success, none have achieved the breadth of applicability and impact that digital image sensors have achieved in the 2D imaging world. A large-scale two-dimensional array of coherent detector pixels operating as a light detection and ranging (LiDAR) system could serve as a universal 3D imaging platform. Such a system would offer high depth accuracy and immunity to interference from sunlight, as well as the ability to directly measure the velocity of moving objects. However, due to difficulties in providing electrical and photonic connections to every pixel, previous systems have been restricted to fewer than 20 pixels. Here, we demonstrate the first large-scale coherent detector array consisting of 512 ($32 \times 16$) pixels, and its operation in a 3D imaging system. Leveraging recent advances in the monolithic integration of photonic and electronic circuits, a dense array of optical heterodyne detectors is combined with an integrated electronic readout architecture, enabling straightforward scaling to arbitrarily large arrays. Meanwhile, two-axis solid-state beam steering eliminates any tradeoff between field of view and range. Operating at the quantum noise limit, our system achieves an accuracy of $3.1~\mathrm{mm}$ at a distance of 75 metres using only $4~\mathrm{mW}$ of light, an order of magnitude more accurate than existing solid-state systems at such ranges. Future reductions of pixel size using state-of-the-art components could yield resolutions in excess of 20 megapixels for arrays the size of a consumer camera sensor. This result paves the way for the development and proliferation of low cost, compact, and high performance 3D imaging cameras.
SCALABLE 3D IMAGING ARCHITECTURE
The architecture combines sequential patch illumination with parallel receiver readout in two focal plane arrays, using solid-state switching to support scalable 3D imaging.
- SCALABLE 3D IMAGING ARCHITECTURE: The transmitter sequentially illuminates scene patches while the receiver detects scattered light from corresponding areas.Both arrays use on-chip thermo-optic switching trees for beam steering.
- SCALABLE 3D IMAGING ARCHITECTURE: Patch-based illumination improves long-range efficiency by directing light only onto the scene portion corresponding to the pixels being read out.The transmitter switching tree addresses one grating coupler at a time.
- SCALABLE 3D IMAGING ARCHITECTURE: The switching approach can scale to arbitrarily large arrays, with optical losses limited by waveguide scattering and switch-tree extinction ratio.The angular resolution is set by the lens point spread function.
- SCALABLE 3D IMAGING ARCHITECTURE: Parallel receiver readout defines resolution by the receiver pixel count rather than steering positions.Receiver pixels corresponding to the illuminated area are read out simultaneously.
- SCALABLE 3D IMAGING ARCHITECTURE: Parallel readout decouples pixel rate from switching rate and permits longer FMCW ramps with lower receiver signal frequencies.This simplifies the readout electronics and avoids requiring fast thermo-optic switching.
DESIGN OF HYBRID CMOS-PHOTONICS CHIP
The hybrid chip integrates dense heterodyne receiver pixels, low-noise electronics, optical switching, and multiplexed readout to improve efficiency, sensitivity, and scalability.
- DESIGN OF HYBRID CMOS-PHOTONICS CHIP: A 32 × 16 receiver array distributes local-oscillator light through silicon waveguides while grating couplers collect scattered scene light at each pixel.Balanced detectors convert the mixed optical signals into photocurrents.
- DESIGN OF HYBRID CMOS-PHOTONICS CHIP: 280 MHz receiver bandwidth and 2–3× lower noise floor than separate-chip photodiode-amplifier systems result from tight photodiode–TIA integration.The integrated design also achieves a similar gain-bandwidth product to conventional systems.
- DESIGN OF HYBRID CMOS-PHOTONICS CHIP: 5 µW of local-oscillator power brings shot noise to parity with amplifier noise in a typical receiver pixel.Balanced heterodyne detectors provide 30–40 dB common-mode rejection, while many pixels can share LO power.
- DESIGN OF HYBRID CMOS-PHOTONICS CHIP: The receiver signal chain uses in-pixel transimpedance amplification followed by row-level amplification and multiplexes 512 pixels to 8 outputs.Pixels are read out in blocks of 8, with subsequent off-chip digitization and FPGA processing.
- DESIGN OF HYBRID CMOS-PHOTONICS CHIP: A microlens-shaped transmitter pattern matched to receiver grating-coupler positions and produced a 24× improvement in signal strength.The transmitter illumination and receiver readout patterns were synchronized.
3D IMAGING AND VELOCIMETRY
The system demonstrates millimetre-scale depth measurements, velocity sensing, and point-cloud imaging at ranges up to 75 metres using low transmitted power.
- 3D IMAGING AND VELOCIMETRY: 1.8 mm precision at 17 m and 3.1 mm precision at 75 m were achieved for targets with 85% and 30% reflectance, respectively.The system operated with 4 mW emitter power, 4 GHz chirp bandwidth, and 850 µs up- and down-chirps.
- 3D IMAGING AND VELOCIMETRY: 1.0 mm/s velocity precision was measured for a basketball rotating at 1 rpm.Doppler splitting between up- and down-chirps encodes target velocity.
- 3D IMAGING AND VELOCIMETRY: Detection probability was 97% at 17 m and 42% at 75 m, with speckle affecting coherent LiDAR measurements.Detection probabilities were calculated without frame stacking.
- 3D IMAGING AND VELOCIMETRY: Point clouds were produced for a rotating basketball at 17 m, stacked boxes at 54 m, and an exterior wall at 75 m.Distance is encoded by colour for the box and wall point clouds.
- 3D IMAGING AND VELOCIMETRY: A narrow receiver-array routing gap creates a missing band of points in the point clouds.The gap is due to electrical and optical routing.
DISCUSSION AND OUTLOOK
The demonstrated solid-state 3D imaging architecture combines long range, millimetre-class accuracy, low transmitted power, and scalable array design. Proposed improvements could extend range, point rate, and depth precision, supporting applications from autonomous navigation to consumer devices.
- DISCUSSION AND OUTLOOK: 3.1 mm precision at > 70 m range is achieved with only 4 mW of transmitted power.The authors report this as an order of magnitude higher accuracy than existing solid-state 3D imagers at these ranges.
- DISCUSSION AND OUTLOOK: Correcting the 4× transmitter–receiver position mismatch and increasing transmitter power could improve system range.The authors also identify lower photonic transmission losses, wider waveguides, and reverse-biased PIN junctions as routes to higher power.
- DISCUSSION AND OUTLOOK: State-of-the-art components could enable approximately 200 µm depth precision through increased chirp bandwidth.This projection is based on demonstrations of 50 GHz silicon photonic modulators.
- DISCUSSION AND OUTLOOK: At 8×5 µm2 pixel sizes, full-frame camera sensors could reach 4500×4800-pixel resolution.The current 80×100 µm2 receiver pixel pitch would provide QVGA resolution on a 36×24 mm2 chip.
- DISCUSSION AND OUTLOOK: The architecture is positioned as a universal solid-state 3D imaging platform spanning robotics, autonomous navigation, and augmented reality headsets.The authors suggest it could become the 3D-imaging analogue of the CMOS image sensor.
Methods
The system combines externally generated FMCW chirps, monolithically integrated photonic-electronic hardware, multiplexed receiver readout, and calibrated optical switching for 3D imaging. Its prototype uses a 512-pixel receiver, but performance is bounded by measured packaging bandwidth, switching-tree losses, and a fourfold transmit–receive steering mismatch.
- Hardware: The demonstrator was fabricated in a 300 mm silicon photonics process monolithically integrating photonic devices with 90 nm RF CMOS electronics.The design primarily used standard foundry process-development-kit photonic devices.
- FMCW processing: Mean and difference of up-chirp and down-chirp beat frequencies separately measure target range and velocity.Low-velocity measurements use one 850 µs up-chirp followed by one 850 µs down-chirp; fast-object measurements use coherent combinations of multiple shorter chirps.
- FMCW generation: An external 1550 nm laser was linearly chirped using a silicon-photonic IQ Mach-Zehnder modulator driven by an arbitrary waveform generator.The approach provides chirp linearity while allowing use of a simple, low-noise laser.
- Characterization: Receiver bandwidth was 280 MHz through the packaged chip, versus 750 MHz simulated for the on-chip amplifier chain.The discrepancy suggests that the test setup limited the measured bandwidth.
- System operation: The prototype illuminates 32 receiver pixels per transmitter position while reading out eight, creating a fourfold steering-position mismatch.Correcting this mismatch gives an equivalent point rate of 2×10^4 per second with 4 mW emitter power and 0.2 µJ per point.