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Demonstration of quantum volume 64 on a superconducting quantum computing system
Petar Jurcevic, Ali Javadi-Abhari, Lev S. Bishop, Isaac Lauer, Daniela F. Bogorin, Markus Brink, Lauren Capelluto, Oktay Günlük, Toshinari Itoko, Naoki Kanazawa, Abhinav Kandala, George A. Keefe, Kevin Krsulich, William Landers, Eric P. Lewandowski, Douglas T. McClure, Giacomo Nannicini, Adinath Narasgond, Hasan M. Nayfeh, Emily Pritchett, Mary Beth Rothwell, Srikanth Srinivasan, Neereja Sundaresan, Cindy Wang, Ken X. Wei, Christopher J. Wood, Jeng-Bang Yau, Eric J. Zhang, Oliver E. Dial, Jerry M. Chow, Jay M. Gambetta
TL;DR
The paper addresses how to improve quantum-circuit quality on superconducting systems as measured by quantum volume. It combines compiler improvements with dynamical decoupling, faster two-qubit gates, and excited state promoted readout, reaching QV64 and highlighting hardware-aware circuit optimization.
Problem
Improving quantum-volume circuits requires addressing compilation, idle-qubit noise, gate duration, and measurement fidelity together.
Method
The authors combine Qiskit compiler optimizations, dynamical decoupling, a shorter direct CX gate, and excited state promoted readout.
Results
QV64 was achieved with a heavy output probability of 0.701 ± 0.031, exceeding the 2/3 threshold at a 98.744% confidence interval.
Takeaways & Limitations
Circuit fidelity is not equivalent to individual gate fidelity, supporting hardware-aware optimization and circuit benchmarks such as quantum volume.
Abstract
from arXiv · showhide
We improve the quality of quantum circuits on superconducting quantum computing systems, as measured by the quantum volume, with a combination of dynamical decoupling, compiler optimizations, shorter two-qubit gates, and excited state promoted readout. This result shows that the path to larger quantum volume systems requires the simultaneous increase of coherence, control gate fidelities, measurement fidelities, and smarter software which takes into account hardware details, thereby demonstrating the need to continue to co-design the software and hardware stack for the foreseeable future.
I. INTRODUCTION
The paper targets higher quantum volume by improving both the Qiskit compiler and low-level circuit-control techniques. Combining these changes enables QV64 on ibmq montreal with HOP 0.701 ± 0.031 and 98.744% confidence.
- Quantum volume is a holistic benchmark sensitive to gate errors, measurement errors, compiler quality, and spectator errors.
- The authors improve the Qiskit compiler to reduce gate counts and circuit depths.
- The system combines compiler improvements, ESP readout, shorter two-qubit gates, and dynamical decoupling on idle qubits.
- QV64 reaches a heavy output probability of 0.701 ± 0.031, exceeding the 2/3 threshold with 98.744% confidence.The test requires exceeding 2/3 HOP by a 97.725% confidence interval.
- The paper presents timing and pulse control as necessary components of improving cloud quantum systems.
II. QUANTUM SYSTEM - ibmq montreal
ibmq montreal is a 27-qubit Falcon processor whose heavy-hex connectivity balances routing efficiency against collision, cross-talk, and spectator-error risks. QV64 was demonstrated using six qubits with the reported device properties and gate implementations.
- The Falcon processor contains 27 qubits arranged for a distance-3 hybrid Bacon-Shor-surface code.
- Its heavy-hex connectivity compromises between minimizing qubit distance and reducing frequency collisions, cross-talk, spectator errors, and SWAP overhead.
- QV32 was measured on the last seven deployed systems, demonstrating the reliability of this architecture.
- QV64 circuits ran on the six-qubit line Q16-Q19-Q22-Q25-Q24-Q23.Average properties were T1 = 113 µs, T2 = 122 µs, single-qubit gate error 3.8 × 10−4, two-qubit gate error 6.4 × 10−3, and single-qubit readout assignment error 6.0 × 10−3.
- Single-qubit gates last 21.33 ns, while cross-resonance-based two-qubit gates last 199−309 ns.The two-qubit implementation uses a target rotary pulse and an offset pulse shape for a direct echoless CNOT.
III. COMPILER
The compiler is improved through hardware-aware mapping, routing, pulse-efficient SU(4) and SWAP decompositions, native-gate targeting, and additional circuit simplification. These changes reduce entangling-gate use and circuit duration while accounting for hardware direction and fidelity.
- Qubit layout and routing: Binary integer programming maps and routes circuits under connectivity constraints by optimizing an effective-fidelity cost function.The cost models gate fidelities, circuit depth, direct mappings, mirrored mappings, and added SWAP gates.
- Qubit layout and routing: Around one second per circuit is sufficient to solve the restricted BIP routing problem to optimality.Restricting candidate SWAP insertion sites reduces problem size, while mirrored implementations eliminate many explicit SWAP gates.
- Pulse-efficient decomposition: The compiler introduces pulse-efficient SU(4) and SWAP decompositions that reduce single-qubit pulse cost and create further cancellation opportunities.The constructive SU(4) decomposition is pulse-optimal by parameter counting, places 8 of 10 single-qubit pulses externally, and enables merging with neighboring gates.
- Compiler evaluation: Across 2000 QV64 circuits, improved mapping lowers CX counts while pulse-efficient compilation lowers single-qubit counts, shortening circuit durations.The comparison is against the state-of-the-art Qiskit SABRE compiler on line connectivity, with basis-gate fidelity Fb = 0.99 assumed for approximate SU(4) expansion.
- Hardware-aware synthesis: Hardware-aware decomposition uses the natural two-qubit gate direction and can target native ECR gates instead of constructing direct CNOTs.Correct-direction synthesis avoids additional local rotations; native ECR targeting yields an additional 7% reduction in mean duration.
IV. DYNAMICAL DECOUPLING
QV64 circuits on line-connected transmons contain substantial idle periods caused by routing and unequal two-qubit gate durations. Dynamical decoupling inserts echo pulses into these gaps to mitigate idle-qubit errors and improves heavy output probability for most tested circuits.
- Idle-time sources: Idle times occupy a significant portion of QV64 circuit duration on a line of transmon qubits.Nearest-neighbor routing requires 7.3 SWAPs on average, while unequal two-qubit durations create additional temporal gaps.
- Idle-time sources: Two-qubit gate durations differ by a factor of 1.5−2, and these gates are approximately 10× longer than single-qubit gates.The resulting timing differences accumulate and leave individual qubits idle during computation.
- Idle-qubit errors: Idle qubits are vulnerable to thermal relaxation, dephasing, cross-talk, and spectator interactions rather than evolving as an ideal identity operation.Dynamical decoupling addresses low-frequency noise using refocusing echo pulses.
- Dynamical-decoupling protocol: The successful QV64 measurement used a τ_i,q/2−Xp−τ_i,q−Xm−τ_i,q/2 echo sequence during idle intervals.Xp and Xm are π-pulses around the x-axis with positive and negative rotation sense, respectively.
- Dynamical-decoupling results: 72.8% of tested circuits improved with dynamical decoupling, with an average heavy output probability increase of 0.0178.The comparison used identical QV circuits run with the Xp−Xm sequence and without dynamical decoupling.
V. DIRECT CX GATE
The paper develops shorter direct CX gates and shows that circuit-level performance depends on balancing gate duration with circuit optimization. QV64 uses a 199 ns direct CX gate, below the duration minimizing two-qubit gate error.
- Gate duration and circuit performance: 57 two-qubit gates and 146 single-qubit gates occur on average in QV64 circuits, making gate speed important for total circuit duration.The circuit also contains substantial idle periods, so individual-gate fidelity alone does not determine circuit performance.
- Gate duration and circuit performance: Separately compiling single-qubit rotations reduces the ECR-based two-qubit gate to its entangling portion.The comparison includes ECR CX, ECR, and direct CX implementations.
- Direct CX implementation: A direct echo-free CX sequence further removes a single-qubit gate from the total two-qubit gate duration.The sequence uses symmetric and antisymmetric target-drive components to implement active cancellation and target rotary tones.
- Gate duration and circuit performance: Reducing gate duration lowers two-qubit gate error, but shortening below the randomized-benchmarking optimum can increase QV-circuit HOP.This demonstrates the need to balance circuit optimization with gate optimization.
- QV64 operating point: 199 ns was the direct CX duration used for QV64, shorter than the duration that minimizes two-qubit gate error.The selected duration reflects circuit-level optimization rather than isolated gate-error minimization.
VI. STATE INITIALIZATION AND READOUT
Because quantum volume is sensitive to state-preparation and measurement errors, the paper examines reset and readout performance. Excited state promotion improves discrimination by transferring |1⟩ to |f⟩ before measurement while adapting the reset protocol.
- Motivation: Quantum volume is sensitive to state-preparation and measurement errors, unlike metrics designed to be insensitive to SPAM errors.Initialization and measurement are therefore part of the holistic QV system measure.
- Initialization: Passive reset waits multiple T1 relaxation times, which can limit computational repetition rates as coherence times increase.The paper notes that active reset schemes have therefore been proposed and demonstrated.
- Initialization: The standard deployed procedure has reset error ERS = 2.8 × 10−2 for the six-qubit ground state |0 . . . 0⟩.This value is inferred from the readout matrix.
- Readout: Standard readout gives a total assignment error of ESP = 0.10 for all 26 states.Single-qubit signals are integrated in the I-Q plane after amplification and filtering.
- Excited state promotion: Excited state promotion applies an additional π-pulse |1⟩→|f⟩ before measurement and discriminates |0⟩ from |f⟩.The stronger dispersive shift and two-step relaxation reduce false |0⟩ assignments, while reset is adapted as reset - π|f⟩→|1⟩ - reset.
VII. CONCLUSION
The paper achieves quantum volume 64 on a superconducting quantum system by combining compiler, gate, dynamical-decoupling, and readout improvements. The result emphasizes hardware-aware circuit benchmarks and lower-stack software–hardware co-design for noisy quantum systems.
- Conclusion: The work demonstrates an improvement in the quantum volume of a state-of-the-art superconducting quantum system.The demonstrated quantum volume is 64.
- Conclusion: QV64 results from four combined factors: Qiskit compiler improvements, two-qubit gate and calibration refinements, dynamical decoupling, and excited state promoted readout.The last three techniques required lower-stack access to pulse and gate definitions.
- Conclusion: Circuit-fidelity optimization is not equivalent to optimizing individual gates, confirming the need for circuit benchmarks such as quantum volume.The conclusion frames hardware-aware circuit-performance improvements as characteristic of noisy quantum systems.