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AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong
TL;DR
Software programmers face a steep learning curve in FPGA design, including manual code reconstruction and parameter tuning for HLS. AutoDSE uses bottleneck-guided coordinate optimization to search for better configurations. It reports 19.9× geometric-mean speedup over one CPU core on MachSuite and Rodinia, and similar Vitis vision-kernel performance with 26.38× fewer optimization pragmas.
Problem
FPGA design remains difficult for software programmers because high-performance HLS kernels require manual code reconstruction and tuning, while HLS behavior complicates reliable design-space exploration.
Source: §1 · pp. 2, 4Method
AutoDSE treats HLS as a black box and uses a bottleneck-guided coordinate optimizer to prioritize impactful design parameters.
Source: §5.2 · p. 13, §7 · p. 21Results
AutoDSE achieves 19.9× geometric-mean speedup over a single-thread CPU on MachSuite and Rodinia, with a 7% performance gap versus manual designs.
Source: §1 · p. 4Takeaways & Limitations
AutoDSE achieves similar performance on Xilinx Vitis vision kernels with a 26.38× reduction in optimization pragmas, requiring less than one per kernel on the geometric mean.
Source: §1 · p. 4The bottleneck-guided optimizer cannot determine whether a parameter option is locally or globally optimal.
Source: §5.5 · p. 17
Abstract
from arXiv · showhide
Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS), accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve the optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an automated DSE framework-AutoDSE- that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point. AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that AutoDSE is able to identify the design point that achieves, on the geometric mean, 19.9x speedup over one CPU core for Machsuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38x while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.
1 Introduction
HLS makes FPGA programming more accessible, but software programmers still face difficult architectural optimization and parameter tuning. AutoDSE automates design-space exploration with bottleneck-guided search, achieving strong benchmark speedups and similar vision-kernel performance with fewer manual optimization pragmas.
1 Introduction
- FPGAs are difficult for software programmers because high-performance designs require code reconstruction and FPGA-specific pragma selection and tuning.The example kernel is 80× slower than one CPU core before optimization; optimized code reaches around 7,041× speedup after bottleneck analysis, code transformations, and 28 pragmas.Source: §1 · pp. 2–3
- HLS design-space exploration must contend with exponentially many configurations, non-monotonic parameter effects, interacting pragmas, tool-version differences, and long synthesis times.Even pipeline, unroll, and array-partition pragmas produce 1020 design points for Code 1; HLS synthesis typically takes 5–30 minutes.Source: §1 · pp. 3–4
- AutoDSE treats HLS as a black box and combines coordinate-descent guidance with bottleneck-guided optimization to search for better configurations.It also represents grid design spaces with list-comprehension syntax and marks invalid points.Source: §1 · p. 4
- AutoDSE evaluates 33 Xilinx Vitis vision kernels and reports similar performance with a 26.38× reduction in optimization pragmas.The geometric mean is less than one required optimization pragma per kernel.Source: §1 · p. 4
- 19.9× geometric-mean speedup over a single-thread CPU on MachSuite and Rodinia, with only a 7% performance gap versus manual designs.On Xilinx Vitis vision kernels, AutoDSE also achieves similar performance with a 26.38× reduction in optimization pragmas.Source: §1 · p. 4
2 Problem Formulation
The formulation seeks a feasible HLS configuration that minimizes execution cycles within a search-time limit. It also frames the problem as trading off manual optimization pragmas against performance gained through automatic pragma application.
2 Problem Formulation
- The design space combines possible HLS pragma configurations, while the programmer is expected to insert a minimal number of optimization pragmas manually.AutoDSE inserts the remaining pragmas automatically.Source: §2 · p. 5
- The DSE objective is to minimize execution cycles for a configuration that fits FPGA resource limits within a given search-time limit.The HLS tool supplies cycle and resource estimates as a black-box evaluation function; the experiments set resource thresholds to 0.8.Source: §2 · p. 5
- The formulation trades off fewer manually inserted optimization pragmas against performance, targeting expert-library performance with less manual pragma work.The reported Vitis-library comparison achieves a 26.38× pragma reduction and requires fewer than one optimization pragma per kernel on the geometric mean.Source: §2 · p. 5
3 Related Work
Prior HLS design-space exploration work includes model-based and model-free methods. The paper contrasts their limitations in accuracy, portability, scalability, and search guidance.
3 Related Work
- Related work divides automated HLS design-space exploration into model-based and model-free techniques.The model-free approaches evaluate designs by invoking the HLS tool rather than relying on a predictive model.Source: §3 · p. 5, §3.2 · p. 6
3.1 Model-based Techniques
- Analytical models can search quickly, but non-monotonic parameter effects, tool-specific behavior, and application-specific assumptions constrain their accuracy and generality.Learning-based models still require new samples and retraining when the HLS tool or target FPGA changes.Source: §3.1 · pp. 5–6
3.2 Model-free Approaches
- Model-free methods invoke HLS for evaluations, but general heuristics can be unreliable and sampling-based approaches can scale poorly as design spaces grow.Gaussian-process Bayesian optimization also incurs cubic computation in the number of samples.Source: §3.2 · p. 6
4 The AutoDSE Framework
AutoDSE builds on Merlin to define a smaller design space and searches it through partitioning and bottleneck-based coordinate exploration. Merlin pragmas enable architectural optimizations while limiting manual code reconstruction.
4 The AutoDSE Framework
- AutoDSE uses the Merlin Compiler as its backend to reduce the design-space size before conducting DSE.Merlin performs source-level code reconstruction and generates many of the required HLS pragmas.Source: §4 · p. 6, §4.1 · p. 7
4.1 Merlin Compiler and Design Space Definition
- Merlin converts high-level directives into HLS pragmas; coarse-grained pipelining enables double buffering, while fine-grained pipelining fully unrolls sub-loops.The compiler also performs source-to-source transformations to apply the corresponding architecture optimizations.Source: §4.1 · p. 7
- 4 Merlin pragmas match the performance of a manually optimized HLS CNN design using 28 pragmas, without further manual code transformation.Merlin transforms the code after the four pragmas are inserted.Source: §4.1 · p. 7
- Merlin handles bottlenecks 1 and 2 by default, while AutoDSE searches pragma locations and settings to address bottlenecks 3–5.The paper describes this as enabling architectural optimizations alongside the best pipelining and parallelization attributes.Source: §4.1 · p. 7
- AutoDSE defines each kernel’s design space by analyzing its AST for loop trip counts, available bit-widths, and related information.The enforced design-space-building rules are listed in Section 5.4.Source: §4.1 · p. 7
- The CNN example’s four DRAM buffers and thirteen loops yield approximately 10^16 design configurations across pragma choices.The passage identifies this large search space as motivation for an efficient search approach.Source: §4.1 · p. 8
4.2 Framework Overview
- AutoDSE builds a Merlin-backed design space, partitions it with K-Means, and explores each partition using bottleneck-based coordinate search.The explorer evaluates design points against configurable targets and reallocates working threads as partitions finish.Source: §4.2 · p. 8
5 AutoDSE Methodology
AutoDSE replaces application-oblivious search with bottleneck-guided exploration and adds parameter ordering, constrained design-space representation, and partitioning. Together, these methods focus exploration on impactful choices while addressing infeasible options and local optima.
5 AutoDSE Methodology
- AutoDSE’s methodology moves from application-oblivious heuristics to a bottleneck-guided coordinate optimizer, then adds further optimizations to improve framework performance.The approach is intended to mimic an expert’s optimization method and generate high-quality design points in fewer iterations.Source: §5 · p. 8
5.1 Application-oblivious Heuristics
- Coordinate descent achieved 2.8× geometric-mean speedup on MachSuite and Rodinia, below S2FA, while evaluating all K parameters can waste runs on currently irrelevant settings.S2FA took an average of 16.8 hours to find its best solution.Source: §5.1 · pp. 9, 11
5.2 AutoDSE Exploring Strategy - Bottleneck-guided Coordinate Optimizer
- Merlin cycle breakdowns map bottleneck statements to parameters, guiding the optimizer to explore promising design points and select options based on whether the bottleneck is memory transfer or computation.For Code 1, the convolution takes 85.2% of cycles, and the method improves performance by 218× after two iterations.Source: §5.2 · pp. 12–13
5.3 Parameter Ordering
- Fine-grained-first ordering reached the best point in fewer iterations; for Code 1 line 15, it enabled synthesis in 28 minutes versus timeout under coarse-grained-first with a 60-minute limit.The HLS tool schedules fine-grained optimizations better than coarse-grained ones.Source: §5.3 · pp. 14–15, Table 4 · p. 15
5.4 Efficient Design Space Representation
- Conditional list-comprehension design spaces preserve the grid while excluding infeasible combinations, reducing space size and allowing Python-compatible evaluation.For example, coarse-grained PIPELINE and PARALLEL are exclusive within a loop nest.Source: §5.4 · pp. 15–16
5.5 Design Space Partitioning
- Bottleneck-guided optimization still cannot determine whether a parameter option is locally or globally optimal, so AutoDSE partitions the space by pipeline mode and explores representative partitions.It profiles partitions and uses K-means with performance and area to select representatives.Source: §5.5 · p. 17
6 Evaluation
The evaluation tests AutoDSE on MachSuite, Rodinia, an Alexnet convolution layer, and Xilinx Vitis vision kernels. It reports speedups over CPU and comparisons with manual designs and other DSE approaches.
6.1 Experimental Setup
- AutoDSE was evaluated on EC2 using an r4.4xlarge instance for DSE and an F1 f1.2xlarge instance with a Virtex UltraScale+ VU9P FPGA for accelerator evaluation.Benchmarks included MachSuite, Rodinia, one Alexnet convolution layer, and Xilinx Vitis vision kernels.Source: §6.1 · p. 17
6.2 Evaluation of Optimization Techniques
- 13.52× geometric-mean speedup followed original coordinate descent, and the proposed optimization strategies added a further 2.47×.The strategies benefited at least one benchmark each; list-based representation helped several kernels, while partitioning helped designs with many loop nests.Source: §6.2 · p. 18
- 19.9× speedup over CPU and 0.93× the performance of manual designs were achieved on the geometric mean, with a 1.1-hour search.AutoDSE uses the bottleneck-guided coordinate optimizer with parameter ordering, design-space representation, and partitioning.Source: §6.2 · p. 18
- The bottleneck-guided search can miss high-impact parameters when HLS reports do not accurately estimate cycles for kernels with many unbounded or while-loops.Without an accurate cycle breakdown, the analyzer may focus on unimportant parameters.Source: §6.2 · p. 18
6.3 Comparison with Other DSE Approaches
- AutoDSE outperformed S2FA, lattice-traversing DSE, and Gaussian process-based Bayesian optimization by 3.6×, 4.3×, and 17.9×, respectively, on the geometric mean.Table 5 compares designs found after the same allotted tool time; the other works did not report performance for every tested kernel.Source: Table 5 · p. 19, §6.3 · p. 19
- Merlin’s automatic transformations support common optimizations, but the comparison with S2FA indicates that using Merlin alone does not remove the need for efficient design-space exploration.Merlin can apply memory burst, memory coalescing, and double buffering, allowing AutoDSE to focus on high-level hardware changes.Source: §6.3 · p. 19
6.4 Comparison with Expert-level Manual HLS Designs
- With the searched optimization pragmas removed, AutoDSE added 3.2 Merlin pragmas per kernel on average and improved performance by 9.04× over the Vitis tool and 1.04× over manually optimized kernels.Table 6 reports geometric-mean speedups over the manually optimized kernels.Source: Table 6 · p. 20, §6.4 · p. 20
- AutoDSE achieved the same or better performance than Xilinx Vitis vision kernels with 26.38× fewer optimization pragmas on the geometric mean.The comparison covered 33 kernels and took 0.3 hours on the geometric mean; less than one optimization pragma per kernel was required on average.Source: §6.4 · p. 20
7 Conclusion and Future Work
The conclusion presents AutoDSE as a push-button, bottleneck-guided approach to HLS design-space exploration. It assumes access to HLS performance breakdowns and identifies additional transformations and placement-and-routing-based QoR estimation as future work.
7 Conclusion and Future Work
- AutoDSE uses synthesis results to estimate QoR rather than placement-and-routing results, which are too time-consuming for exploring sufficient design points within a reasonable time budget.The framework combines bottleneck-guided coordinate optimization, parameter ordering, design-space pruning, and partitioning to address search challenges.Source: §7 · p. 21
- The approach assumes that HLS tools provide performance breakdowns so AutoDSE can perform bottleneck-driven design-space exploration.The conclusion notes that Xilinx HLS provides this information and Intel OpenCL was planning to add it.Source: §7 · p. 21
- Future work will add transformations for data-access and reuse patterns and estimate QoR from placement-and-routing results using a model trained on synthesis results.Source: §7 · p. 21
A.1 Optimized HLS Code for CNN
The appendix presents optimized HLS C code for the CNN algorithm, applying code transformations and pragmas listed in Table 1.
A.1 Optimized HLS Code for CNN
- The code applies array partitioning to bias, intermediate, weight, output, and input buffers.The shown directives use complete or cyclic partitioning with specified dimensions and factors.Source: §A.1 · p. 24
- The CNN initialization and convolution loops use pipeline and unroll pragmas to expose parallel work.The code also unrolls loops over output channels and kernel dimensions.Source: §A.1 · pp. 24–25
- The code organizes the CNN work into bias loading, convolution, ReLU and max pooling, and output storage stages.Source: §A.1 · pp. 24–25
A.2 Detailed Comparison to the Vitis Library
The appendix compares AutoDSE with expert-level manual designs from Xilinx Vitis libraries. It reports comparable performance with substantially fewer optimization pragmas.
A.2 Detailed Comparison to the Vitis Library
- AutoDSE achieved the same performance as the Vitis designs while using 26.38× fewer pragmas on the geometric mean.Source: §A.2 · p. 25
- Figure 7 presents the detailed performance comparison with Xilinx results alongside the number of removed pragmas.Source: Figure 7 · p. 25, §A.2 · p. 25