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Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives

M. F. Gonzalez-Zalba, S. de Franceschi, E. Charbon, T. Meunier, M. Vinet, A. S. Dzurak

arXiv:2011.11753v2quant-phcond-mat.mes-hall

TL;DR

The paper examines how to scale quantum computing systems when conventional miniaturization faces increasing complexity and cost, focusing on CMOS-based silicon platforms. It reviews system-level architectures, device and materials requirements, and classical-electronics challenges, concluding that CMOS could enable compact integration but large-scale fault-tolerant systems require advances beyond current VLSI capabilities.

  • Problem

    Scaling quantum computing to enough error-free resources for useful algorithms requires high-fidelity qubits and system-level integration, but large-scale architectures and manufacturing remain challenging.

  • Method

    The paper reviews silicon quantum-computing scaling prospects across the quantum layer, quantum-classical interface, classical processing, CMOS fabrication, and cryogenic operation.

  • Results

    CMOS could support compact integration and low-cost manufacturing, while higher-temperature operation may increase cooling power but currently reduces fidelity and can increase qubit and electronics requirements.

  • Takeaways & Limitations

    Large-scale fault-tolerant silicon processors require development beyond current VLSI technology, although the authors foresee no fundamental roadblock.

Abstract

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Complementary metal-oxide semiconductor (CMOS) technology has radically reshaped the world by taking humanity to the digital age. Cramming more transistors into the same physical space has enabled an exponential increase in computational performance, a strategy that has been recently hampered by the increasing complexity and cost of miniaturization. To continue achieving significant gains in computing performance, new computing paradigms, such as quantum computing, must be developed. However, finding the optimal physical system to process quantum information, and scale it up to the large number of qubits necessary to build a general-purpose quantum computer, remains a significant challenge. Recent breakthroughs in nanodevice engineering have shown that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge. In this article, we focus on the analysis of the scaling prospects of quantum computing systems based on CMOS technology.

A QUANTUM COMPUTING SYSTEM

A scalable silicon quantum computing system must be designed as a full stack comprising quantum, interface, and classical layers. CMOS-compatible integration could support compact architectures, but the physical arrangement remains flexible.

  • A QUANTUM COMPUTING SYSTEM: A quantum computing system shifts focus from few-qubit demonstrations to coordinated quantum, quantum-classical, and classical layers.The quantum layer contains the QPU; the interface controls and reads out qubits; the classical layer supports error correction and algorithm execution.
  • A QUANTUM COMPUTING SYSTEM: The quantum layer uses a two-dimensional qubit distribution with nearest-neighbour interactions, separating data qubits from X- and Z-syndrome measurement qubits.X- and Z-syndrome qubits measure bit-flip and phase-flip errors, respectively.
  • A QUANTUM COMPUTING SYSTEM: The interface combines signal generation, conversion, amplification, modulation, and multiplexing to manage QPU control, readout, routing, and I/O.Its components include ADCs, DACs, amplifiers, and (de)multiplexers.
  • A QUANTUM COMPUTING SYSTEM: The classical layer correlates QPU outputs with error type, location, and time, while fast feedback supports universal computation and algorithm compilation.Processing may use an FPGA or ASIC within cryogenic cooling-power constraints.
  • A QUANTUM COMPUTING SYSTEM: CMOS-based quantum systems may flexibly arrange layers and could resemble image sensors, whose competing technologies offer different integration specifications.The analogy concerns physical architecture rather than identical device operation.

Qubit arrays

Scaling silicon spin qubits requires dense, high-fidelity arrays, scalable control, and interaction schemes that manage routing, crosstalk, and connectivity. Modular arrays, global fields, and mediator structures are possible approaches, but several remain experimentally or architecturally constrained.

  • Qubit arrays: Commercial CMOS lines must fabricate dense two-dimensional arrays of individually addressable quantum dots with gate-controlled tunnel barriers.Gate electrodes have used footprints around 40 × 40 nm with 70 nm pitch, while routing and exchange-gate placement remain challenging.
  • Qubit arrays: Modular one-dimensional and bilinear quantum-dot arrays could scale progressively toward sparse two-dimensional connectivity while reserving space for routing and electronics.The proposed sequence is 1D arrays followed by combined 2D modules.
  • Qubit arrays: Single-qubit fidelities exceed 99.9% in 200 ns, while two-qubit fidelities reached 98% in 5 µs and recently exceeded 99%.The target is gate-set fidelity well above 99% across large arrays on timescales around a microsecond or less.
  • Qubit arrays: On-chip microwave antennas control few-qubit systems but scale poorly because antenna count and microwave-current heat increase with qubit number.Global AC magnetic fields and compact dielectric resonators are proposed alternatives; KTaO3 resonators have demonstrated single-spin ESR and coherent control.
  • Qubit arrays: Intrinsic spin-orbit coupling may simplify qubit cells, with finFET-based single-hole spin qubits controlled near the fault-tolerant threshold at 1.5 K using 147 MHz rotations.This approach can avoid additional control elements required for some micro-magnet-based schemes.
  • Qubit arrays: Exchange modulation and resonant gates provide two-qubit control options, while a CPhase gate has reached 99.5% fidelity in 100 ns.Mediator quantum dots could extend interactions beyond nearest neighbours, but silicon demonstrations remain outstanding and interaction range is expected to be reduced.
  • Qubit arrays: Large-scale control must characterize and compensate crosstalk among target, idling, and simultaneously addressed qubits.Gate sets should be benchmarked jointly for fidelity, operation time, and effects on idling qubits.

High-fidelity readout

Silicon spin readout converts spin information into charge or resonator responses, with high-frequency and dispersive methods offering more compact or multiplexable architectures. Scaling remains limited by sensor integration and resonator footprint.

  • High-fidelity readout: Spin-dependent tunnelling converts spin information into charge signals detected by sensitive electrometres such as SETs.Elzerman readout and Pauli spin blockade are the cited tunnelling mechanisms.
  • High-fidelity readout: SET-based readout achieved 99.9% fidelity in 6 µs and 99% in 1.6 µs using amplifier-proximity and rf-SET techniques, respectively.SETs require close placement and two charge reservoirs, complicating dense-array scaling.
  • High-fidelity readout: The rf-SEB offers a two-terminal dispersive sensor, while IDR removes the charge sensor and reservoirs by embedding the qubit in an electrical resonator.Demonstrated fidelities were 99% in 1 ms for rf-SEB and 98% in 6 µs for IDR.
  • High-fidelity readout: FDMA enables simultaneous readout, TDMA can share a resonator sequentially, and quantum-limited amplification may accelerate dispersive readout.These techniques target reduced resonator count and faster signal processing.
  • High-fidelity readout: High-frequency readout resonators typically exceed 100 × 100 µm, creating a substantial scaling challenge.High-inductance-density materials, including Josephson metamaterials and high-kinetic-inductance materials, are proposed to reduce footprint, though CMOS integration may be complex.
  • High-fidelity readout: Further scaling of SET readout requires compact low-power amplifiers, multiplexing, and methods that resolve femtofarad-scale tunnelling capacitance.The discussion also points beyond charge sensors and IDR toward adapted classical-electronics concepts.

Qubit variability

Manufacturing high-fidelity silicon qubits at scale is difficult because atomic-scale defects and process variation strongly affect quantum-device parameters. Materials engineering and wafer-scale cryogenic characterization are therefore central requirements.

  • Qubit variability: Quantum-device variability is more consequential than conventional VLSI reproducibility because a single atomic defect can alter tunnel coupling or valley splitting.Interface quality, material purity, and crystallinity require particular attention.
  • Qubit variability: Isotopically enriched Si or Si/Ge stacks are needed to provide nuclear-spin-free active substrates and suppress hyperfine-related spin dephasing.The paper identifies enriched 28Si silane and depleted 73Ge germane as relevant process modules.
  • Qubit variability: Gate-stack development must minimize trapped charge densities below 10^11 cm−2, emphasizing high-quality Si-SiO2 interfaces.Cryogenic thermal-contraction mismatch can generate defects, strain, and variation in quantum-dot locations.
  • Qubit variability: Electron-spin operation frequencies vary primarily through G-tensor variation influenced by device and material parameters, with MOS quantum-dot ∆g/g ≈ 10−2.Stark shifts may partially mitigate these variations, subject to experimental constraints.
  • Qubit variability: Wafer-scale cryogenic probing and cryogenic multiplexers are needed to evaluate process-induced variability statistically and guide its control.The goal is to correlate process changes with variability and identify optimization routes.

Modelling

CMOS-inspired microscopic modelling methods are being adapted to silicon qubits, with the longer-term goal of connecting device descriptions to array-level simulation.

  • Modelling: Microscopic modelling adapts CMOS techniques to the one/few-charge regime and qubit-relevant quantities rather than electrical currents.The models target charge density, wavefunctions, and qubit-device figures of merit.
  • Modelling: Finite-volume Poisson solvers provide electrostatic potentials from which k · p, tight-binding, or related methods calculate qubit figures of merit.Examples include electron filling, valley splitting, tunnel coupling, g-factor, and exchange coupling strength.
  • Modelling: Existing modelling tools have mainly explained valley splitting, electron-spin EDSR, and Rabi frequency after experiments.Their use has so far been primarily a posteriori rather than as a complete predictive design workflow.
  • Modelling: Growing statistical datasets could enable a QCAD suite spanning microscopic device descriptions through qubit-array simulation.This is presented as a prospective development enabled by increasing amounts of statistical data.

CHALLENGES FOR CRYO-CMOS DESIGN

Cryo-CMOS design requires temperature-aware device models because cryogenic operation changes transistor behavior, excludes some technologies, and imposes evolving modelling requirements.

  • CHALLENGES FOR CRYO-CMOS DESIGN: Cryogenic circuit design must account for temperature-dependent device parameters, power dissipation restrictions, and communication latency.These challenges affect both the quantum-classical interface and the classical layer.
  • CHALLENGES FOR CRYO-CMOS DESIGN: Preliminary low-temperature technology studies established initial transistor rules of thumb and exploratory compact models.These models support an initial phase of cryogenic integrated-circuit design.
  • CHALLENGES FOR CRYO-CMOS DESIGN: Modern bulk-silicon and fully depleted silicon-on-insulator CMOS generally operate at deep cryogenic temperatures, but threshold voltage increases by typically 0.1-0.2 V for n-type devices.Reduced phonon scattering increases mobility, while MOSFET subthreshold swing decreases to about 10 mV/dec before saturation.
  • CHALLENGES FOR CRYO-CMOS DESIGN: Mass-scale transistor and circuit characterization is still needed to establish cryogenic compact models and ECAD tools.The paper presents this as the next phase beyond heuristic knowledge and advanced preliminary models.

Power consumption and communication latency

Scaling cryogenic control electronics requires reducing feedback latency while staying within severe cooling-power limits, motivating elevated-temperature operation and low-power circuit technologies.

  • Power consumption and communication latency: 30 ns minimum latency from room-temperature electronics approximately 1.5 m away can approach two-qubit exchange-gate times, challenging active QEC feedback.Cryo-electronics placed near the qubits can reduce this latency impact.
  • Power consumption and communication latency: Cooling power falls from a few watts at 4 K to typically below 1 mW at 100 mK, making radio- or microwave-frequency transistor switching power a central constraint.This limits how much electronics can be co-integrated at millikelvin temperatures.
  • Power consumption and communication latency: Silicon spin qubits may operate within error-correction thresholds at 1.1-1.45 K, increasing the available cooling-power budget between the quantum and cryo-electronic layers.The reported higher-temperature operation currently comes at reduced fidelity, potentially increasing physical-qubit and electronics requirements.
  • Power consumption and communication latency: Because dynamic power scales with voltage squared, cryogenic IC design may target supply voltages of only a few hundred millivolts.The strategy also relies on the substantial reduction in subthreshold swing at deep cryogenic temperatures.
  • Power consumption and communication latency: Superconducting interconnects could reduce resistive dynamic losses, improve signal transmission, and limit phononic heat flow toward the qubits.Gate and cable capacitances still require charging power unless operated adiabatically.

CHALLENGES AT THE QUANTUM-CLASSICAL INTERFACE

The quantum-classical interface must deliver many high-frequency control and readout signals without scaling room-temperature wiring and heat loads proportionally with qubit count.

  • CHALLENGES AT THE QUANTUM-CLASSICAL INTERFACE: Spin-qubit control and readout require high-frequency analog signals, with each logic gate individually controlled by external inputs.These requirements define key interface challenges for scalable systems.
  • CHALLENGES AT THE QUANTUM-CLASSICAL INTERFACE: Directly wiring every qubit and exchange-gate electrode to room-temperature electronics does not scale because of macroscopic wiring and heat-load management.Reducing room-temperature inputs per qubit is therefore a key scaling challenge.
  • CHALLENGES AT THE QUANTUM-CLASSICAL INTERFACE: Shared-control architectures use common gates for quantum dots and tunnel barriers, analogous to CCD sensor structures.They require strong quantum-layer uniformity, including consistent single-electron loading with one common voltage.
  • CHALLENGES AT THE QUANTUM-CLASSICAL INTERFACE: Row-column addressing could independently control N qubits with O(N) room-temperature resources, at the cost of sacrificing simultaneous operation.This approach is proposed alongside continued efforts to reduce device variability.
  • CHALLENGES AT THE QUANTUM-CLASSICAL INTERFACE: Floating capacitors can provide memory by retaining gate voltages longer than qubit coherence times.Thicker gate oxides and low operating voltages can extend retention and reduce unwanted voltage drift.

Control and readout electronics

Control and readout electronics must generate, multiplex, amplify, digitize, and decode signals at cryogenic temperatures without becoming a bottleneck for qubit performance.

  • Readout: Cryogenic readout uses multiplexers, amplifiers, demodulators, and ADCs to process signals that are typically only a few tens of microvolts.The generic architecture resembles a radio transceiver adapted for cryogenic operation.
  • Readout: Quantum-limited amplifiers such as JPAs can reduce readout time by an order of magnitude relative to conventional cryogenic amplifiers.Phase-sensitive operation may also use quadrature squeezing to exceed the quantum limit.
  • Control: Cryo-CMOS control circuits use DACs, IQ modulators, and rf amplifiers to generate programmable 1–20 GHz signals for flexible spin control.Multiplexing is a potential route to controlling multiple qubits.
  • Performance modelling: SPINE links qubit time evolution with time-varying classical signals to determine electronics specifications that avoid bottlenecking QPU performance.The framework connects control and readout electronics to qubit fidelity.
  • Digital processing: Digital logic must operate faster than qubits to identify errors and generate high-fidelity feedback for quantum error correction.Even 10 or 100 ns silicon-qubit operation timescales could be managed with current classical processors.
  • Digital processing: Cryogenic FPGAs are being combined with quantum-error-correction implementations to improve feedback speed, reduce latency, and support machine-learning decoding.They may also support hybrid algorithms such as VQE and QAOA.
  • Memory: Reduced leakage can make cryogenic DRAM effectively static, freeing area or increasing controller memory for more sophisticated waveforms during simultaneous qubit control.Additional memory could support scalability as the number of controlled qubits increases.

CHALLENGES AT THE ARCHITECTURE LEVEL

Architecture-level scaling must reconcile dense silicon qubit arrays with wiring, variability, crosstalk, readout, and the placement of classical electronics across 2D and 3D designs.

  • Architecture-level challenges: Silicon’s small qubit footprint creates an I/O problem and complicates classical-electronics placement without disrupting the 2D array required for quantum error correction.Monolithic integration is attractive except for power consumption, but in-plane electronics can break the QEC array.
  • 3D Integration: Proposed 3D integration uses floating memory units and embedded control transistors to address local variability and I/O, but assumes short gate pitch and un demonstrated 3D integration.The design also depends on managing gigahertz-regime crosstalk.
  • 3D Integration: A monolithic 3D design with on-chip readout can implement the surface code in a 2 × 2 QD sublattice, whereas projective spin-blockade readout requires 2 × 3.The 2 × 2 design gives each qubit a dedicated rf sensor for spin readout.
  • 2D Integration: Planar 2D monolithic designs use row, column, and diagonal gate layers while moving readout and control electronics to the periphery through dispersive readout and multiplexed microwaves.These proposals are described as compatible with current technology.
  • 2D Modular: Sparse modular 2D geometries relax fabrication and variability constraints while allowing local tuning, long-distance coupling, reduced crosstalk, and more space for classical electronics.Separated registers are proposed to alleviate wiring problems.
  • 2D Modular: Cavity-mediated spin–photon interactions remain below fault-tolerance thresholds because coherent coupling rates do not yet sufficiently exceed spin and photon decay rates.Industry-fabricated double QDs and high-impedance resonators may improve these coupling rates.

OUTLOOK

The review presents CMOS-based silicon quantum computing as a promising system-level scaling route, while emphasizing that large fault-tolerant processors require advances beyond current VLSI capabilities and broader foundry access.

  • OUTLOOK: CMOS fabrication could support compact integration of the quantum layer, quantum-classical interface, and classical processing unit, with potentially low-cost manufacturing.Small silicon processors may already be readily manufacturable, but larger fault-tolerant systems need further development beyond current VLSI capabilities.
  • OUTLOOK: The authors identify key engineering challenges and provide directions for addressing them across the quantum and classical parts of a quantum computing system.
  • OUTLOOK: Transitioning to standard silicon foundries could enable a global Multi-Project Wafer prototyping service for silicon quantum circuits.The proposed service could increase standardization, fabrication throughput, accessibility, and development speed.

FIGURE TITLES/CAPTIONS

The figures depict silicon quantum-dot devices, the layered quantum computing system, two-dimensional qubit and sensor arrays, and the principal scaling challenges.

  • Silicon QD devices: Figure 1 compares SEM and cross-sectional views of Si/SiGe, MOS, CMOS p-type, and hole-spin double quantum-dot devices.The devices include gates, readout transistors or sensors, micromagnets, and microwave antennas for spin control.
  • A quantum computing system: Figure 2 represents the quantum computing system’s layers and intermodule connections, including multiplexing, IQ signal processing, ADCs, DACs, and digital feedback.
  • Two-dimensional arrays: Figure 3 presents two-dimensional qubit arrays for surface-code interactions, alternative 2 × 2 and 2 × 3 layouts, image-sensor analogies, and quantum-dot cell electronics.
  • Challenges: Figure 4 organizes scaling challenges into the quantum layer, quantum-classical interface, classical layer, and architecture.It also depicts modular and 3D architectures, an FPGA, and device-modelling simulation.
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