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Exploiting dynamic quantum circuits in a quantum algorithm with superconducting qubits
Antonio D. Corcoles, Maika Takita, Ken Inoue, Scott Lekuch, Zlatko K. Minev, Jerry M. Chow, Jay M. Gambetta
TL;DR
The work implements quantum phase estimation with a main circuit that shifts the control phase using previous measurement results. It develops output estimators from circuit statistics and reports low estimation error, while measurement characterization reveals scope limitations for one dephasing protocol.
Problem
Quantum phase estimation requires choosing an approximation to the phase from sampled output distributions when multiple measurements per bit are available.
Method
The implementation shifts the control-signal phase based on previous measurement results and uses repeated measurement-reset cycles for the pointer qubit.
Results
2.905 × 10−4 error was obtained for the phase estimate 0.484375 against the phase 0.4840845.
Takeaways & Limitations
Selecting consecutive bitstrings among the two most likely outputs consistently yields the lowest estimation error across the tested resource counts.
Takeaways & Limitations
The cavity readout sweep protocol is most efficient only when the dispersive shift is much smaller than the cavity decay rate.
Abstract
from arXiv · showhide
The execution of quantum circuits on real systems has largely been limited to those which are simply time-ordered sequences of unitary operations followed by a projective measurement. As hardware platforms for quantum computing continue to mature in size and capability, it is imperative to enable quantum circuits beyond their conventional construction. Here we break into the realm of dynamic quantum circuits on a superconducting-based quantum system. Dynamic quantum circuits involve not only the evolution of the quantum state throughout the computation, but also periodic measurements of a subset of qubits mid-circuit and concurrent processing of the resulting classical information within timescales shorter than the execution times of the circuits. Using noisy quantum hardware, we explore one of the most fundamental quantum algorithms, quantum phase estimation, in its adaptive version, which exploits dynamic circuits, and compare the results to a non-adaptive implementation of the same algorithm. We demonstrate that the version of real-time quantum computing with dynamic circuits can offer a substantial and tangible advantage when noise and latency are sufficiently low in the system, opening the door to a new realm of available algorithms on real quantum systems.
Device characterization
The experiment uses two superconducting transmon qubits in a 14-qubit processor, characterized through coherence, gate-error, and readout-related measurements.
- Device characterization: The device uses two superconducting transmon qubits, Q0 and Q1, coupled and read out through coplanar waveguide resonators.Q0 serves as the system qubit and Q1 as the pointer qubit.
- Device characterization: Qubit relaxation and echo-coherence times vary substantially, with median T1 values of 68.20 µs for Q0 and 49.23 µs for Q1.The reported T echo values are 59.93 µs and 41.92 µs, respectively.
- Device characterization: Single-qubit operations use 30 ns DRAG pulses, while phase rotations are implemented as software frame changes.Two-qubit operations use echoed cross-resonance with Q1 controlling Q0.
- Device characterization: The measured two-qubit error per Clifford is 2.32 × 10−2, corresponding to an estimated CNOT error of 1.55 × 10−2 under the stated gate-weight assumption.Single-qubit error-per-gate values were 7.59 × 10−4 for Q0 and 5.67 × 10−4 for Q1.
Measurement characterization
The pointer qubit is measured through a reflected coplanar-waveguide resonator, with a TWPA providing early-stage amplification before subsequent amplification stages.
- Measurement characterization: The pointer-qubit readout signal is measured in reflection from its resonator and amplified first by a Traveling Wave Parametric Amplifier.A HEMT amplifier and room-temperature amplification follow the TWPA.
Dressed dephasing experiments for measurement characterization
Dressed dephasing measurements characterize how the readout drive affects the qubit and calibrate the dispersive shift, cavity decay, and photon population relevant to the algorithm.
- Dressed dephasing experiments for measurement characterization: The cavity-response method is most efficient when χ ≪κ because the dephasing parameters depend nonlinearly on χ and κ.This is an author-stated scope limitation of the amplitude-sweep use case.
- Dressed dephasing experiments for measurement characterization: The protocol sweeps cavity-probe frequency and amplitude while measuring both qubit quadratures to extract measurement-induced rotation and dephasing.It uses a Ramsey sequence modified by an additional cavity probe tone and remains valid down to single-photon levels.
- Dressed dephasing experiments for measurement characterization: The formalism eliminates the resonator degree of freedom through a polaron transformation and yields equations for measurement-induced AC Stark shift and dephasing.The qubit dynamics are then described using Bloch equations with time-dependent rotation and dephasing terms.
- Dressed dephasing experiments for measurement characterization: The extracted resonator response α_i describes the finite-duration drive when the qubit occupies state |i⟩.Its dynamics depend on the input drive, resonator decay, drive detuning, and dispersive coupling.
- Dressed dephasing experiments for measurement characterization: χ/π = 5.8 MHz and κ/2π = 5.7 MHz are obtained from the dressed-dephasing fits.The same analysis extrapolates the algorithm’s measurement drive to an average cavity population of n̄ ∼11.
Measuring readout photon number via photon time operation
Photon time operation uses an echo experiment after the readout pulse to fit photon-dependent phase and contrast dynamics, yielding the measurement-tone photon population.
- Measuring readout photon number via photon time operation: The photon-number estimate assumes κtR ≫1, short echo gates relative to system dynamics, and timing precision sufficient to resolve photon decay.The experiment is not fully in the short-gate regime, motivating the rescaling correction.
- Measuring readout photon number via photon time operation: The model represents resonator photon decay as n0e−κt, combining a photon-dependent frequency shift with exponential contrast loss.The echo removes external low-frequency-noise contributions.
- Measuring readout photon number via photon time operation: The fit gives n0 ∼3.8 before correction and n0 ∼11 after applying the eκtg ∼2.93 finite-gate correction.The corrected value is about half of ncrit.
Overview of the control electronics
The control system integrates FPGA-based waveform generation, sequencing, readout acquisition, and classical control between the host computer and superconducting quantum hardware.
- Overview of the control electronics: The control electronics combine DAC waveform generation, ADC measurement acquisition, FPGA sequencing, and a cryogenic-system interface.The FPGA defines pulse amplitudes, frequencies, shapes, and durations while orchestrating their playback.
- Overview of the control electronics: The system evolved from a prototype into integrated custom cards supporting RF waveform generation and readout capture under host-PC control.The cards communicate with the host through PCIe Gen 2/Gen 3 x4.
- Overview of the control electronics: The electronics provide two DAC channels up to 2.5 GS/s and two ADC channels up to 500 MS/s, with optional single-channel 1 GS/s ADC operation.Both DAC and ADC channels support up to 14-bit resolution.
- Overview of the control electronics: A Xilinx MPSoC UltraScale+ FPGA drives the ADC and DAC channels using programmable logic for fast qubit-state determination and conditional waveform playback.The design is tailored to conditional control and readout sequences.
- Overview of the control electronics: Clock generators provide flexible, low-jitter ADC, DAC, and local-oscillator clocks, while FPGA memory and Ethernet support embedded-controller extensions.The embedded ARM microcontroller is currently unused.
1. ADC Controller Logic
The ADC controller digitizes readout signals, determines qubit states with FPGA processing, transfers data efficiently, and exposes low-latency results for feedback and reset.
- 1. ADC Controller Logic: The ADC captures down-converted intermediate-frequency signals at 1G samples per second and transfers them to FPGA logic through LVDS channels.The two physical channels use 500 MS/s sampling with a 1 ns phase offset.
- 1. ADC Controller Logic: FPGA DMA transfers sustain up to 1.6 GBytes/sec over PCIe, sufficient to move complete ADC captures for typical 1 ms-trigger-interval experiments.The sustained rate depends on transfer block size.
- 1. ADC Controller Logic: Trigger aggregation stores up to 256 triggers in a ring buffer so bursts of short, fast-repeating readouts can be transferred in batches.Batching reduces the impact of per-transfer PCIe transaction overhead, which can be on the order of microseconds.
- 1. ADC Controller Logic: Dual-port FPGA memory allows host DMA transfers to proceed asynchronously and in parallel with qubit readout without data loss when aggregate readout rates remain within transfer capacity.The relevant capacity is readouts per second multiplied by readout sample length.
- 1. ADC Controller Logic: A calibrated FPGA matched filter integrates incoming readout data and compares it with a threshold to determine qubit states with low latency and high fidelity.DSP blocks impose up to four logic-clock cycles of integration and thresholding overhead.
- 1. ADC Controller Logic: The readout result drives active-reset switches and DAC conditional branches, with nominal ADC-trigger-to-result latency of 40 ns in the QPE configuration.This latency excludes the qubit-dependent readout sample duration.
2. DAC Controller Logic
The DAC controller uses FPGA sequencing and conditional branching to generate reusable waveforms and adapt QPE control pulses to measurement results in real time.
- 2. DAC Controller Logic: The sequence processor supports waveform reuse, loops, absolute and conditional branches, and marker signals controlling external analog gates.Conditional branches can use readout-result signals generated by the FPGA ADC controller.
- 2. DAC Controller Logic: A simpler DAC operating mode supports one waveform and marker block per trigger through software-managed registers.The QPE experiments instead used sequence-processor mode.
- 2. DAC Controller Logic: The sequence processor executes conditional branches synchronously with DAC data transfer, enabling single-clock-cycle branching from qubit readout results.The data-transfer clock is configured to one-eighth of the DAC sampling clock.
- 2. DAC Controller Logic: A 128-bit FPGA block RAM stores up to 512K waveform samples, fetching eight samples in parallel for transmission to two DAC chips.A Xilinx FPGA SERDES sends samples over an LVDS parallel link.
- 2. DAC Controller Logic: The instruction format and prototype programming extension provide labels, conditional branches, and unconditional gotos for adaptive quantum programs.A conditional-reset example branches according to a measured qubit state and later reconverges.
- 2. DAC Controller Logic: The QPE extension shifts the control phase according to previous measurement results, implementing the algorithm’s adaptive core in the DAC controller.Conditional reset was separately implemented with an RF switch to reduce instruction-memory and software complexity.
Reset fidelity and readout QND-ness
Reset fidelity was assessed using excited-state probability, and repeated measurement-reset cycles produced low, stable error consistent with reasonably QND readout.
- Reset fidelity and readout QND-ness: The reset-fidelity study prepares alternating ground and excited states, measures the qubit, and conditionally resets it at rates faster than the qubit lifetime.The experiment compares apparatus-induced state-preparation error with environmental thermalization.
- Reset fidelity and readout QND-ness: Reset error is defined as the probability P(1) of obtaining the excited state after reset.The ideal reset distribution is Q = (1, 0), while the measured distribution is P = (P(0), P(1)).
- Reset fidelity and readout QND-ness: 1.65% reset error occurs after one reset and 1% after two resets, while further measurement-reset iterations do not significantly increase the error.The authors therefore characterize the measurement as reasonably Quantum Non-Demolition (QND).
- Reset fidelity and readout QND-ness: The main QPE experiments use two measurement-reset cycles for the pointer qubit.This choice follows the measured reset-error behavior.
IPE Algorithm output from circuit statistics
The IPE output is estimated from circuit statistics by combining the two most likely bitstrings, with enforcing consecutiveness giving the most accurate result across resource counts.
- The algorithm estimates the phase as a weighted average of the two most likely consecutive output bitstrings.The consecutive-bitstring condition reduces sampling error compared with averaging the two most likely bitstrings without that constraint.
- The consecutive-bitstring weighted average consistently yields the lowest error for any number of available resources.This strategy is therefore used for the main-body results.
- The most-likely-bitstring estimator eventually flattens as more circuit outputs are sampled, while the ensemble average has the highest error.The ensemble average retains the full sampling error, whereas the most-likely-bitstring approach stops improving effectively.
- Kitaev estimation performs poorly with very few resources but approaches the iterative method when measurements are substantially increased.
Kitaev Estimator
The Kitaev estimator reconstructs a phase approximation from shifted-bit estimates, refining bits iteratively; an example reaches seven-bit accuracy with error below 1/2^8.
- Kitaev Estimator: Kitaev’s approach estimates eigenvalues with an exponential advantage over classical methods, then requires a classical estimator to reconstruct the phase bit by bit.
- Kitaev Estimator: The circuits estimate shifted bits α_k derived from the m-bit phase approximation, which is represented in binary as 0.ϕ_1ϕ_2...ϕ_m.
- Kitaev Estimator: The estimator initializes the final bits from α_m and iteratively determines preceding bits by comparing shifted binary candidates with each α_j.
- Kitaev Estimator: For ϕ = 0.4840845, the estimator returns the 7-bit approximation 0.0111110 = 0.484375 with error 2.905 × 10^-4 < 1/2^8.