Machine Learning for Electronic Design Automation: A Survey

1 INTRODUCTION

• As IC scale grows exponentially, EDA faces scalability and reliability challenges and needs more effective, efficient algorithms for extremely large search spaces with low latency.Source: §1 · p. 1
• ML can accelerate EDA by reusing learned features and patterns, whereas traditional methods often restart from scratch and consume substantial time and resources on NP-complete problems.Source: §1 · p. 1
• ML-based methods have been proposed across almost all chip-design stages and have demonstrated impressive improvements over traditional methods.The stages include design-space reduction and exploration, logic synthesis, placement, routing, testing, verification, and manufacturing.Source: §1 · p. 2
• The survey groups ML-for-EDA work into four approaches: traditional-method decision making, performance prediction, black-box optimization, and automated design.These approaches represent decreasing manual effort and expert experience, or increasing automation.Source: §1 · p. 2
• The survey reviews recent ML methods across EDA stages, with most included studies published in the preceding five years.Its coverage spans synthesis and physical design, mask synthesis, analog design, testing and verification, and related topics; it also discusses studies from an ML perspective and future trends.Source: §1 · p. 2

2.1 Electronic Design Automation

• HLS converts C/C++/SystemC specifications to HDL, but its long synthesis time makes efficient design-space exploration crucial; logic synthesis uses heuristics, including ML methods.Logic synthesis maps behavioral descriptions to gates from a cell library and optimizes for different goals, but is generally not solved optimally.Source: §2.1 · pp. 2–3
• Placement assigns netlist components to layout locations, routing connects them under timing, wirelength, and design-rule constraints, and their coupling motivates routing-aware ML methods.Placement quality affects area utilization, timing, and routability; ML methods also address lithography simulation and mask synthesis challenges [20].Source: §2.1 · p. 3
• Verification occurs throughout the EDA flow, where ML studies optimize test-set generation; manufacturing testing targets coverage and efficiency through test-set optimization and complexity reduction.Larger test sets can improve coverage but consume more resources.Source: §2.1 · pp. 3–4

2.2 Machine Learning

• EDA studies use supervised and unsupervised learning on static datasets, active learning to select samples and refine models, and reinforcement learning to learn through actions and rewards.These paradigms all have applications to EDA problems.Source: §2.2 · p. 4
• Conventional EDA models include regression, random forests, neural networks, support vector machines, and K-nearest neighbors, with ensemble or boosting methods such as XGBoost expanding model expressiveness [66, 178, 91, 55, 12, 39, 23].Support vector machines are especially suited to tasks with small training sets.Source: §2.2 · p. 4
• Recent EDA studies use CNNs for grid data, RNNs for sequences, and GNNs for graphs, alongside GANs and deep reinforcement learning [37] [148].Deep reinforcement learning combines deep learning with reinforcement learning, learning strategies from rewards associated with prior actions.Source: §2.2 · p. 4

3.1 Machine Learning for Result Estimation

• Because complex physical synthesis makes early estimates difficult, ML learns from real benchmarks to predict timing, resource use, operation delay, and cross-platform performance.This addresses the trade-off between estimation accuracy after synthesis and efficiency at the HLS stage.Source: §3.1 · p. 5

3.1.1 Estimation of Timing, Resource Usage, and Operation Delay.

• HLS estimation trains regression models on HLS-report features and implementation-report targets, using feature selection to reduce collinearity and dimensionality.Studies collect reports across designs, clock periods, and FPGA devices; a customized GNN can also infer hardened-block mappings for operation-delay prediction.Source: §3.1.1 · pp. 5–6
• A customized GNN captures dataflow-operation associations and hardened-block mappings, reducing Vivado HLS operation-delay prediction RMSE by 72%.Conventional estimators add pre-characterized operation delays, which can miss post-implementation optimizations such as mapping to hardened blocks.Source: §3.1.1 · p. 6

3.1.2 Cross-Platform Performance Prediction.

• XPPE achieved 5.1% relative mean square error and speedup more than 0.98× [109]; HLSPredict achieved 9.08% APE and 43.78× runtime speedup.XPPE uses resource utilization on one FPGA to estimate performance on other platforms; HLSPredict uses workload execution on a host CPU and requires the target platform to match its training platform.Source: §3.1.2 · p. 7

3.2 Machine Learning for Design Space Exploration in HLS

• HLS DSE seeks Pareto-optimal designs; ML models trained on explored designs guide searches, while other learning-based methods improve classical algorithms.Classical simulated annealing and genetic algorithms do not learn from previously explored designs.Source: §3.2 · pp. 7–8

3.2.1 Active Learning.

• Active-learning DSE for HLS uses predictive ML models to surrogate synthesis; Liu and Schäfer report 6.5× faster than exhaustive search and 3.0× faster than restricted search, with higher-quality results.TED seeks samples that describe the design space accurately. PAL evaluates uncertain samples, while ATNE adapts its Pareto-identification threshold to estimated RF-regressor inaccuracy.Source: §3.2.1 · pp. 8–9

3.2.2 Machine Learning for Improving Other Optimization Algorithms.

• Models predicting ADRS and runtime from hyperparameters improved ADRS by more than 1.92× over default settings within similar runtime [149].Combining simulated annealing, genetic algorithms, and ant colony optimization further improved search efficiency.Source: §3.2.2 · p. 10

3.3 Summary of Machine Learning for HLS

• The review recommends public benchmarks covering many DSE implementations and ML models customized with domain knowledge, as exemplified by Ustun et al..DSE evaluation often uses few applications because synthesizing large design spaces is costly; customized GNNs have improved delay-prediction accuracy.Source: §3.3 · p. 10

4.1 Logic Synthesis

• Logic-synthesis studies use DNNs and CNNs to schedule or rank existing optimizer flows, while GCN and A2C policies search DAG transformations.LSOracle selects between AIG and MIG optimizers on circuit partitions, while Yu et al. classify synthesis flows by QoR levels.Source: §4.1 · p. 11

4.2.1 Traditional Placers Enhancement.

• PADE separates data-path from random-logic placement, using SVM and NN pattern extraction and SAPT optimization for the data path.It extracts and evaluates data-path patterns from netlist structure, initial placement hints, and relative area, then maps them to a bit-stack structure.Source: §4.2.1 · p. 11

4.2.2 Routing Information Prediction.

• ML models predict routing hotspots and congestion, early-stage circuit metrics and sign-off timing, and also support clock-tree synthesis and pre-route crosstalk estimation.Methods include CNN/FCN image models for DRC or congestion, regression and other models for routing or routability estimates, and predictors of sign-off timing.Source: §4.2.2 · pp. 11–12

4.2.3 Placement Decision Making.

• Placement decision methods learn floorplanning heuristics with deep Q-learning and train an RL policy to place macros using graph, metadata, wirelength, and congestion information.The latter applies force-directed standard-cell placement after macro placement and optimizes a reward based on weighted wirelength and congestion.Source: §4.2.3 · pp. 12–13

4.3 Power Deliver Network Synthesis and IR Drop Predictions; 4.5 Other Predictions

• ML supports PDN design through static and dynamic IR-drop estimation, PDN template selection, and bump-inductance prediction, alongside memory-timing-failure and aging-effect prediction.Methods include XGBoost for incremental static IR-drop prediction, a maximum CNN for dynamic IR-drop, and conditional GANs for electromigration-induced IR-drop.Source: §4.3 · p. 13, §4.5 · p. 15

4.4 Design Challenges for 3D Integration

• For 3D integration, die-to-die variation complicates path-delay modeling, and ML-based design-space exploration has been used to aid optimization.Conventional OCV, AOCV, and POCV methods may not accurately capture cross-die path delay; current bin-based tier partitioning can degrade design quality by ignoring hierarchy and technology.Source: §4.4 · p. 13
• TP-GNN improves 3D tier partitioning by 7.7% in wirelength, 27.4% in effective frequency, and 20.3% in performance.It uses hierarchy-aware edge contraction and timing-informed node features before GNN training and weighted k-means tier assignment; the work addresses quality degradation from bin-based partitioning that ignores design hierarchy and technology.Source: §4.4 · pp. 13–15

4.6 Summary of Machine Learning for Logic Synthesis and Physical Design

• The review identifies existing-tool primitives as the current basis for synthesis-flow optimization and highlights prediction of simulation-dependent information as a physical-design focus; it calls for broader algorithms and ML techniques [including NAS and unsupervised learning].Future directions include more logic-synthesis algorithms, metrics, and emerging-technology applications, as well as techniques to improve routing and placement results.Source: §4.6 · p. 15

5.1 Lithography Hotspot Detection

• Hotspot detection ranges from grid-level SVM and routing prediction and spatial-feature and inter-layer methods to end-to-end large-layout localization.An attention-based CNN with an inception backbone is also developed for feature embeddings.Source: §5.1 · pp. 15–16

5.2 Machine Learning for Optical Proximity Correction

• OPC studies include deterministic selection among OPC solutions and GAN mask generation with ILT-guided pre-training to address convergence and improve speed and mask accuracy.ILT-guided pre-training replaces the discriminator with an ILT convolution model while training the generator, then removes the costly ILT model for whole-GAN training.Source: §5.2 · pp. 16–17
• 70× speedup and 0.43× mask complexity versus traditional ILT are reported for neural-ILT, while DAMO [20] outperforms academic and industrial state-of-the-art OPC on ISPD 2019 full-chip layouts.Neural-ILT replaces costly ILT with a neural network and penalizes complex output masks; DAMO uses a shared deep conditional GAN and coarse-to-fine window splitting for full-chip layouts.Source: §5.2 · p. 17

5.3 Machine Learning for SRAF Insertion

• For SRAF insertion, CCAS and dictionary learning produce logistic-regression probability maps that feed integer-linear programming under SRAF design rules.The probability map indicates whether to insert an SRAF at each grid.Source: §5.3 · pp. 17–18

5.4 Machine Learning for Lithography Simulation

• LithoGAN combines conditional-GAN shape modeling with CNN center prediction, achieving high-accuracy resist patterns and reducing simulation time by several orders of magnitude.The ML-based simulator in [20] also outputs via contours to assist via-oriented OPC.Source: §5.4 · p. 18

6 ANALOG DESIGN

• Analog design remains difficult to automate: ADCs and RF transceivers occupy little SoC area yet consume most design effort, amid larger design spaces and application-specific, variation-sensitive specifications.The passage also identifies validation and verification against noise and process-voltage-temperature variations as additional burdens.Source: §6 · pp. 18–19

6.1 The Design Flow of Analog Circuits

• Analog design proceeds from system-level topology selection and device sizing to layout synthesis, parasitic extraction, and post-layout simulation, with redesign iterations when specifications are unmet.The flow combines top-down optimization with bottom-up layout synthesis and verification.Source: §6.1 · p. 19, Figure 11 · p. 20
• Automation tools have improved but cannot yet replace manual work; ML efforts span circuit-level topology selection, device-level sizing, and physical-level analog layout.The survey frames these efforts across the analog design hierarchy.Source: §6.1 · pp. 19–20

6.2 Machine Learning for Circuit Topology Design Automation

• Topology design is a time-consuming, high-freedom first step, and an unsuitable choice forces redesign; ML studies address candidate selection, building-block extraction, and RNN/hypernetwork generation.As analog-circuit scale and demand increase, CAD tools are urgently needed, although topology automation remains less explored.Source: §6.2 · p. 20

6.2.1 Topology Selection.

• For reusable functional units such as amplifiers, FASY maps specifications to fixed topology alternatives with fuzzy logic and backpropagation, while later work classifies specifications to topology indexes using CNNs.Data collection and training are time-consuming, so selection is efficient mainly when repetitive designs allow model reuse.Source: §6.2.1 · p. 20

6.2.2 Topological Feature Extraction.

• Feature-extraction methods identify circuit structures and connections, detect symmetry through graph similarity, including passive devices, and hierarchically generate symmetry constraints with GNNs.The work also targets hierarchical structures, generic templates, and overlaps among structures.Source: §6.2.2 · pp. 20–21

6.2.3 Topology Generation.

• For two-port circuits, an RNN and hypernetwork topology generator outperformed traditional methods when inductor circuit length n≥4.This was a first attempt to generate circuit topology for given specifications; the study was limited to two-port circuits.Source: §6.2.3 · p. 21

6.3.1 Reinforcement Learning Based Device Sizing.

• The RL agent receives each transistor’s local status and the circuit’s global operating-point status, accounting for their interdependence when updating device sizes.The framework uses simulator observations, a value-network reward, and agent actions to update sizes.Source: §6.3.1 · p. 21
• 9.4× acceleration over previous approaches is reported for reinforcement learning trained with schematic simulations and validated with post-layout simulations, using additional deployment iterations.The transfer-learning method addresses the increased training time of post-layout simulation.Source: §6.3.1 · p. 21
• A GCN-based RL agent aggregates circuit-topology features and shares learned weights to transfer sizing across functionally similar topologies and technology nodes.The trainable weights are updated by DDPG; the cited work builds on [148] and enhances transferability.Source: §6.3.1 · pp. 21–22

6.3.2 Artificial Neural Network Based Device Sizing.

• A 3-layer MLP with data augmentation improves robustness and achieves the best performance by jointly regressing device sizes and classifying circuit topology.Augmentation generates copies with worse specifications; regression handles sizing, while classification handles topology selection.Source: §6.3.2 · p. 22

6.3.3 Machine Learning Based Prediction Methods.

• Hakhamaneshi et al. and Pan et al. use DNN and SVM simulator predictors; the DNN learns pairwise specification superiority, expanding training data by N^2.Pairwise comparison is presented as easier than fitting each specification’s absolute value under limited training data and a non-convex, potentially ill-posed prediction problem.Source: §6.3.3 · pp. 22–23
• On two-stage OPA, ML methods require more training simulations than genetic methods but need few inference iterations at deployment; genetic algorithms combined with ML predictors can reduce simulations.The passage identifies complicated circuit design as still challenging.Source: §6.3.3 · p. 23, Table 5 · p. 23

Motivation

• Because parasitics complicate performance estimation, ML-based automation aims to reduce long design times and potential inaccuracies of experience-based estimates.The section notes that parasitics significantly affect circuit performance and that traditional designer estimates can be time-consuming and inaccurate.Source: §6.4 · p. 23

Layout generation and modeling

• ML methods support analog layout through learned layout generation, circuit-hierarchy partitioning, and estimation of electromagnetic properties.Xu et al. use a GAN to mimic designers’ manual layouts, producing op-amp wells with comparable post-layout performance; Kunal et al. achieve 100% accuracy on 275 test cases after postprocessing a GCN’s hierarchy output; Zhang et al. use a GNN to estimate EM properties and design circuits with target properties.Source: §6.4 · p. 23

Layout automation

• Other approaches automate routing, reuse legacy designs, or explore layouts through simulation feedback.Zhu et al. [177] propose VAE-based automated routing; Wu et al. match circuits to legacy designs and expand the database as new circuits are designed; Liu et al. use multi-objective Bayesian optimization in a closed-loop framework.Source: §6.4 · p. 24

Parasitic estimation

• Estimated parasitics reduce average pre-layout versus post-layout simulation error from 37% to 8%.Ren et al. use a GNN to predict net parasitic capacity and device parameters from schematics; Shook et al. use net features and a star topology for multi-port nets.Source: §6.4 · p. 24

Layout performance prediction

• A customized GNN reports higher performance-prediction accuracy than a CNN-based method.Li et al. compare SVM, random forest, and neural networks and combine prediction with simulated annealing for automated layout; Liu et al. use a 3D CNN with circuit images plus a coordinate channel, and Li et al. report higher accuracy than.Source: §6.4 · p. 24

• Machine-learning methods for analog sizing, topology design, and layout require fewer simulation rounds and achieve higher-quality designs than previous optimization-based algorithms.Source: §6.5 · p. 24
• Existing methods cannot yet replace human experts because models are trained on limited datasets and have limited flexibility.Source: §6.5 · p. 24
• Most studies train and test on typical circuits such as OTAs, motivating models that generalize across a variety of circuits.Source: §6.5 · p. 24
• System-level design remains unstudied, leaving machine learning's potential in analog design open for further exploration.Source: §6.5 · p. 25

7.1.1 Test Set Redundancy Reduction for Digital Design Verification.

• Digital coverage-directed test generation uses diverse ML methods to guide test selection, including genetic algorithms, SVMs, neural networks, probabilistic models, and rule learning.These methods search for higher-coverage generator configurations, identify novel or relevant tests, adapt Bayesian or Markov models from coverage feedback, or extract rules for generating tests.Source: §7.1.1 · p. 26

7.1.2 Test Set Redundancy Reduction for Analog/RF Design Testing.

• Analog/RF specification-test feature selection uses a multi-objective genetic algorithm and binary classifiers to reduce test types and repetitions while predicting pass/fail outcomes.A relatively small subset of non-RF tests predicted many power-set pass/fail tags, and adding some RF tests further improved prediction error.Source: §7.1.2 · p. 27
• 267 samples predicted 3241 data points with 0.3% average error and 14× test-process speedup in IC technology characterization.The method extracts features from a small number of tested samples, fits a regression model, and uses it to infer performance curves and other sample results.Source: §7.1.2 · p. 27

7.1.3 Test Set Redundancy Reduction for Semiconductor Technology Testing.

• Over 11× synthesis-time reduction was achieved by using random-forest models to select unique, testable semiconductor-technology test data.The models predict whether test data is unique and testable from features such as net count, fanout, and maximum logic depth.Source: §7.1.2 · p. 27, §7.1.3 · p. 28

7.2 Machine Learning for Test & Diagnosis Complexity Reduction

• Compared with commercial test tools, a GCN reduced observation points by 11% at similar fault coverage and reduced test-pattern count by 6%.The method maps a netlist to a graph and classifies modules as easy or difficult to observe; inserting observation points decouples tests of different modules.Source: §7.2 · p. 28

7.2.1 Test Complexity Reduction for Digital Design.

• BugMD classified and localized hardware bugs using machine-learning triage, achieving over 90% top-3 localization accuracy.It encodes instruction windows from DUT–golden-simulator mismatches and trains on synthetic bugs generated by randomly changing module functionality.Source: §7.2.1 · p. 28

7.2.2 Verification Diagnosis Complexity Reduction for Digital Design.

• Rising system complexity and robustness demands make analog/RF signal verification a bottleneck and render failure detection and design verification challenging.The section identifies analog/RF verification as a distinct complexity-reduction concern.Source: §7.2.2 · p. 28

7.2.3 Verification & Test Complexity Reduction for Analog/RF Design.

• For analog/RF verification and testing, a two-tier ML and specification-testing approach trades cost against accuracy, while HFMV uses active learning to detect rare failures.An ONN routes ambiguous results from low-cost testing to specification testing; HFMV uses max-variance and formally guided active learning when model confidence is insufficient.Source: §7.2.3 · p. 29

8.1 Power Prediction

• Lee and Gerstlauer report significant speedup within 10% error using high-level C/C++ behavior descriptions, while SIMMANI clusters toggle-encoded RTL signals for regression-based power prediction.The multi-level model granularity depends on available hardware information, ranging from black- to white-box modeling.Source: §8.1 · p. 30
• PRIMAL achieves 50× speedup over gate-level estimation with average error below 5%; GRANNITE achieves two orders-of-magnitude speedup over probabilistic switching-activity estimation with average relative error within 5.5%.PRIMAL predicts power tracks for workloads unlike its training set; GRANNITE improves transferability by using gate-level netlist information for graph generation, while still performing RTL-level—not gate-level—power prediction.Source: §8.1 · pp. 30–31

8.2 Machine Learning for SAT Solver

• SAT learning spans restart and branching heuristics, solver selection, evolved or reinforcement-learned heuristics, and neural methods for satisfiability classification or guiding solver search.Examples include LMPick, SATzilla [157], NeuroSAT, and simplified NeuroSAT [132].Source: §8.2 · p. 31
• Recent SAT approaches combine GNN formula encodings with reinforcement learning for heuristics or variable selection, while Circuit-SAT uses gated recurrent units to propagate DAG-structured data.RNNs can also embed formulas or DAGs; Circuit-SAT training follows an exploration-and-exploitation procedure.Source: §8.2 · p. 31

8.3 Acceleration with Deep Learning Engine

• DREAMPlace maps analytical placement onto neural-network training and reports over 40× speedup against CPU-based multithreaded tools using hand-optimized operators in PyTorch.The framework is presented as extensible by adding solver descriptions in high-level languages such as Python.Source: §8.3 · p. 32

8.4 Auto-tuning design flow

• Design-flow tuning studies use adaptive parameter settings, collaborative filtering, XGBoost with clustering and approximate sampling, and unsupervised-GNN features for deep reinforcement learning.These methods target synthesis settings or placement-tool parameters and seek to make tuning more efficient.Source: §8.4 · p. 32

9.1 The Functionality of ML

• ML in EDA is grouped into decision making in traditional methods, performance prediction, black-box optimization, and automated design.The discussion organizes these categories by ML functionality in the EDA workflow.Source: §9.1 · p. 32
• ML replaces brute-force or empirical configuration choices, including tool-chain selection for logic and mask synthesis and topology selection in analog design.EDA tool algorithms and hyper-parameters can strongly affect procedure efficiency and outcome quality; the cited examples include logic synthesis and mask synthesis.Source: §9.1 · p. 32

9.2 Data Preparation

• Dataset volume and quality are essential to model performance, and studies use EDA domain knowledge to engineer large, fair, clean datasets.Source: §9.2 · p. 34
• Feature extraction is problem-specific, using layout images [32, 89, 154], netlist geometry or graphs, algorithmic features, or manual selection.Manual selection lacks theoretical guarantees or practical guidance for other problems; labels often require time-consuming simulation or synthesis, motivating data-efficient model design, feature preprocessing, and semi-supervised dataset expansion.Source: §9.2 · pp. 34–35
• Common preprocessing includes feature normalization and edge-data removal, while some studies use PCA or LDA to adjust inputs.Source: §9.2 · p. 35

9.3 Domain Transfer

• Cross-platform models use new-domain specifications, while pretrained RL agents fine-tuned on new tasks can reduce training time and sometimes outperform training from scratch.Source: §9.3 · p. 35

• ML techniques have found applications in almost all stages of the EDA hierarchy, and the paper reviews the literature from both EDA and ML perspectives.Source: §10 · p. 35

Towards full-fledged ML-powered EDA tools

• Industrial needs remain difficult for ML-only approaches in tasks such as analog/RF testing and physical design, motivating combinations of ML with traditional methods and more useful models for real applications.Current methods may be limited to less flexible design spaces or simplified problems.Source: §10 · p. 35

Application of new ML techniques

• Point cloud, GCN, domain adaptation, and reinforcement learning have begun to find applications in EDA, with broader use anticipated.Source: §10 · p. 35

Trusted Machine Learning

• Broader ML adoption in EDA depends on trustworthy predictions and outputs that designers can assess as reliable, fair, and harmless.Source: §10 · p. 35