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Machine Learning for Electronic Design Automation: A Survey

Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang

arXiv:2102.03357v2eess.SPcs.AIcs.LGeess.SY

TL;DR

Increasing IC scale has expanded EDA search spaces and intensified demands for efficient, low-latency design methods. The paper surveys ML applications throughout the EDA hierarchy, organizing studies by design stage and ML perspective. Across representative applications, the reviewed methods report substantial speedups and improved transferability, while limitations remain in model scope and generalization.

  • Problem

    Growing IC complexity requires EDA methods that handle extremely large search spaces more effectively and efficiently with low latency.

  • Method

    The paper comprehensively reviews ML-based approaches across EDA stages and analyzes them from both EDA and ML perspectives.

  • Results

    The reviewed methods report improvements including 70× speedup with 0.43× mask complexity for neural-ILT and 9.4× acceleration for transfer-learning-based reinforcement learning.

  • Takeaways & Limitations

    ML has applications across almost all EDA stages and provides a data-driven perspective for accelerating EDA tasks.

  • Takeaways & Limitations

    Existing analog-design methods cannot yet replace human experts because limited datasets constrain model flexibility and generalization across circuit types.

Abstract

from arXiv · show

With the down-scaling of CMOS technology, the design complexity of very large-scale integrated (VLSI) is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 90s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interests in incorporating ML to solve EDA tasks. In this paper, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

1 INTRODUCTION

Increasing IC scale has made EDA design flows harder to scale, creating demand for efficient algorithms that handle huge search spaces with low latency. This survey reviews recent ML applications across the EDA flow and organizes them by design stages and ML perspectives.

  • Exponential IC growth challenges the scalability and reliability of circuit design flows, requiring more effective and efficient EDA software.
  • ML can reuse extracted features and patterns, reducing the repeated analysis and resource consumption typical of traditional methods.
  • Recent ML-for-EDA studies span design-space exploration, synthesis, placement, routing, testing, verification, and manufacturing.
  • The survey groups ML-for-EDA research into decision making, performance prediction, black-box optimization, and automated design.
  • The review covers recent ML studies across EDA stages, including high-level synthesis, physical design, mask synthesis, analog design, testing, verification, and related topics.

2 BACKGROUND

EDA spans a standardized but increasingly complex chip-design flow, from high-level specifications through synthesis, physical design, fabrication, and verification. ML supplies data-driven approaches across this hierarchy, while the survey reviews both EDA-stage applications and ML paradigms and models.

  • Electronic Design Automation: EDA converts high-level specifications into hardware descriptions, then performs synthesis, placement, routing, fabrication-related mask synthesis, and verification.
  • Electronic Design Automation: High-level synthesis requires design-space exploration because large-scale systems can make synthesis time-consuming.
  • Electronic Design Automation: Logic synthesis selects library gates to implement functions and uses heuristics because the optimization process is complicated and generally not optimal.
  • Electronic Design Automation: Placement affects area utilization, timing, and routability, while routing assigns wires connecting components based on placement.
  • Electronic Design Automation: Mask synthesis uses lithography simulation to reduce fabrication-failure probability, while ML methods also target testing and verification challenges.
  • Machine Learning: The survey reviews learning-based approaches for each EDA stage and discusses them from both EDA and ML perspectives.
  • Machine Learning: ML automatically extracts information from datasets or prior knowledge and includes supervised, unsupervised, active, and reinforcement learning paradigms.
  • Machine Learning: Common deep-learning models in EDA include CNNs for grid data, RNNs for sequences, GANs for generation, and GNNs for graph-organized data.

3 HIGH LEVEL SYNTHESIS

High-level synthesis studies use ML to predict implementation outcomes and guide design-space exploration, addressing costly synthesis and difficult configuration choices. The survey covers prediction, improved search algorithms, and active-learning workflows, alongside benchmark and model-design needs.

  • HLS converts high-level specifications into hardware descriptions, but tuning pragmas and configurations is difficult and exhaustive exploration is impractical because synthesis can take hours.
  • ML for HLS targets fast result estimation, refinement of conventional DSE algorithms, and active-learning formulations of DSE.
  • 3.1 Result Estimation: Prediction workflows train models on HLS-report features to estimate post-implementation timing and resource usage without time-consuming post-implementation.
  • 3.1.1 Estimation of Timing, Resource Usage, and Operation Delay: 72% lower RMSE for operation-delay prediction was achieved by a customized GNN that captures dataflow associations and infers hardened-block mapping choices.
  • 3.1.2 Cross-Platform Performance Prediction: XPPE uses HLS utilization, target-FPGA resources, and application characteristics to estimate FPGA-over-ARM speedup, reaching 5.1% relative mean square error and more than 0.98× speedup.
  • 3.2 Machine Learning for Design Space Exploration in HLS: DSE studies face limited application coverage because synthesizing large design spaces is costly, motivating public benchmarks and customized ML models incorporating domain knowledge.

4 LOGIC SYNTHESIS AND PHYSICAL DESIGN

ML methods are applied across logic synthesis and physical design to guide optimization, predict costly outcomes, and automate placement, routing, power, and emerging 3D-design decisions.

  • Logic Synthesis: Logic-synthesis studies use DNNs, CNNs, GCNs, and reinforcement learning to select optimization strategies, predict synthesis quality, or search transformations.These methods generally operate on existing synthesis primitives or model transformations as actions.
  • Placement: Placement methods use learned data-path extraction, evaluation, and graph-based macro representations to improve placement decisions.PADE separates data-path placement from random logic, while another approach embeds macro features and netlist adjacency for sequential macro placement.
  • Routing: ML models predict routing congestion, design-rule hotspots, and violation counts from placement-derived features, including image representations and congestion estimators.The reviewed approaches include CNNs, fully convolutional networks, encoder-decoders, and conditional GANs.
  • Performance and Analysis: Regression and generative or reinforcement-learning methods estimate timing, wirelength, area, power, clock-tree, and signal-integrity outcomes before expensive analyses.These approaches target early-stage prediction and reduce reliance on repeated simulator or sign-off tool calls.
  • Design Challenges for 3D Integration: 3D integration motivates ML-based optimization because die-to-die variation, expanded design spaces, and evaluation overhead challenge conventional modeling and search.The survey describes ML for 3D design-space exploration and reports TP-GNN results on RISC-V and NETCARD benchmarks.

5 LITHOGRAPHY AND MASK SYNTHESIS

Machine learning is applied across lithography hotspot detection, mask optimization, SRAF insertion, and lithography simulation to address costly, complex manufacturing steps. The reviewed methods improve scalability, mask quality, simulation speed, or hotspot analysis through prediction, optimization, and generative models.

  • 5.1 Lithography Hotspot Detection: Lithography hotspot detection uses ML to identify process-sensitive patterns before manufacturing, reducing reliance on time-consuming optical simulation.Methods include SVMs, neural networks, spatially aware feature extraction, and end-to-end object detection for large-scale layouts.
  • 5.1 Lithography Hotspot Detection: Region-based hotspot detection processes full or large-scale layouts by localizing areas where hotspots might occur.The approach is described as an end-to-end trainable object detection model for large-scale hotspot analysis.
  • 5.2 Machine Learning for Optical Proximity Correction: Heterogeneous OPC selects among multiple OPC solutions for a given design, while GAN-OPC combines mask generation with quality estimation and ILT-guided pre-training.ILT-guided pre-training replaces the discriminator with an ILT convolution model before jointly training the GAN to address convergence difficulty.
  • 5.2 Machine Learning for Optical Proximity Correction: 70× speedup and 0.43× mask complexity are reported for neural-ILT compared with traditional ILT methods.Neural-ILT replaces the costly ILT process with a neural network, penalizes complex masks, and uses a CUDA-based accelerator for lithography simulation.
  • 5.2 Machine Learning for Optical Proximity Correction: DAMO applies an end-to-end conditional GAN framework with coarse-to-fine window splitting to full-chip OPC and outperforms state-of-the-art academic and industrial solutions on ISPD 2019 layouts.The framework uses a UNet++ backbone with residual bottleneck blocks and clusters via-density regions for window selection.
  • 5.4 Machine Learning for Lithography Simulation: LithoGAN maps mask patterns to resist patterns with a conditional GAN for shape modeling and a CNN for center prediction, reducing lithography simulation time by several orders of magnitude.The CNN addresses the GAN’s imprecise pattern positioning while retaining its shape-generation capability.

6 ANALOG DESIGN

Analog design remains labor-intensive because its topology, device sizing, specifications, noise sensitivity, and process variation create a large and difficult design space. ML research spans topology selection, feature extraction, topology generation, device sizing, and analog layout automation, although manual work remains necessary.

  • 6 ANALOG DESIGN: Analog design demands substantial manual effort because its design space and specifications vary widely, while signals are sensitive to noise and process-voltage-temperature variation.Analog and RF blocks can occupy little area but account for most design effort in mixed-signal SoCs.
  • 6 ANALOG DESIGN: The analog flow combines top-down topology and device-size optimization with bottom-up layout synthesis and verification.Topology design and device sizing form the pre-layout stage before layout-oriented steps.
  • 6 ANALOG DESIGN: ML applications range from topology selection and feature extraction to topology generation, device sizing, and analog layout.These efforts aim to support stages where automatic tools have not yet replaced manual design work.
  • 6.2 Topology Design Automation: Topology selection methods use learned relationships between specifications and candidate alternatives, while feature-extraction methods identify building blocks, hierarchical structures, templates, overlaps, and symmetry.FASY is an early fuzzy-logic topology-selection tool, and later work applies supervised, unsupervised, and graph-based methods.
  • 6.2.1 Topology Selection: Topology selection is efficient mainly for repetitive designs because data collection and model training are time-consuming.A trained model can be reused when similar design tasks recur.
  • 6.2 Topology Design Automation: An RNN and hypernetwork generate two-port circuit topologies for given specifications and report better performance than traditional methods when inductor circuit length n≥4.This work addresses topology generation directly, unlike earlier studies that focused on selection or feature extraction.

6.3 Machine Learning for Device Sizing Automation

Device sizing is formulated as an optimization from circuit parameters to specifications, with reinforcement learning, graph-based agents, data augmentation, and predictive models used to automate or accelerate the search. The methods reduce deployment or simulation costs but retain substantial training and simulation dependencies.

  • 6.3. Machine Learning for Device Sizing Automation: Device sizing maps design parameters, including transistor, capacitor, and resistor sizes, to circuit specifications and normalized optimization objectives.Rigid targets include bandwidth, DC gain, and phase margin, while optimization targets include power and area.
  • 6.3.1 Reinforcement Learning Based Device Sizing: Reinforcement learning updates device sizes by feeding simulator observations to an agent, computing rewards from current performance, and selecting sizing actions.The framework uses simulator interaction as the environment for iterative design optimization.
  • 6.3.1 Reinforcement Learning Based Device Sizing: 9.4× acceleration is reported when transfer learning trains the agent with schematic simulations and validates it with post-layout simulations.Additional deployment iterations are used to adapt the approach while reducing post-layout simulation overhead.
  • 6.3.1 Reinforcement Learning Based Device Sizing: A GCN-based reinforcement-learning agent aggregates neighboring transistor features to incorporate circuit-netlist topology into device-sizing decisions.Its trainable weight matrix is updated by DDPG, and weights can be reused across circuits with similar design principles.
  • 6.3.2 Artificial Neural Network Based Device Sizing: Data augmentation generates copies with worse specifications by adjusting sample means and optimization directions, producing more robust models on the augmented dataset.The parameter γ∈[0, 1] adjusts the mean value, while Δ and Γ encode random perturbations and maximize-or-minimize directions.
  • 6.3.2 Artificial Neural Network Based Device Sizing: A three-layer MLP combines regression for device sizing with classification for topology selection using circuit performances as input.The model outputs device sizes across multiple topologies together with topology classifications.
  • 6.3.3 Machine Learning Based Prediction Methods: ML methods require more training simulations than genetic methods but need only a few inference iterations during deployment, while complex circuits remain challenging.Combining genetic algorithms with ML predictors is described as a way to reduce simulation needs.

6.4 Machine Learning for Analog Layout

ML-based analog layout research addresses the strong effect of parasitics and the complex relationship between layout and circuit performance. Approaches generate layouts, infer hierarchy, automate routing, search legacy designs, optimize layouts in closed loop, estimate parasitics, and predict post-layout performance.

  • 6.4 Machine Learning for Analog Layout: Analog layout is difficult because parasitics significantly affect circuit performance, creating a gap between pre-layout and post-layout simulation.Traditional parasitic estimation relies on designer experience and can increase design time and inaccuracy.
  • 6.4 Machine Learning for Analog Layout: GAN-based layout generation produces wells with post-layout op-amp performance comparable to manual designs, while a GCN reaches 100% hierarchy-partition accuracy in 275 test cases.The GCN takes a circuit netlist as input and outputs circuit hierarchy before postprocessing.
  • 6.4 Machine Learning for Analog Layout: Other layout approaches use a VAE for automated routing, knowledge-based comparison with legacy designs, and multi-objective Bayesian optimization with simulation feedback.These methods represent distinct automation strategies for routing, reuse, and closed-loop layout exploration.
  • 6.4 Machine Learning for Analog Layout: GNNs and random forests estimate parasitic capacitance, resistance, and device parameters from schematics or engineered net features before layout.Multi-port nets may be simplified with star topologies to support parasitic regression.
  • 6.4 Machine Learning for Analog Layout: ML predicts layout performance using SVM, random forest, neural networks, and 3D CNNs, with prediction combined with simulated annealing for automated layout.These methods target the high cost of SPICE-like post-layout simulation.

6.5 Conclusion of Analog Design

Machine learning has shown strong results for analog device sizing, topology design, and layout, often using fewer simulation rounds while producing higher-quality designs. However, current methods remain limited by narrow training data and incomplete coverage of analog design problems.

  • Machine learning methods achieve higher-quality analog designs with fewer simulation rounds than previous optimization-based algorithms.The reported applications include device sizing, topology design, and layout.
  • Existing models cannot yet replace human experts in the analog design flow.The survey identifies limited flexibility as one obstacle.
  • Most researchers train and test on typical circuits such as OTAs, motivating models that generalize across varied circuits.The survey explicitly calls for a generalizable model for a variety of circuits.
  • System-level analog design has not been studied, leaving further machine-learning potential for future work.

7 VERIFICATION AND TESTING

Verification and testing are costly because they require broad coverage over complex digital, analog, and RF behaviors. The surveyed ML methods reduce redundancy, predict outcomes from cheaper measurements, and guide test generation and selection.

  • Verification and testing are complicated and expensive because of coverage requirements and high circuit complexity.Verification occurs throughout the EDA flow, while testing evaluates fabricated chips.
  • Compact test sets must avoid repeated or useless situations while covering enough input combinations for reliable verification.
  • Cheap, low-precision tests can support accurate prediction of analog/RF results, reducing the need for costly direct testing or formal verification.
  • ML methods address verification and testing through redundancy reduction, estimation, result inference, sample-strategy optimization, and test-bench generation.
  • Coverage has different meanings across problems, including FSM states or input situations for digital designs and input values for analog/RF systems.
  • Coverage-directed generation combines simulation and coverage evaluation with ML-guided search, including Bayesian networks, Markov models, genetic algorithms, SVMs, and rule learning.
  • Analog/RF specification testing is costly because repeated measurements must cover configurations such as temperature, voltage, load, and operating modes.
  • ML can identify redundant information in specification tests, fit regression models from limited samples, and predict test quality before expensive synthesis.Pan et al. use partial testing and extracted features to infer performance curves; Liu et al. report over 11× synthesis time reduction.

8 OTHER RELATED STUDIES

Related EDA studies apply ML to power prediction, SAT solving, GPU-accelerated physical design, and synthesis-parameter tuning. These approaches target faster estimation, learned heuristics, and more efficient exploration of large design spaces.

  • Power estimation trades accuracy against simulation complexity, motivating ML models that provide faster predictions at controlled error.
  • PRIMAL combines PCA, MLP, and CNN models to estimate RTL power from encoded register-toggle patterns.
  • 50× speedup with average error below 5% is reported for PRIMAL versus gate-level power estimation.
  • GRANNITE uses a GNN with gate-level netlist information to improve transferability across designs while retaining RTL-level power prediction.It reports average speedup of two orders of magnitude and average relative error within 5.5% against probabilistic switching-activity estimation.
  • SAT research uses supervised learning, SVMs, neural networks, GNNs, and reinforcement learning to select restarts, tune heuristics, encode formulas, and guide search.
  • EDA physical-design solvers increasingly target multicore CPUs and GPUs, but developing effective GPU implementations remains challenging.DREAMPlace uses deep-learning software infrastructure to build a GPU-accelerated placement framework.
  • Learning-based synthesis methods tune complete parameter settings and use collaborative filtering to recommend configurations within large design spaces.

9 DISCUSSION FROM THE MACHINE LEARNING PERSPECTIVE

From an ML-application perspective, the survey organizes EDA uses into four categories spanning decreasing manual effort and increasing automation. These categories cover configuration decisions, performance prediction, black-box optimization, and automated design across EDA tasks.

  • The survey revisits prior studies according to how ML functions within the EDA workflow.
  • Most EDA applications fall into decision making, performance prediction, black-box optimization, or automated design.
  • Decision making in traditional methods: Decision-making methods replace brute-force or empirical configuration choices for tool chains, algorithms, and hyper-parameters.
  • The overview spans HLS design-space exploration, analog topology design, placement and routing, and physical-implementation tasks.
  • Representative models include regression, SVM, random forest, XGBoost, CNN, GAN, MARS, and other neural-network methods.

9.2 Data Preparation

Data preparation for ML-based EDA emphasizes constructing high-quality datasets, extracting task-specific features, preprocessing inputs, and adapting models across domains.

  • Data Preparation: Dataset volume and quality are essential to ML model performance in EDA.Reviewed studies discuss engineering datasets that are large, fair, and clean.
  • Data Preparation: Raw-data collection typically combines features with ground-truth labels, using images, geometric or graph-based netlist features, or algorithmically generated features.Feature extraction is generally problem-specific, although shared heuristics exist.
  • Data Preparation: Semi-supervised techniques and improved preprocessing can expand datasets and increase data efficiency.Researchers also adapt models and input features to reduce data requirements.
  • Data Preparation: Feature preprocessing commonly includes normalization, edge-data removal, and dimensionality reduction with PCA or LDA.These operations adjust model inputs before learning.
  • Data Preparation: Domain-adaptive models use specifications of a new application domain to predict results from knowledge acquired in the original domain.The reviewed approach is applied to cross-platform performance estimation for FPGA design instances.

10 CONCLUSION AND FUTURE WORK

The survey finds ML applicable across nearly all EDA hierarchy stages and reviews this literature from both EDA and ML perspectives. It identifies full-fledged tools, newer techniques, and trustworthy predictions as priorities for future work.

  • 10 CONCLUSION AND FUTURE WORK: ML techniques have been applied across almost all stages of the EDA hierarchy, and the survey reviews the literature from both EDA and ML perspectives.The paper presents ML for EDA as a promising direction for accelerating tasks by learning from prior experience.
  • Future Work: Purely ML-based solutions remain below industrial needs for some tasks, including analog/RF testing and physical design.The survey therefore emphasizes combining ML with traditional methods and addressing simplified or inflexible design spaces.
  • Future Work: Future research should broaden applications of point-cloud models, graph convolutional networks, domain adaptation, and reinforcement learning in EDA.The survey identifies these as newer ML models, methodologies, or techniques beginning to enter the field.
  • Future Work: Broad adoption of ML in EDA depends on trustworthy predictions and outputs.The survey frames understanding how ML works and its outputs as important to trust in the technology.
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