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DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era
Satyabrata Sarangi, Bevan Baas
TL;DR
Deep-submicron CMOS scaling estimates based on classical Dennard assumptions have become less accurate, creating a need for better estimation approaches. DeepScaleTool models published silicon trends, fits polynomial curves, and extrapolates scaling factors from 130 nm to 7 nm. Compared with TSMC scaling data, its errors are 1% for area, 2.5% for delay, and 5% for power, while the cited alternative modeling approach has larger errors for area, delay, and power.
Problem
Traditional scaling-factor estimates are no longer accurate in the deep-submicron regime, while accurate node-to-node estimates are needed for educational, research, and cross-node design comparisons.
Method
DeepScaleTool analyzes published silicon trends, fits second-order polynomial models, extrapolates missing nodes, and provides scaling factors through a spreadsheet framework.
Results
1% area error, 2.5% delay error, and 5% power error are reported against TSMC scaling data from 10 nm to 7 nm.
Takeaways & Limitations
Published-silicon-data modeling correlates better with TSMC scaling trends than the cited ITRS- and PTM-based modeling approach.
Abstract
from arXiv · showhide
The estimation of classical CMOS "constant-field" or "Dennard" scaling methods that define scaling factors for various dimensional and electrical parameters have become less accurate in the deep-submicron regime, which drives the need for better estimation approaches especially in the educational and research domains. We present DeepScaleTool, a tool for the accurate estimation of deep-submicron technology scaling by modeling and curve fitting published data by a leading commercial fabrication company for silicon fabrication technology generations from 130~nm to 7~nm for the key parameters of area, delay, and energy. Compared to 10~nm--7~nm scaling data published by a leading foundry, the DeepScaleTool achieves an error of 1.7% in area, 2.5% in delay, and 5% in power. This compares favorably with another leading academic estimation method that achieves an error of 24% in area, 9.1% in delay, and 24.9% in power.
I. INTRODUCTION
Traditional CMOS scaling becomes inaccurate in the deep-submicron regime, motivating DeepScaleTool, which estimates scaling factors from industrial trends for educational and research use.
- Dennard scaling becomes inaccurate as deep-submicron transistors encounter short-channel effects, leakage, thermal runaway, and process variation.
- Accurate scaling estimates matter for fair comparisons of design performance and metrics across fabrication nodes.
- DeepScaleTool uses industrial technology trends and polynomial curve fitting to estimate deep-submicron scaling factors.
- DeepScaleTool is a spreadsheet-based tool estimating area, delay, and energy scaling from 130 nm to 7 nm.
- The work analyzes errors between classical scaling factors and estimates derived from real silicon data.
- The tool compares its estimates with PTM-, ITRS-, and TSMC-based scaling approaches.
II. TRANSISTOR SCALING TRENDS, DATA MODELING, AND DEEPSCALETOOL FRAMEWORK
DeepScaleTool is built by analyzing published transistor trends, fitting available data, extrapolating missing nodes, and embedding the resulting factors in a spreadsheet framework.
- Published transistor scaling trends are analyzed before fitting available technology-node data with second-order polynomial models.
- Scaling data are extrapolated for technology nodes missing from the published datasets.
- The spreadsheet framework uses modeled scaling factors for combinations of starting and target technology nodes.
A. Transistor Scaling Trends
Published Intel-based studies describe scaling trends in delay, energy, area, performance, and power, including more aggressive area scaling at newer nodes.
- Holt reports generational benefits in gate delay, switching energy, and energy-delay product from approximately 65 nm to 10 nm.
- Intel-derived scaling trends indicate increased transistor density, higher performance, and lower power for circuits.
- 14 nm and 10 nm each achieve 0.37 times the logic-area scaling of the previous generation.
B. Data Extraction and Modeling
The modeling process digitizes published plots, extrapolates missing technology generations, and fits polynomial models with high reported goodness of fit.
- Digitized scaling data are extracted from properly labeled plots using g3data.
- Missing generations are extrapolated to obtain area, delay, and energy trends from 130 nm to 7 nm.
- Polynomial curve fits for the circuit parameters achieve R2 values of at least 0.99.
C. DeepScaleTool Framework
DeepScaleTool uses a spreadsheet-based VBA framework to automatically generate scaling factors for supported circuit parameters and technology nodes.
- DeepScaleTool is a spreadsheet-based framework for automated generation of scaling factors across technology fabrication nodes.The framework is implemented using Visual Basic for Applications (VBA).
III. USAGE OF DEEPSCALETOOL AND SCALING FACTOR COMPUTATION EXAMPLES
Users select current and target technology nodes, generate a scaling factor for a metric, and use the tool’s instructions to compute the target value.
- The tool supports nodes from 130 nm through 7 nm, including 130, 90, 65, 45, 40, 32, 28, 22, 14, 10, and 7 nm.Users enter a current node and target node from the supported list.
- Figure 2 presents the current and target node inputs, generated scaling factors, and user instructions.
- Users select a performance metric or parameter and press its corresponding button to display the scaling factor.The workflow is presented as part of the tool’s three-step usage process.
B. Examples of Scaling Factor Computation
The examples illustrate how DeepScaleTool scaling factors are applied to estimate target-node metrics, while the figures summarize modeled trends and comparisons with traditional factors.
- 8.3 is the area scaling factor for scaling from 130 nm to 45 nm, producing 12.05 um2 from an initial 100 um2 area.The computation is 100 / 8.3 = 12.05 um2.
- 1.238 is the power scaling factor for scaling from 45 nm to 32 nm, producing 80.775 mW from an initial 100 mW power dissipation.The computation is 100 / 1.238 = 80.775.
- Scaling factors for delay, energy, energy delay product, throughput, throughput/area, and power density can be generated using the tool’s corresponding primary metrics.
- Figure 3 presents modeled scaling trends for area, delay, and power from 130 nm to 7 nm.
- Figure 4 compares traditional scaling factors with the modeled factors for the deep-submicron regime.
IV. COMPARISON OF SCALING FACTORS ESTIMATION METHODS AND ACCURACY WITH TRADITIONAL SCALING
Modeled scaling diverges from traditional expectations in deep-submicron technologies: area remains comparatively strong, while delay, power, and energy show larger deviations driven by physical and interconnect limits.
- Scaling trends: Area scaling shows the least variation and remains at or above traditional estimates, supported by high-dielectric metal gates, FinFETs, and 3D FinFETs.
- Scaling trends: Delay and throughput achieve minimal scaling at recent technology nodes, while delay and power differ substantially from traditional 1/K and 1/K2 improvements.
- Scaling trends: Leakage current limits threshold-voltage and supply-voltage scaling, constraining energy-efficiency improvement below the traditional 1/K3 factor.
- Scaling trends: Slower interconnect scaling primarily limits transistor gate-delay scaling, contributing to poor delay, power, and energy-efficiency trends.
B. Comparison of Scaling Factor Estimation Methods
DeepScaleTool correlates more closely with TSMC scaling data than the ITRS- and PTM-based approach, especially for area, delay, and power. Its silicon-data modeling also produces a substantially larger 130 nm-to-7 nm area scaling factor than the comparison method.
- Comparison with TSMC data: 1%, 2.5%, and 5% are DeepScaleTool’s errors for area, delay, and power, respectively, against TSMC’s 10 nm-to-7 nm scaling data.The corresponding errors for the ITRS- and PTM-based approach are 24–29%, 9.1%, and 24.9%.
- Comparison with TSMC data: DeepScaleTool achieves better correlation with TSMC scaling data than the ITRS- and PTM-based modeling approach for area, delay, and power.The comparison uses modeled Intel silicon trends and TSMC-based scaling data.
- Area scaling across generations: 754.55 is DeepScaleTool’s modeled area scaling factor from 130 nm to 7 nm, compared with 110 for the alternative method.The paper also states that area generally scales down by approximately 303 over eight generations in this range.
- Area scaling across generations: DeepScaleTool uses silicon-data modeling to estimate scaling factors across major foundries and avoid prediction inaccuracies from ITRS and PTM models.The paper attributes the larger area factor partly to aggressive scaling exceeding the normal rate of 0.49.
V. CONCLUSION
DeepScaleTool estimates deep-submicron scaling factors using published silicon trends and polynomial curve fitting. The tool is presented as a platform for reliable scaling estimates, understanding discrepancies with traditional factors, and comparing circuit performance across technology nodes.
- Method: DeepScaleTool estimates scaling factors from published silicon trends using a polynomial-based curve-fitting method.The primary datasets come from Intel, while the resulting estimates also correlate with TSMC scaling trends.
- Conclusion: The tool shows that traditional scaling factors become obsolete in the deep-submicron era.The conclusion contrasts published-silicon modeling with simulation-based modeling using ITRS and PTM data.
- Conclusion: DeepScaleTool provides an easy platform for obtaining reliable scaling factors for design parameters in the deep-submicron era.It also supports examining discrepancies with traditional scaling factors and comparing circuit performance across technology nodes.