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Logical-qubit operations in an error-detecting surface code
J. F. Marques, B. M. Varbanov, M. S. Moreira, H. Ali, N. Muthusubramanian, C. Zachariadis, F. Battistel, M. Beekman, N. Haider, W. Vlothuizen, A. Bruno, B. M. Terhal, L. DiCarlo
TL;DR
Quantum error correction needs logical-qubit operations alongside repeated stabilization, but experimental evidence for complete operation suites under multi-round stabilization remains limited. This paper implements initialization, measurement, and universal logical gates in a distance-two superconducting surface code, finding higher performance for fault-tolerant variants and slightly higher performance for pipelined stabilization.
Problem
Error-corrected quantum computers require logical-qubit operations and repetitive parity checks, while prior trapped-ion QEC experiments were generally limited to a single stabilization round.
Method
The paper realizes initialization, measurement, and universal single-qubit gates in a distance-two surface code undergoing repeated error detection, including logical Pauli transfer-matrix process tomography and stabilization-scheme comparisons.
Results
The complete logical-operation suite preserves multi-round stabilization, with fault-tolerant variants outperforming non-fault-tolerant variants and pipelined stabilization slightly exceeding parallel stabilization.
Takeaways & Limitations
The results demonstrate integrated logical operations and repeated stabilization in a superconducting surface-code architecture relevant to higher-distance implementations.
Takeaways & Limitations
The distance-two code detects but cannot correct physical errors, and the simulations omit several relevant error sources, including measurement-induced dephasing and some readout-related crosstalk.
Abstract
from arXiv · showhide
We realize a suite of logical operations on a distance-two logical qubit stabilized using repeated error detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere, and a universal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference through detailed characterization. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes.
INTRODUCTION
Error-corrected quantum computing requires logical-qubit operations and repetitive parity checks that detect and potentially correct physical errors. This work uses a distance-two surface code that supports error detection through post-selection while implementing a broad suite of logical operations.
- Logical qubits encode information in a two-dimensional subspace of many entangled physical qubits.
- Repetitive parity checks can detect physical errors while preserving encoded information, with fault-tolerant operation required for error suppression as code distance increases.
- The paper demonstrates arbitrary logical-state initialization, cardinal-basis measurements, universal single-qubit gates, logical process characterization, and scalable stabilizer-scheme comparisons during multi-round stabilization.
- The distance-two surface code uses four data qubits to encode one logical qubit in the even-parity stabilizer subspace.
- Because phase-flip errors share syndromes, this code detects but cannot correct such errors; stabilization therefore post-selects runs with no detected syndrome.
RESULTS
The experiments characterize stabilizer-based logical-state preparation in a distance-two surface code and compare fault-tolerant variants with conventional preparation. They show high logical fidelities across cardinal states while using repeated measurements and post-selection.
- Stabilizer assignment fidelities are 94.2%, 86.1%, and 97.2% for the measured parity operators.
- Logical cardinal states are prepared by initializing product states and applying stabilizer measurements that project the register toward the desired codespace state.
- Figure 1 compares estimated physical density matrices for four logical cardinal states with their ideal target density matrices.
- Logical fidelities for |0L⟩, |1L⟩, |+L⟩, and |−L⟩ reach 99.83%, 99.97%, 97.02%, and 95.54% under the initial procedure.
- Fault-tolerant preparation of |+L⟩ and |−L⟩ raises logical fidelities to 99.78% and 99.64%, matching the performance of |0L⟩ and |1L⟩ preparation.
Logical measurement of arbitrary states
The distance-two surface code prepares arbitrary logical states and measures them in the ZL, XL, and YL bases with additional error detection. Fault-tolerant ZL and XL measurements achieve higher logical assignment fidelities than the non-fault-tolerant YL measurement.
- Measurement procedure: Logical operators ZL, XL, and YL are evaluated from data-qubit measurements with additional error detection.The measurement outcomes also provide stabilizer information for detecting errors.
- Equatorial states: ⟨XL⟩ and ⟨YL⟩ oscillate sinusoidally while ⟨ZL⟩ remains near zero for equatorial logical states.These states are prepared by setting θ = π/2 and sweeping φ.
- Equatorial states: 95.8% for XL and 87.5% for YL, with the lower YL fidelity reflecting its non-fault-tolerant measurement.The YL measurement also has a higher post-selected fraction P.
- XL-ZL plane: 99.4% for ZL and 96.4% for XL when measuring states prepared on the XL-ZL plane.Both measurements are fault-tolerant.
- Measurement comparison: ZL measurement is less vulnerable than XL measurement because it faces only vertical double bit-flip errors, whereas XL also faces horizontal and diagonal double phase-flip errors.
Logical gates
The experiment implements arbitrary logical rotations and a universal single-qubit gate set, then characterizes logical gates through process tomography and logical Pauli transfer matrices. Fault-tolerant transversal gates are assessed alongside generally non-fault-tolerant rotations.
- Process tomography: TL process tomography initializes six cardinal logical states, characterizes input and output states by four-qubit tomography, and projects them onto the codespace.The resulting logical density matrices support extraction of logical Pauli transfer matrices.
- Gate characterization: Logical state tomography and extracted logical Pauli transfer matrices characterize the implemented TL, ZL, and XL gates.The logical density matrices are obtained after projecting four-qubit tomography results onto the codespace.
- Repeated stabilization: 840 ns for pipelined and 1000 ns for parallel stabilizer measurement cycles, enabling comparison of repeated error-detection schemes during logical operations.The figure compares logical-state behavior and post-selected data as cycle count and experiment duration increase.
- Gate characterization: 97.3%, 95.6%, 97.9%, and 98.1% are the reported average logical gate fidelities extracted from the logical Pauli transfer matrices.
Pipelined versus parallel stabilizer measurements
The paper compares two scalable stabilizer-measurement schemes whose cycle duration remains independent of code distance. Their performance is comparable, with a slight advantage for pipelining.
- Scalable stabilization schemes: The pipelined and parallel schemes are both scalable because their cycle duration remains independent of code distance.Pipelining interleaves stabilizer operations with ancilla readout, whereas the parallel scheme performs all ancilla readouts simultaneously.
- Performance comparison: γpip ∼45% was slightly lower than the parallel error-detection rate, with γpip/γpar ∼97% across input logical states.The authors attribute the pipelined advantage most likely to its shorter cycle duration.
- Performance trade-offs: The two schemes balance shorter pipelined cycles against extra ancilla dephasing introduced during the interleaved readout process.Density-matrix simulations indicate that relaxation, dephasing, and readout assignment errors alone do not explain the observed net error-detection rate.
Process tomography in the codespace
Logical process tomography constructs a logical Pauli transfer matrix from tomographically characterized input and output states projected into the codespace, then enforces physical-channel constraints.
- Logical Pauli transfer matrix: A Pauli transfer matrix maps input Pauli expectation values to the corresponding output-state expectations for a single-qubit gate.The input representation includes p0 = 1.
- Process reconstruction: The logical transfer matrix is reconstructed by linear inversion from six overcomplete cardinal logical input states and their corresponding outputs.Both input and output states are obtained through four-qubit tomography followed by projection into the codespace.
- Physicality constraints: The reconstructed matrix may violate trace preservation and complete positivity, so it is converted to a Choi representation for constraint enforcement.The resulting Choi matrix must satisfy a partial-trace constraint in addition to being a density matrix.
- Gate characterization: Convex optimization produces the optimal physical Choi representation, from which the logical transfer matrix and average logical gate fidelity are computed.The fidelity compares the reconstructed logical gate with the ideal target transfer matrix.
Extraction of error-detection rate
The post-selected fraction decays exponentially with the number of error-detection cycles, consistent with a constant error-detection rate per cycle.
- Exponential decay: The post-selected data fraction P decreases exponentially as the cycle count n increases.This behavior is observed in the repetitive error-detection experiment.
- Rate model: The exponential decay is modeled using a constant per-cycle error-detection rate γ.The rate is extracted by fitting the dependence of P on n.
- Rate extraction: Fitting P as a function of n provides the experiment’s error-detection rate γ.The supplied passage introduces the fit but does not provide the numerical fitted value.
DEVICE CHARACTERISTICS
The device characterization covers transmon parameters, parity-check performance, repeated stabilization, readout behavior, and error sources affecting post-selection. Leakage accumulates with cycle count, while post-selection rejects affected runs and simulations identify decoherence and SPAM errors as dominant contributors.
- Parity-check performance: 94.2%, 86.1% and 97.2% are the average assignment fidelities of the three measured Z-type parity checks.The checks are ZD1ZD3, ZD1ZD2ZD3ZD4 and ZD2ZD4, respectively.
- Leakage: Single-shot readout histograms show leakage accumulation at n = 8 and n = 15 compared with n = 1.The additional Gaussian-distributed population is consistent with leakage, mostly to |2⟩.
- Leakage: Post-selection rejects runs where leakage occurred on the measured transmons, limiting its expected effect on logical initialization and gate fidelity.Leakage can nevertheless considerably affect the error-detection rate.
- Repeated stabilization: The post-selected fraction P decays exponentially with the number of error-detection cycles n, consistent with a constant error-detection rate per cycle.The rate is extracted by fitting the observed decay.
- Density-matrix simulations: SPAM errors and decoherence are the dominant contributors to the simulated error-detection rate, while the baseline modeled sources fail to reproduce the experimental decay quantitatively.The baseline includes decoherence, flux-noise dephasing, SPAM errors and residual-ZZ crosstalk.
- Leakage: L1 ≈ 5% produces a good match to experiment, suggesting leakage significantly impacts the observed error-detection rate.The estimate assumes the same leakage rate for all CZ gates and may be overestimated because of model approximations and omitted error sources.
- Scope: Leakage is an important error source for larger-distance quantum error-correction experiments, motivating detection-based post-selection or leakage-reduction units.The detailed leakage rates and mechanisms are left for future work.
Error models
The simulations model transmon noise through amplitude damping, phase damping, flux-noise dephasing, and experimentally parameterized coherence effects during idling and gates.
- Decoherence: Amplitude damping is parameterized by the relaxation time T1, while phase damping is parameterized by the pure-dephasing time at the sweetspot.These channels are included in the density-matrix simulations of repetitive error detection.
- Decoherence: The qutrit amplitude- and phase-damping channels are inserted during idling periods and symmetrically around each single- or two-qubit gate.Each inserted period lasts half the duration of the corresponding gate.
- Flux-noise dephasing: Flux noise away from the sweetspot adds dephasing determined by the qubit’s flux sensitivity and the flux-noise spectral-density scaling parameter.The resulting dephasing time parameterizes the damping channel during CZ interaction and parking frequencies.
- Flux-noise dephasing: Slow-frequency flux-noise components are neglected because sudden Net Zero pulses echo out this noise to first order.The simulations therefore focus on the fast-frequency contribution to dephasing away from the sweetspot.
Model 3
The model includes residual excitation and measurement errors, then incorporates calibrated phase effects from residual ZZ crosstalk during parity-check circuits.
- State preparation and measurement: Residual excitation is modeled by initializing a transmon in |1⟩ with probability pe instead of |0⟩.The probability pe is extracted from double-Gaussian fits to single-shot readout voltages.
- State preparation and measurement: Measurement errors are represented by POVM operators Mi whose probabilities P(i|j) describe outcome i after preparing state j.The model includes outcomes i ∈ {0, 1, 2}.
- State preparation and measurement: The simulation applies the measured assignment probabilities for prepared |0⟩ and |1⟩ states and sets P(0|2) = 0.The latter assumption is consistent with the observed readout histograms.
- Post-selection: The post-selected fraction combines the probability of trivial data-qubit syndromes with the probability of measuring each ancilla in |0⟩.This calculation conditions on detecting no error.
- Residual ZZ crosstalk: The optimized CZ phases capture the net ZZ-crosstalk effect included in simulation, while phase errors during ancilla readout are omitted under ancilla-|0⟩ conditioning.The CZ gates are jointly calibrated for each parity-check block.
- Residual ZZ crosstalk: Measured Ramsey phases satisfy ⃗φRam = A⃗φCZ, where A encodes the linear dependence between parity-check phases and CZ phases.The CZ-phase parameters are constrained by 0 ≤ ⃗φCZ_j < 2π.
Model 5
The model includes selected CZ-gate leakage and crosstalk effects while omitting several higher-order and measurement-related error mechanisms.
- Leakage model: CZ leakage is modeled as population exchange between |11⟩ and |02⟩, except for the A1–D3 gate, which exchanges population with |20⟩.The exception reflects use of the |11⟩–|20⟩ avoided crossing for that gate.
- Leakage model: The simulation neglects leakage-conditional phases, higher-excited-state excitation, and leakage mobility.Non-leaked transmons interacting with leaked ones are assigned ideal leakage-conditional phases.
- Unmodeled error sources: Measurement-induced ancilla dephasing and readout-dependent crosstalk are omitted, limiting comparison of pipelined and parallel parity-check schemes.The model also does not capture the additional phase error from noncommuting ZZ crosstalk and amplitude damping.