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Interleaving: Modular architectures for fault-tolerant photonic quantum computing

Hector Bombin, Isaac H. Kim, Daniel Litinski, Naomi Nickerson, Mihir Pant, Fernando Pastawski, Sam Roberts, Terry Rudolph

arXiv:2103.08612v1quant-ph

TL;DR

The paper addresses how to scale fault-tolerant photonic quantum computing beyond small resource-state generators by using fiber delays as quantum memory. It introduces interleaving modules and finds that 1-km delays can support four logical distance-35 surface-code qubits per RSG while tolerating photon-loss rates above 2%, with broader architectural extensions.

  • Problem

    Fault-tolerant FBQC requires a scalable architecture that increases available qubits beyond small resource states and supports large computations.

    Source: §III · p. 11, §IV · p. 19

  • Method

    The paper combines RSGs, fusion devices, switches, and fiber delays into interleaving modules that reuse RSGs for successive resource-state production.

    Source: §I · p. 6, B. Universal interleaving modules · p. 11, §IV · p. 19

  • Results

    Four logical distance-35 surface-code qubits per RSG are achievable with 1-km fiber delays while tolerating photon-loss rates above 2% in addition to fiber-delay loss.

    Source: D. Hardware considerations · p. 18, §IV · p. 19

  • Takeaways & Limitations

    Interleaving can reduce logical-operation costs, support unconventional geometries, and scale disconnected matter-qubit devices into larger quantum computers when they transduce to photons.

    Source: §IV · p. 19

Abstract

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Useful fault-tolerant quantum computers require very large numbers of physical qubits. Quantum computers are often designed as arrays of static qubits executing gates and measurements. Photonic qubits require a different approach. In photonic fusion-based quantum computing (FBQC), the main hardware components are resource-state generators (RSGs) and fusion devices connected via waveguides and switches. RSGs produce small entangled states of a few photonic qubits, whereas fusion devices perform entangling measurements between different resource states, thereby executing computations. In addition, low-loss photonic delays such as optical fiber can be used as fixed-time quantum memories simultaneously storing thousands of photonic qubits. Here, we present a modular architecture for FBQC in which these components are combined to form "interleaving modules" consisting of one RSG with its associated fusion devices and a few fiber delays. Exploiting the multiplicative power of delays, each module can add thousands of physical qubits to the computational Hilbert space. Networks of modules are universal fault-tolerant quantum computers, which we demonstrate using surface codes and lattice surgery as a guiding example. Our numerical analysis shows that in a network of modules containing 1-km-long fiber delays, each RSG can generate four logical distance-35 surface-code qubits while tolerating photon loss rates above 2% in addition to the fiber-delay loss. We illustrate how the combination of interleaving with further uses of non-local fiber connections can reduce the cost of logical operations and facilitate the implementation of unconventional geometries such as periodic boundaries or stellated surface codes. Interleaving applies beyond purely optical architectures, and can also turn many small disconnected matter-qubit devices with transduction to photons into a large-scale quantum computer.

I. PRINCIPLES OF FBQC AND INTERLEAVING

FBQC replaces static-qubit circuit arrays with fusion graphs executed by modular networks of resource-state generators, fusion devices, delays, and switches. Interleaving uses longer photonic delays to reuse RSGs, enlarging fusion-graph slices while trading computational speed for physical-qubit capacity.

FBQC architecture

  • FBQC represents computations as fusion graphs of few-qubit resource states connected by fusions, implemented by networks of RSGs, fusion devices, delays, waveguides, and switches.The paper focuses on 6-ring resource states, whose fusion graphs form simple cubic lattices.Source: §I · pp. 2–4

Interleaving principle

  • Interleaving allocates one RSG to successive fusion-graph resource states across different RSG cycles, allowing delays to expand the effective number of available qubits.Interleaving coordinates specify both the generating RSG and the cycle in which each resource state is produced.Source: §I · pp. 5–6

Layered interleaving

  • Replacing 1-delays with k-delays produces k interleaved copies of the original fusion graph, multiplying active qubits by k while requiring k RSG cycles per slice.This layered scheme can turn hardware capable of one logical qubit into hardware capable of k logical qubits.Source: §I · p. 6, Figure 3 · p. 6

Rastered interleaving

  • Rastered interleaving partitions each slice into L × L squares and assigns their resource states to one RSG across L^2 time bins.The corresponding modules use one RSG, five fusion devices, four switches, and delays of lengths 1, L, and L^2.Source: §I · pp. 6–7, Figure 4 · p. 7
  • Networks of n_x × n_y rastered modules produce slices of size L·n_x × L·n_y in L^2 RSG cycles, yielding an interleaving ratio of L^2.Compared with 1-delay modules, this is a linear space-time trade-off: L^2 more logical-qubit capacity at L^2 lower slice-generation speed.Source: §I · p. 7

Alternative coordinate assignments

  • Changing interleaving coordinates can make all networked fusions instantaneous, eliminating the L- and L^2-delays between neighboring modules at the cost of four module types.The four types share delay lengths but differ in hardware-component arrangement.Source: §I · p. 7

II. UNIVERSAL INTERLEAVING MODULES

The paper shows that interleaving modules can implement universal fault-tolerant FBQC using surface codes and lattice surgery. The construction preserves the repeated-resource-state architecture while adding reconfigurable measurement and routing capabilities.

Universal fault-tolerant computation

  • Networks of interleaving modules become universal fault-tolerant quantum computers when used with surface codes and lattice surgery.The construction provides explicit implementations of a universal set of logical operations.Source: §II · p. 8

A. From surface codes to fusion graphs

Surface-code time slices and spacetime diagrams can be translated into 6-ring fusion graphs whose cubes and boundaries encode fault-tolerant checks and logical structure.

Time slices and spacetime diagrams

  • Surface-code computations are represented as sequences of check-operator measurements on two-dimensional time slices or three-dimensional spacetime diagrams.Time increases upward in spacetime diagrams, while cuts through them represent individual time slices.Source: A. From surface codes to fusion graphs · p. 8
  • Square surface-code patches contain d × d physical qubits, with four-qubit bulk checks and two-qubit boundary checks.For the illustrated patch, d = 5; solid and dashed boundaries encode logical Z and X operators.Source: A. From surface codes to fusion graphs · p. 8

Spacetime diagrams

  • The translated protocols include logical two-qubit X ⊗X measurements, multi-qubit Pauli measurements, twist defects, and lattice dislocations.These features arise from moving boundaries and corner lines through the spacetime diagram.Source: A. From surface codes to fusion graphs · p. 8

Surface-code checks in fusion graphs

  • Bulk surface-code checks correspond to products of 12 fusion outcomes from eight resource states, while boundary checks use half-cubes and single-qubit outcomes.Twists use Y ⊗Y outcomes formed by multiplying X ⊗X and Z ⊗Z outcomes.Source: A. From surface codes to fusion graphs · pp. 8, 10

From spacetime diagrams to fusion graphs

  • A fusion graph is generated by filling the spacetime bulk with primal and dual check cubes in a three-dimensional checkerboard pattern, using half-cubes at boundaries.The number of cubes determines code distance, while a distance-d square time slice uses d^2 resource states.Source: Figure 6 · p. 9, A. From surface codes to fusion graphs · p. 10

B. Universal interleaving modules

Universal interleaving modules replace fixed fusion devices with reconfigurable operations that implement state injection, dislocations, twist defects, and lattice-surgery computations.

Universal interleaving modules

  • Universal interleaving modules replace fusion devices with reconfigurable devices that route photons to fusion or single-qubit measurement operations.The modules retain the regular bulk structure of the original interleaving architecture.Source: B. Universal interleaving modules · p. 10
  • A switch can perform an e−iXπ/8 rotation followed by Z measurement for non-Clifford magic-state injection.This operation supplies the T-gate resource states required for universal surface-code computation.Source: B. Universal interleaving modules · pp. 10–11, Figure 8 · p. 11
  • Additional delayed local fusions implement dislocations by delaying an x+-qubit by one RSG cycle.The construction assumes dislocations lie along x and do not terminate at module boundaries.Source: B. Universal interleaving modules · p. 11

Universal operations and full quantum computations

  • Magic-state preparation and arbitrary multi-qubit Pauli measurements form a universal logical-operation set compatible with surface codes and lattice surgery.These operations can be translated into switch settings for every RSG cycle of a module network.Source: B. Universal interleaving modules · p. 11

Beyond 6-ring fusion networks

  • Interleaving generalizes to translationally invariant Bravais-lattice fusion graphs, with switching needed to introduce topological features.Switching can alter fusion measurement bases or photon routing locations.Source: B. Universal interleaving modules · p. 11

III. BENEFITS OF INTERLEAVING IN ARCHITECTURAL DESIGN

The architecture uses fiber delays as memory and interconnects, then evaluates their loss tolerance, space-time trade-off, logical-operation cost, and extension to matter-based devices.

Benefits of interleaving in architectural design

  • Interleaving combines optical-fiber memory and macroscopic interconnects to support scalable modular fault-tolerant quantum computers.The section evaluates loss thresholds, the space-time trade-off, logical-operation costs, and matter-based extensions.Source: §III · p. 11

A. Increased number of logical qubits due to high delay-line loss tolerance

Numerical threshold simulations show that kilometer-scale fiber delays reduce baseline loss tolerance only modestly, supporting substantial interleaving despite delay loss.

Loss model

  • The simulations model baseline preparation, routing, and measurement loss together with delay loss determined by each photon’s time in fiber.For qubit i, the delay contribution depends on the number of RSG cycles N_i spent in the delay.Source: A. Increased number of logical qubits… · pp. 11–12

Syndrome-graph simulation

  • The syndrome-graph analysis represents parity checks as vertices and fusion outcomes as edges with direction-dependent erasure probabilities.Primal and dual syndrome graphs are identical, and each resource-state cube contributes six edges to each graph structure.Source: A. Increased number of logical qubits… · p. 12

Loss model

  • The studied rastering lengths range from L = 1 to L = 170, with optical-fiber loss modeled as 0.2 dB/km and 1 ns time bins.The interleaving ratio is L2, and the longest delay determines the additional loss considered in the threshold analysis.Source: A. Increased number of logical qubits… · pp. 11–12

Numerical threshold simulations

  • Thresholds are estimated by Monte Carlo simulations of periodic three-dimensional blocks using code distances d = 12, 16, 20 and a union-find decoder.At least 15,000 samples are used for each parameter combination.Source: A. Increased number of logical qubits… · pp. 12–13
  • 2.3% baseline loss remains tolerable with an interleaving ratio of L2 = 5041 requiring a 1 km delay, versus 2.7% with trivial interleaving.A 2 km delay reduces the baseline threshold to 1.9%, while delay loss can exceed that threshold because it affects only z+-photons.Source: Table II · p. 12, A. Increased number of logical qubits… · p. 13

B. Computational volume reductions due to linear space-time trade-offs

Interleaving trades slower individual logical operations for more encoded qubits, and this extra capacity can reduce total computational volume when used effectively.

B. Computational volume reductions due to linear space-time trade-offs

  • The interleaving ratio increases encoded logical qubits by L2 while decreasing logical-operation speed by L2, creating a linear space-time trade-off.The ratio must remain between a computation-dependent minimum and a loss-threshold maximum.Source: B. Computational volume reductions due… · p. 13
  • If the required interleaving ratio exceeds the loss-tolerance maximum, the computation cannot run unless additional hardware modules reduce the ratio.This constraint follows from the code's loss threshold.Source: B. Computational volume reductions due… · p. 13
  • Interleaving beyond the minimum can be counterproductive when added delay loss requires a larger code distance, increasing computational volume.Unused additional qubits likewise add redundant volume rather than improving the computation.Source: B. Computational volume reductions due… · p. 13
  • Additional logical qubits can reduce total computational volume through better-than-linear space-time trade-offs, including faster magic-state production and parallelized T gates.These benefits can reduce logical cycles and fusion-graph volume even when qubits × T gates does not decrease.Source: B. Computational volume reductions due… · p. 13
  • Increasing interleaving can reduce redundant computational volume by slowing logical execution enough for classical decoding to keep pace.Otherwise, decoder bottlenecks can stall computation or require resource states to be retained for auto-corrected rotations.Source: B. Computational volume reductions due… · p. 13

C. Modified connectivity to improve logical gates

Modified optical connectivity lets interleaving modules implement periodic boundaries, route qubits more efficiently, and realize unconventional or higher-dimensional fusion-graph geometries.

Periodic boundary conditions

  • Periodic boundaries can double encoded logical qubits at fixed footprint, reduce planar-patch footprint by two, or be generated with single-module delays and modular networks.Toric slices can use 1-, M-, and M^2-delays, while staggered modules reduce these delays to 1/n, M/n, and M^2/n.Source: C. Modified connectivity to improve… · pp. 14–15, Figure 10 · p. 14

Qubit routing

  • Networked z fusions save volume of size ∼d3 when moving logical qubits between neighboring sites and support routing between spatially separated logic units.Non-local connections also avoid wasted packing space for differently shaped storage and magic-state-distillation units.Source: Figure 11 · p. 15, C. Modified connectivity to improve… · p. 15

Unconventional geometries

  • Switchable connections enable stellated n-gon patches, including an n = 10, d = 9 example, by selecting fusion partners and 1- versus (n −1)-delays.The construction produces slices in n RSG cycles and uses a triangular module arrangement plus a backbone module.Source: C. Modified connectivity to improve… · pp. 15–16, Figure 12 · p. 16
  • Layered interleaving facilitates efficient encoding in stellated patches that are difficult to place on regular two-dimensional physical-qubit lattices.For large n, these patches use d2/2 physical qubits per logical qubit, half the asymptotic count for square patches.Source: C. Modified connectivity to improve… · pp. 15–16

Folded-layer constructions

Synthetic dimensions

D. Hardware considerations

A 1-km fiber-delay interleaving module can generate approximately four distance-35 logical qubits per RSG, while practical hardware must also address delay-induced and additional optical errors. Hybrid matter-based RSGs can simplify scaling by moving adaptive interactions and classical processing away from the matter qubits.

Hardware performance

  • Approximately four distance-35 logical qubits per RSG can be generated using a 1-km fiber delay, equivalent to at least ~5,000 circuit-based physical data qubits.The example assumes 1-ns RSG cycles, 5,000 photons in the fiber, and interleaving ratio L2 = 5000.Source: D. Hardware considerations · p. 18
  • An interleaving ratio of L2 = 5000 changes 1-ns fusion-graph slices into 5-µs slices, still comparable to microsecond surface-code cycles in solid-state architectures.The speed penalty can be reduced by shortening the rastering length or using space-time trade-offs.Source: D. Hardware considerations · p. 18

Practical limitations

  • Fiber loss is only a first-order guide: coupling loss, phase shifts, fiber-length mismatch, and wavepacket-duration constraints also affect practical implementations.Dual-temporal-rail encodings can partly mitigate phase errors, while wavepacket duration must balance mismatch sensitivity against fiber capacity.Source: D. Hardware considerations · p. 18

Hybrid matter-based/photonic architectures

  • Hybrid RSG viability depends on photon-mapping repetition rate, output-photon loss, spectral purity, and related photonic errors.These factors are constrained by the interaction Hamiltonians and operating frequencies of non-photonic devices.Source: D. Hardware considerations · p. 18
  • Hybrid architectures reduce the matter-qubit requirement to repeated generation of small photon-compatible entangled states, with photonic components handling connections, memory, fusions, and decoding.The architecture can remove photonic states from the matter-qubit environment, enabling adaptive interactions and classical processing elsewhere.Source: D. Hardware considerations · p. 18
  • Homogeneous entanglement generation avoids high-throughput classical information flow to and from cold, sensitive matter-qubit locations.Adaptive interactions, decoding, and other intensive classical computation can occur after the photonic state leaves the matter-device environment.Source: D. Hardware considerations · pp. 18–19

IV. CONCLUSION

The paper proposes interleaving modules that use photonic delays to expand the computational Hilbert space while trading logical-operation speed for qubit capacity. It shows scalable fault-tolerant architectures, operation-cost reductions through non-local connections, and extensions to hybrid matter-based systems.

Architecture and scaling

  • A 1-delay, L-delay, and L2-delay interleaving module increases the qubits contributed by one RSG by L2, while reducing logical-operation speed by the same factor.The delays store photons for multiple RSG cycles and provide photonic memory within modular FBQC.Source: §IV · p. 19
  • L2 > 1000 is technologically feasible with kilometer-scale low-loss fiber, giving thousands of stored photons and microsecond surface-code cycles for nanosecond RSGs.An interleaving ratio near 1000 is reported as competitive with solid-state architectures.Source: §IV · p. 19

Logical operations

  • Additional qubits can lower overall computation cost by parallelizing operations or enabling algorithms with lower qubits × operations volume, despite slower logical operations.If these software trade-offs are unavailable, adding modules can increase computational speed.Source: §IV · p. 19
  • Modified and switchable fiber connections can reduce logical-operation costs and support geometries beyond strict two-dimensional nearest-neighbor layouts.The paper presents these connections as a toolbox for further architectural improvements.Source: §IV · p. 19

Hybrid architectures

  • Interleaving can scale hybrid matter-based systems by connecting disconnected few-qubit devices to photonic memory, long-distance links, and fault-tolerant processing.The matter devices repeatedly generate identical few-qubit resource states, while photonic components provide the large-scale connectivity and memory.Source: §IV · p. 19

1. 6-ring fusion network

The 6-ring fusion network is represented through a syndrome graph related to a cubic cell-complex orientation, then tiled with periodic boundary conditions to model surface-code behavior. Its logical structure is determined by non-trivial cycles crossing periodic boundaries.

Network representation

  • The studied 6-ring fusion network is arranged on a cubic lattice, with one resource state per cubic cell and a syndrome graph whose colored edges represent fusion outcomes.The paper maps its orientation to the cell-complex orientation used in Ref. [1].Source: §1 · p. 19, Figure 16 · p. 20

Simulation geometry

  • Simulations tile the repeating syndrome-graph unit cell into an L × L × L structure with periodic boundary conditions.The construction contains one logical membrane in each of the three periodic dimensions on both primal and dual lattices.Source: §1 · p. 20
  • A logical error occurs when an error chain crosses the syndrome graph and a periodic boundary, forming a non-trivial cycle.This criterion identifies logical failure in the simulated primal or dual lattice.Source: §1 · p. 20

2. Linear optical fusion

Linear-optical fusion is a probabilistic Bell measurement with three outcomes: success, failure, or photon loss. The boosted type-II implementation combines fusion failure with baseline and interleaving-fiber loss to determine measurement erasure.

Fusion outcomes

  • A successful fusion performs the intended Bell-stabilizer measurements X1X2 and Z1Z2 with probability 1 − pfail.The operation is a probabilistic Bell measurement on the two input photons.Source: §2 · p. 20
  • A failed fusion performs separable single-qubit measurements, allowing one desired stabilizer outcome to be reconstructed from two single-qubit outcomes.The implementation randomizes failures so X1X2 and Z1Z2 are measured with equal probability.Source: §2 · p. 20
  • Photon loss yields neither intended stabilizer outcome because the fusion detects the wrong photon number.Loss therefore differs from fusion failure, which still provides one reconstructible stabilizer outcome.Source: §2 · p. 20

Boosted fusion model

  • The boosted type-II fusion uses an ancillary Bell pair, has pfail = 1/4, and succeeds only when all four photons survive their relevant losses.Its success probability is ηf = (1 − pinterleaved)(1 − pbaseline)^3.Source: §2 · p. 20
  • The physical fusion measurement erasure probability combines the intrinsic fusion-failure contribution with baseline and interleaving-fiber photon loss.The interleaving loss depends on the number of time bins traversed in the delay.Source: §2 · p. 20

3. Encoded fusion erasure probability

The paper uses four-qubit Shor encodings and randomized code variants to reduce encoded fusion erasure probabilities, then numerically estimates loss thresholds for interleaved fusion networks. The simulations model photon loss, syndrome decoding, logical errors, and threshold crossings across delay lengths.

3. Encoded fusion erasure probability

  • Encoded fusion uses four-qubit Shor codes C1 and C2, with stabilizers arranged as complementary X- and Z-repetition structures.C1 places X repetition above Z, while C2 places Z repetition above X.Source: §3 · p. 20
  • Randomly choosing C1 or C2 makes the average encoded fusion erasure probabilities uniform across the two fusion outcomes.For C1, the XAXB and ZAZB erasure probabilities are [1 −(1 −p0)2]2 and 1 −(1 −p2 0)2, respectively; C2 swaps them.Source: §3 · p. 20
  • penc < p0 when p0 < 0.5, establishing lower encoded-fusion erasure than the underlying physical erasure in that regime.Source: §3 · p. 21

4. Numerical methods

  • The numerical error model applies independent photon loss from state preparation and interleaving-fiber propagation across six resource-state qubits with delays N1−6 = {0, 0, 0, 1, L, L2}.Encoded fusion erasure probabilities are then calculated for the relevant delay lengths.Source: §4 · p. 21
  • Logical-error rates are estimated by sampling erasures on primal and dual syndrome graphs, decoding them with union-find, and repeating at least 15,000 trials per parameter combination.A logical error is counted when either graph has an error in any periodic dimension.Source: §4 · p. 21
  • Thresholds are obtained by sweeping pbaseline at fixed delay length L and fitting logical-error curves to a rescaled, shifted beta-distribution CDF.The curve crossing estimates the threshold for each fixed L; repeating this over delay lengths produces the threshold-versus-delay data.Source: §4 · p. 21
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