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Fault-tolerant operation of a logical qubit in a diamond quantum processor
M. H. Abobeih, Y. Wang, J. Randall, S. J. H. Loenen, C. E. Bradley, M. Markham, D. J. Twitchen, B. M. Terhal, T. H. Taminiau
TL;DR
Large-scale quantum computation requires fault-tolerant logical qubits that remain reliable despite noisy operations, but this capability had not been demonstrated on a logical qubit in diamond. The paper uses a seven-spin-qubit implementation of the 5-qubit code with flag-based fault-tolerant protocols, demonstrating logical encoding, Clifford gates, and flagged stabilizer measurements; the measured average fidelity in an additional flagged-measurement test is 0.79(1).
Problem
Large-scale quantum computers and networks require error-corrected logical qubits operated fault-tolerantly despite noisy operations.
Method
The experiment uses the 5-qubit code with an ancilla and flag qubit, implementing repeated-measurement logical encoding, fault-tolerant Clifford gates, and flagged stabilizer measurements.
Results
0.79(1) average fidelity was obtained in an additional flagged stabilizer-measurement test.
Takeaways & Limitations
The work realizes fault-tolerant logical-qubit protocols in a diamond quantum processor, including a primitive for fault-tolerant quantum error correction.
Abstract
from arXiv · showhide
Solid-state spin qubits are a promising platform for quantum computation and quantum networks. Recent experiments have demonstrated high-quality control over multi-qubit systems, elementary quantum algorithms and non-fault-tolerant error correction. Large-scale systems will require using error-corrected logical qubits that are operated fault-tolerantly, so that reliable computation is possible despite noisy operations. Overcoming imperfections in this way remains a major outstanding challenge for quantum science. Here, we demonstrate fault-tolerant operations on a logical qubit using spin qubits in diamond. Our approach is based on the 5-qubit code with a recently discovered flag protocol that enables fault-tolerance using a total of seven qubits. We encode the logical qubit using a novel protocol based on repeated multi-qubit measurements and show that it outperforms non-fault-tolerant encoding schemes. We then fault-tolerantly manipulate the logical qubit through a complete set of single-qubit Clifford gates. Finally, we demonstrate flagged stabilizer measurements with real-time processing of the outcomes. Such measurements are a primitive for fault-tolerant quantum error correction. While future improvements in fidelity and the number of qubits will be required, our realization of fault-tolerant protocols on the logical-qubit level is a key step towards large-scale quantum information processing based on solid-state spins.
Supplementary Information for “Fault-tolerant operation of a logical
This section is identified as supplementary information for the paper “Fault-tolerant operation of a logical qubit in a diamond quantum processor.”
- The supplementary material accompanies the paper “Fault-tolerant operation of a logical qubit in a diamond quantum processor.”
- The document concerns fault-tolerant operation of a logical qubit.
- The research setting is a diamond quantum processor.
I. SYSTEM HAMILTONIAN
The NV processor is modeled with separate electron, nitrogen, carbon, and interaction Hamiltonians, including electron–nuclear and nuclear–nuclear couplings.
- The total Hamiltonian combines electron, nitrogen, carbon, electron–nitrogen, electron–carbon, and nuclear–nuclear terms.These terms are denoted He, HN, HC, HeN, HeC, and HCC.
- Electron spin: The NV electron is a spin-1 system whose ms = 0 and ms = ±1 states are split by the zero-field splitting.An external magnetic field of ∼403 G lifts the degeneracy of the ms = ±1 states, and the electron-spin qubit uses ms = 0 and ms = −1.
- Nuclear spins and interactions: The nitrogen and carbon nuclear spins interact with the electron through hyperfine couplings, while carbon spins also have weak dipolar couplings to one another.Under the secular approximation, the electron–carbon and electron–nitrogen interactions retain longitudinal terms, with an additional transverse electron–carbon component.
- Nuclear spins and interactions: The nuclear-spin data qubits experience weak dipolar interactions characterized by couplings Cij.These couplings are slightly modified by the presence of the electron spin.
II. EXPERIMENTAL SEQUENCE
The experiment uses the NV electron spin as an ancilla and the 14N nuclear spin as a flag ancilla to implement the logical-qubit circuits and their readout.
- The NV electronic spin serves as the ancilla because it supports optical initialization and nondestructive readout and couples to the nuclear spins.It can directly implement two-qubit gates with the 13C and 14N nuclear-spin qubits.
- The sequence prepares the NV and flag qubits, initializes five data qubits by SWAP operations, and performs fault-tolerant logical-state preparation.The preparation measures logical operators, verification operators, and the flag qubit.
- After preparation, the experiment measures a flagged stabilizer and characterizes the resulting state through multi-qubit readout.The required correlation is mapped to the ancilla before optical readout.
- Branches and return arrows represent real-time decisions and feedforward based on measurement outcomes.
A. NV preparation and initialization
NV preparation verifies the negative charge state and laser resonance before optical spin pumping initializes the electron in ms = 0.
- NV preparation: The NV is checked in the negative charge state and on resonance with the initialization and readout lasers.Initialization and readout lasers are applied simultaneously for 150 µs while detected photons are counted against a threshold.
- NV preparation: If the photon count is below threshold, a 515 nm charge-reset laser is applied for 1 ms and the check is repeated.
- NV initialization: The NV electron spin is initialized to ms = 0 by spin pumping on the E1,2 transition with the initialization laser for 100 µs.
B. Two-qubit gates
The processor implements electron–nuclear two-qubit gates with dynamical-decoupling-based native operations. These controlled rotations are equivalent to CNOT gates up to single-qubit rotations.
- Two-qubit gate implementation: Dynamical-decoupling sequences on the NV electron spin implement controlled rotations of targeted 13C nuclear spins.The sequences use equally spaced electron π-pulses and resonance with the selected nuclear spin.
- Two-qubit gate implementation: DD gates require a significant hyperfine-interaction component perpendicular to the applied magnetic field.
- Two-qubit gate implementation: When perpendicular hyperfine coupling is small, DDRF gates interleave dynamical decoupling with resonant radio-frequency pulses.
- Gate equivalence: Both native sequences realize controlled-Rx(±π/2), equivalent to a standard CNOT up to single-qubit rotations.Controlled-Ry(±π/2) is obtained from controlled-Rx(±π/2) by adding phase-shift gates.
C. Initialization and final readout of the data qubits
The data qubits are initialized sequentially after measurement-based initialization of the 14N flag qubit. SWAP sequences transfer the electron’s |0⟩ state onto the five nuclear-spin data qubits.
- Initialization: The 14N nuclear-spin flag qubit is initialized using a measurement-based sequence performed twice to improve initialization fidelity.
- Initialization: The five data qubits are initialized sequentially with SWAP sequences that transfer the electron spin state |0⟩ onto them.An optical pulse resets the electron to |0⟩ after each transfer step.
D. Circuit compilation
The experimental circuits are translated into native gates and compiled to reduce single-qubit-gate overhead. The same compilation strategy is used for encoding and stabilizer-measurement circuits.
- Circuit compilation: All circuits are first translated into the processor’s native gates and then compiled to reduce the total number of single-qubit gates.
- Circuit compilation: The compiled circuit shown for the encoding protocol corresponds to the main-text encoding circuit.
- Circuit compilation: The same native-gate translation and compilation approach is applied to stabilizer measurements on the encoded logical state.
E. Echo sequences for the data qubits
Long circuit durations make nuclear-spin dephasing and unwanted data-qubit couplings important. Echo and asynchronous-echo sequences are used to refocus the spins, protect coherence, and suppress residual couplings.
- Echo design: Spin echoes can extend nuclear-spin coherence times to several seconds and refocus the spins at required circuit points.The design uses two echo stages while minimizing idle time with the electron in a superposition.
- Unwanted couplings: Asynchronous echo sequences suppress non-negligible couplings between data qubits during long experimental sequences.The strongest relevant couplings are C3↔C2 at 16.90(4) Hz and C3↔C5 at 12.96(4) Hz.
- Experimental implementation: Echo stages are inserted between stabilizer measurements to mitigate nuclear-spin decoherence and unwanted couplings.The echoes are applied asynchronously rather than simultaneously to all spins.
III. ADDITIONAL DATA
The supplementary data characterize flagged XXXX measurements and GHZ-state preparation through operator expectation values and fidelity measurements.
- Supplementary Figure 7: 0.79(1) average fidelity is obtained for the flagged XXXX measurement, increasing to 0.82(1) when data are post-selected on no flag.When the flag is raised, fidelity is 0.47(5); the flag is used here only to test the circuit.
- Supplementary Figure 8: The supplementary figures report expectation values for 31 operators defining the encoded state.These measurements correspond to the encoded state prepared using the main-text circuit.
IV. PARAMETERS OF THE NUCLEAR-SPIN QUBITS
The supplementary material specifies nuclear-spin frequencies, couplings, coherence measures, gate parameters, and circuits for flagged stabilizer measurements in the diamond processor.
- Qubit parameters: Precession frequencies are reported for three NV electron-spin projections, alongside hyperfine components parallel and perpendicular to the applied magnetic field.For 14N, the frequencies refer to the mI = 0 ↔ mI = −1 transition and A∥ is derived from (ω+1 −ω−1)/2.
- Coherence times: Coherence-time tables characterize the nuclear-spin qubits using fitted dephasing and dynamical-decoupling measurements.The dynamical-decoupling coherence measure uses α = 256 pulses.
- Gate parameters: Gate parameters include the number and spacing of electron π-pulses, gate type, initialization fidelity, and nuclear-spin gate fidelities.DDRF gates interleave radio-frequency pulses with dynamical decoupling, whereas DD gates do not.
- Qubit couplings: Measured and calculated nuclear-spin coupling strengths are tabulated as CZZ values in hertz.Values without uncertainties are calculated from nuclear-spin coordinates rather than measured directly.
- Flagged correction: Supplementary circuits and tables specify the 5-qubit stabilizers, malicious ancilla faults, flagged-error sets, and corresponding syndromes.The flag outcome changes how the 4-bit syndrome is interpreted and which recovery operation is applied.
V. FLAG FAULT-TOLERANT QUANTUM ERROR CORRECTION
This section defines distance-3 fault tolerance and explains how flag measurements make noisy stabilizer extraction compatible with correction of single-qubit errors.
- Fault-tolerance criteria: A distance-3 code corrects arbitrary single-qubit errors, but practical syndrome extraction must remain reliable when its operations are noisy.Fault-tolerant extraction constrains how errors from the input and a single circuit fault can appear at the output.
- Fault model: A single fault may be any Pauli error inserted during idling, measurement, preparation, or a one- or two-qubit gate.For two-qubit gates, all 15 two-qubit Pauli errors are included; measurement faults produce incorrect outcomes.
- Flag protocol: Flag fault tolerance uses flag-qubit outcomes to correct certain two-qubit errors that can arise during stabilizer measurement.With no flag flip, the output has at most a single-qubit error; a flipped flag identifies a broader correctable-error case.
- Flag-QEC cycle: A complete flag-QEC cycle repeatedly measures stabilizers with and without flags until the logical error is unambiguously identified.The conditional protocol follows the flow chart proposed by Chao and Reichardt.
A. Stabilizer measurement with flag
The experiment prepares a logical |−⟩L state, performs a flagged s1 stabilizer measurement, and evaluates recovery using the flag-conditioned error information.
- Stabilizer measurement: The experiment measures s1 = XXY IY with a flag qubit after preparing the logical state |−⟩L.This measurement is a primitive of the proposed flag-QEC protocol.
- Recovery analysis: Logical-state fidelity is calculated after an imagined perfect stabilizer-measurement round that uses flag information to select optimal recoveries.The recovery analysis is applied to the experimentally obtained output state.
- Fault assumptions: The listed flagged errors assume an initially error-free logical state and only one fault during the s1 measurement.Incoming logical errors or multiple circuit faults can produce errors outside the listed set.
- Syndrome interpretation: When the flag is raised, E′ denotes the correctable errors using flag information, whereas E includes all single-qubit Pauli errors without it.The corresponding 4-bit stabilizer syndromes are tabulated separately.
VI. PROOF OF FAULT-TOLERANCE OF THE PREPARATION SCHEME
The proof shows that the verified preparation circuit tolerates any single fault by either rejecting inconsistent outcomes or producing the intended logical state with at most one physical-qubit error. The argument extends across verification faults, preparation faults, alternative basis-state preparations, and Pauli-frame corrections.
- Preparation conditions: The acceptance checks require stabilizer outcomes to match products of logical-operator outcomes and require the flag qubit not to be raised.These conditions are used to establish fault-tolerant preparation of |−⟩L.
- Extensions and implementation: The same fault-tolerance derivation applies to other basis states, compiled transversal logical gates, echo pulses, and different gate decompositions.The experimental protocol additionally conditions on runs with m3 = +1, m4 = +1, and m5 = +1.
- Extensions and implementation: Classical Pauli-frame tracking interprets final measurement outcomes as if noiseless recovery had been applied, using correction rules determined by the measured eigenvalues.The lookup-table corrections are not unique because stabilizers and logical X incarnations leave |−⟩L unchanged up to phase.
- Case A: verification-circuit faults: For a single fault in verification, data-qubit faults either leave at most one physical-qubit error or violate the consistency checks and cause rejection.Single measurement faults and several flagged two-qubit faults likewise cause rejection rather than an undetected multi-qubit error.
- Case A: verification-circuit faults: Flagged two-qubit faults are either detected through the flag or reduce, after logical equivalence, to a single-qubit outgoing error.The proof gives explicit examples in which propagated Pauli errors are equivalent to a logical operator times one physical-qubit Pauli.
- Case B: preparation-circuit faults: For a fault in the preparation circuit, the verification scheme excludes the potentially bad |+⟩L states X4|+⟩L and Z4|+⟩L that could otherwise pass its checks.The proof argues that no single preparation fault can produce either state, while the 5-qubit code's perfect structure reduces higher-weight errors to the relevant cases.