PaperlayerView exact revision on arXiv

Source-linked AI summary

Quantum Computational Advantage via 60-Qubit 24-Cycle Random Circuit Sampling

Qingling Zhu, Sirui Cao, Fusheng Chen, Ming-Cheng Chen, Xiawei Chen, Tung-Hsun Chung, Hui Deng, Yajie Du, Daojin Fan, Ming Gong, Cheng Guo, Chu Guo, Shaojun Guo, Lianchen Han, Linyin Hong, He-Liang Huang, Yong-Heng Huo, Liping Li, Na Li, Shaowei Li, Yuan Li, Futian Liang, Chun Lin, Jin Lin, Haoran Qian, Dan Qiao, Hao Rong, Hong Su, Lihua Sun, Liangyuan Wang, Shiyu Wang, Dachao Wu, Yulin Wu, Yu Xu, Kai Yan, Weifeng Yang, Yang Yang, Yangsen Ye, Jianghan Yin, Chong Ying, Jiale Yu, Chen Zha, Cha Zhang, Haibin Zhang, Kaili Zhang, Yiming Zhang, Han Zhao, Youwei Zhao, Liang Zhou, Chao-Yang Lu, Cheng-Zhi Peng, Xiaobo Zhu, Jian-Wei Pan

arXiv:2109.03494v2quant-ph

TL;DR

Improving classical simulation threatens the durability of quantum computational advantage, motivating continued quantum-hardware upgrades. This work develops Zuchongzhi 2.1 and demonstrates larger-scale random circuit sampling, with a 60-qubit, 24-cycle task that takes about 4.2 hours experimentally but is estimated to require 48,000 years on Summit.

  • Problem

    Classical simulation algorithms and hardware are improving rapidly, challenging whether quantum computational advantage can remain durable.

  • Method

    The authors design and fabricate a 66-qubit two-dimensional superconducting processor with tunable couplers, improve calibration and readout, and perform random circuit sampling with 4-patch calibration.

  • Results

    60-qubit, 24-cycle random circuit sampling is achieved; its classical simulation cost is about 5000 times higher than the hardest Zuchongzhi 2.0 task and would take Summit 48,000 years.

  • Takeaways & Limitations

    Zuchongzhi 2.1 significantly enhances the demonstrated quantum computational advantage over Zuchongzhi 2.0.

  • Takeaways & Limitations

    Uncalibrated coupler square-pulse distortions cause additional errors, leaving circuit fidelity below the value predicted by multiplying individual-operation fidelities.

Abstract

from arXiv · show

To ensure a long-term quantum computational advantage, the quantum hardware should be upgraded to withstand the competition of continuously improved classical algorithms and hardwares. Here, we demonstrate a superconducting quantum computing systems \textit{Zuchongzhi} 2.1, which has 66 qubits in a two-dimensional array in a tunable coupler architecture. The readout fidelity of \textit{Zuchongzhi} 2.1 is considerably improved to an average of 97.74\%. The more powerful quantum processor enables us to achieve larger-scale random quantum circuit sampling, with a system scale of up to 60 qubits and 24 cycles. The achieved sampling task is about 6 orders of magnitude more difficult than that of Sycamore [Nature \textbf{574}, 505 (2019)] in the classic simulation, and 3 orders of magnitude more difficult than the sampling task on \textit{Zuchongzhi} 2.0 [arXiv:2106.14734 (2021)]. The time consumption of classically simulating random circuit sampling experiment using state-of-the-art classical algorithm and supercomputer is extended to tens of thousands of years (about $4.8\times 10^4$ years), while \textit{Zuchongzhi} 2.1 only takes about 4.2 hours, thereby significantly enhancing the quantum computational advantage.

INTRODUCTION

Zuchongzhi 2.1 upgrades a superconducting quantum processor to sustain quantum computational advantage against improving classical simulation. Its 66-qubit hardware and improved fidelities enable 60-qubit, 24-cycle random circuit sampling with substantially higher classical simulation cost.

  • Motivation: Classical simulation algorithms reduced the estimated cost of Sycamore’s 53-qubit, 20-cycle sampling from 10,000 years to about 19 days on Summit.Exact amplitudes for 2 million correlated bitstrings were also computed in 5 days using 60 GPUs.
  • Hardware: Zuchongzhi 2.1 is a 66-qubit two-dimensional superconducting processor with tunable couplers and separate sapphire chips for qubits and control lines.The processor contains 110 couplers, with one coupler providing fixed coupling at about 7.5 MHz.
  • Performance: 97.74% average readout fidelity, 99.84% single-qubit gate fidelity, and 99.40% two-qubit gate fidelity characterize the upgraded processor.For the selected 60 qubits, the average single-qubit readout error is 2.26%, and the highest readout fidelity reaches 99.1%.
  • Experiment: 60-qubit, 24-cycle random circuit sampling is realized experimentally using the upgraded processor.The experiment selects 60 functioning qubits and uses iSWAP-like two-qubit gates with parallel gate calibration.
  • Advantage: The sampling task has an estimated classical computational cost about 6 orders of magnitude and 5000 times higher than the hardest Sycamore and Zuchongzhi 2.0 tasks, respectively.The stronger coupling shortens the iSWAP-like gate duration from about 32 ns to about 24 ns.

60-QUBIT RANDOM CIRCUIT SAMPLING

The experiment implements and verifies large-scale random quantum circuit sampling on up to 60 qubits and 24 cycles, using patch-based calibration and verification circuits. The largest circuits produce statistically significant nonzero XEB fidelity, while their classical simulation is estimated to require extensive computational resources.

  • Circuit design: Each random-circuit cycle applies randomly selected single-qubit gates followed by patterned two-qubit iSWAP-like gates.The two-qubit layer patterns are labeled A, B, C, and D and implemented in the sequence ABCDCDAB.
  • Calibration and verification: 1.09 and 1.13 are the average patch-to-full and elided-to-full fidelity ratios for 15–60-qubit, 10-cycle circuits, supporting both verification circuits.After calibration, the corresponding ratios improve to 1.05 and 1.07 in the reported four-patch results.
  • Experimental results: The measured circuit fidelities fall below predictions from multiplying individual-operation fidelities because the control method introduces additional error.Uncalibrated coupler square-pulse distortion makes iSWAP-like gate parameters slightly inaccurate for shallow circuits.
  • Calibration and verification: 4-patch calibration partitions the full circuit into four non-overlapping patches and uses gradient-based optimization to tune iSWAP-like gate parameters.The method trains each patch from sampled bitstrings and optimizes its gate parameters with a BFGS optimizer.
  • Experimental results: 60-qubit circuits are sampled from 12 to 24 cycles, with patch and elided circuits used to estimate full-circuit performance.Each system size uses 12 randomly generated circuit instances.
  • Experimental results: 3.66 × 10^-4 is the combined linear XEB fidelity for twelve 60-qubit, 24-cycle elided-circuit instances, with null uniform sampling rejected above 10σ.Approximately 7.0 × 10^7 bitstrings are collected for each circuit instance.

COMPUTATIONAL COST ESTIMATION

The authors estimate the classical cost of reproducing the largest 60-qubit, 24-cycle random-circuit sampling task using a state-of-the-art tensor-network algorithm. They compare this cost with prior processors and the experiment’s runtime.

  • 1.63×10^18 floating-point operations are estimated to generate one perfect sample from the 60-qubit, 24-cycle circuit.
  • 1.10×10^22 floating-point operations are estimated to reproduce the same sampling results.
  • The task is about 6 orders of magnitude harder to simulate than Sycamore’s hardest task and 5000 times harder than Zuchongzhi 2.0’s.
  • Zuchongzhi 2.1 completes the 60-qubit, 24-cycle sampling task in 4.2 hours, whereas Summit would require 48,000 years to simulate it.

CONCLUSION

Zuchongzhi 2.1 achieves larger-scale random quantum circuit sampling with 60 qubits and 24 cycles, substantially increasing the estimated classical simulation difficulty over Zuchongzhi 2.0. The authors identify future applications beyond abstract sampling.

  • Zuchongzhi 2.1 achieves random quantum circuit sampling with 60 qubits and 24 cycles, corresponding to a Hilbert-space dimension up to 2^60.
  • The sampling task is about 5000 times more difficult to simulate classically than the Zuchongzhi 2.0 task.
  • Future work will investigate practical applications of random circuits on NISQ devices, including certified random bits, error correction, and hydrodynamics simulation.

Supplemental Material for “Quantum Computational Advantage via 60-Qubit 24-Cycle Random Circuit Sampling”

The supplemental material lists relevant Zuchongzhi 2.1 results while referring readers to earlier work for detailed calibration and analysis methods. It describes the processor’s programmable architecture and tunable couplers.

  • The supplemental material lists Zuchongzhi 2.1 results without repeating detailed methods described in the Zuchongzhi 2.0 reference.
  • The device is a 66-qubit superconducting programmable processor built from Transmon qubits and tunable couplers.
  • Each tunable coupler can turn off idle qubit-qubit coupling and turn it on for two-qubit gates, with an experimental coupling strength of about −14 MHz.

II. EXPERIMENTAL WIRING

The experimental setup combines cryogenic control and multiplexed readout hardware with calibration procedures for qubit coherence, readout, pulse distortion, and gate performance. The setup operates at 20 mK with dedicated room-temperature electronics.

  • EXPERIMENTAL WIRING: All experiments are performed in a dilution refrigerator at a base temperature of 20 mK with magnetic-field shielding.
  • Calibration: The processor calibration includes measurements of T1, T2* near idle frequencies, XY crosstalk, and adaptive adjustment of idle-frequency distributions.
  • Readout: Readout fidelity is measured using prepared all-zero and all-one states, while driving qubits from |1⟩ to |2⟩ reduces energy-relaxation effects before readout.
  • Pulse calibration: Ramsey testing measures Z-control pulse distortion, after which square pulses are calibrated to mitigate frequency and coupling variations during operation.
  • Gate calibration: Single- and two-qubit gate performance is benchmarked using XEB, including effects from TLS, pulse distortion, decoherence, and residual coupling.

3. Two-Qubit Gate Calibration

The experiment calibrates iSWAP-like gates by tuning near-neighbor qubits into resonance and benchmarking them with two-qubit XEB. Simultaneous operation introduces additional error mainly from residual coupling, while calibrated gates achieve near-90° swap angles and 10° conditional phases.

  • 24 ns iSWAP-like gates are calibrated by tuning near-neighbor qubits into resonance and adjusting coupling strength and detuning toward swap angles near π/2.The calibration accounts for leakage to the non-computational basis.
  • Two-qubit XEB benchmarks calibrated gate performance by optimizing the parameters θ, φ, ∆+, ∆−, and ∆−,off.The analysis also considers errors from two-level systems, pulse distortion, decoherence, and residual nearest-neighbor coupling.
  • Simultaneous two-qubit manipulation produces larger SPB error than isolated operation, mainly because of residual coupling strength.XEB error remains close to SPB error in both isolated and simultaneous cases, indicating small control error.
  • The 99 iSWAP-like gates have an average swap angle of 90 degrees and an average conditional phase of 10 degrees.

C. 4-patch calibration

The 4-patch calibration method addresses shallow-circuit inaccuracies and the difficulty of evaluating full 60-qubit XEB by independently optimizing four non-overlapping circuit patches. The calibrated parameters substantially improve 10-cycle XEB fidelities across systems from 15 to 60 qubits.

  • C. 4-patch calibration: Square-pulse distortion changes qubit frequency and coupling strength during operation, making XEB-fitted iSWAP parameters slightly inaccurate for shallow circuits.The coupler square pulses are not calibrated, while the gate parameters are fitted using circuits with 10–500 cycles.
  • C. 4-patch calibration: The loss function is minimized with classical autodifferentiation and BFGS, using experimentally generated bitstrings as training data and two-qubit-XEB parameters as initialization.
  • C. 4-patch calibration: Full-circuit XEB is extremely difficult to evaluate for 60 qubits, motivating a patch-based optimization strategy.
  • C. 4-patch calibration: The method divides the full circuit into four non-overlapping patches covering all iSWAP gates, then optimizes each patch’s parameters with experimentally generated depth-24 training data.
  • C. 4-patch calibration: 4-patch calibration greatly improves 10-cycle XEB fidelities for circuits containing 15–60 qubits.The optimized coupling-related parameters θ and φ change slightly after calibration.

V. XEB RESULT ANALYSIS

The analysis validates circuit-performance estimation by comparing patch and elided circuits with full circuits and tests measured bitstring probabilities against a theoretical distribution. These checks show close fidelity ratios and consistency with the experimentally estimated fidelity.

  • Patch and elided circuits are compared with full circuits to evaluate the circuit-performance estimation method.
  • For a 60-qubit 24-cycle elided circuit, the scaled bitstring-probability distribution is tested against the theoretical probability density function.The scaled probability is defined as x ≡ Dp.
  • The Kolmogorov–Smirnov test gives p = 0.77 for F = F̂ and p = 8.0 × 10^-4 for F = 0 in one circuit instance.

B C D

The study evaluates 60-qubit, 24-cycle random-circuit samples using verification circuits, bootstrap uncertainty estimates, and classical simulation-cost methods. The combined analysis reports an aggregate XEB fidelity and uses tensor-network contraction to estimate classical cost.

  • B C D: The 60-qubit 24-cycle bitstring-probability distribution is compared with a theoretical curve scaled by Ns = 7 × 10^7 samples.
  • B C D: Bootstrap analysis uses 2500 samples to estimate the statistical uncertainty of XEB for a 60-qubit 24-cycle elided circuit.The estimated uncertainties from the formula, bootstrap, and Gaussian fit are 1.20, 1.19, and 1.21 × 10^-4, respectively.
  • B C D: The inverse-variance-weighted fidelity across twelve 60-qubit 24-cycle elided circuits is F̂_l = (3.66 ± 0.35) × 10^-4.This result is compared with a theoretical statistical uncertainty of 3.5 × 10^-5.
  • B C D: Tensor network contraction and Schrödinger–Feynman algorithms estimate the classical computational cost, with tensor network contraction more efficient for this system size.

A. Tensor network contraction

Tensor-network contraction estimates the classical cost of reproducing the 60-qubit random-circuit samples, while SFA estimates account for circuit cuts and gate imbalance. The 60-qubit, 24-cycle circuit requires substantially greater estimated resources than the compared circuits, although imbalance can accelerate classical simulation.

  • Tensor network contraction: 4.68 × 10^23 floating point operations are estimated to generate one perfect sample from the 60-qubit, 24-cycle circuit.The estimate uses cotengra with 21 open qubits, a largest intermediate tensor size of 230, and the kahypar optimizer, repeated about 100 times.
  • Tensor network contraction: 4.8 × 10^4 years is the estimated Summit time to reproduce the 53-qubit, 20-cycle and 60-qubit, 24-cycle results under the stated cost model.The estimate combines the contraction cost, Summit timing, and the 0.0366% fidelity factor.
  • SFA estimates: SFA cost estimates use promising circuit cuts for the 60-qubit, 22-cycle and 24-cycle circuits and the simulator and server from Ref..The supplemental comparison also includes estimates for Sycamore and Zuchongzhi 2.0 circuits.
  • SFA estimates: Imbalanced iSWAP-like gates can accelerate SFA simulation, and the analysis omits DCD formation from its estimate.The experiment uses θ ≈ π/2 and φ ≈ π/18 as expected gate values; deviations are treated as sources of imbalance.
Loading 2109.03494v2…