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Cryogenic Memory Technologies

Shamiul Alam, Md Shafayat Hossain, Srivatsa Rangachar Srinivasa, Ahmedullah Aziz

arXiv:2111.09436v2cs.ETphysics.app-ph

TL;DR

Scalable quantum computers and practical SFQ systems lack compatible cryogenic memory, a need also relevant to space electronics. This review surveys non-superconducting, superconducting, and hybrid memory technologies and their challenges. It highlights 4 K compatibility and capacity as important trade-offs among candidate approaches.

  • Problem

    Scalable quantum computers and practical SFQ systems face a lack of suitable, compatible cryogenic memory.

    Source: §1 · p. 1

  • Method

    The review surveys cryogenic memory efforts across non-superconducting, superconducting, and hybrid technologies and discusses their integration challenges.

    Source: §1 · p. 2, §5 · p. 15

  • Results

    SIS JJ- and SQUID-based memories are attractive for 4 K compatibility, but implementing high-capacity systems remains a challenge; magnetic JJ and hybrid variants may help scalability but face challenges.

    Source: §4 · p. 14

  • Takeaways & Limitations

    The review identifies memory capacity and integration constraints as unresolved considerations when assessing cryogenic memory options for quantum computers and SFQ systems.

    Source: 3.B. Superconducting Memories · p. 9, §4 · p. 14

    Flux trapping limits integration density in JJ- and SQUID-based memories, and large-scale energy efficiency remains an issue.

    Source: 3.B. Superconducting Memories · p. 9

Abstract

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The surging interest in quantum computing, space electronics, and superconducting circuits has led to new developments in cryogenic data storage technology. Quantum computers promise to far extend our processing capabilities and may allow solving currently intractable computational challenges. Even with the advent of the quantum computing era, ultra-fast and energy-efficient classical computing systems are still in high demand. One of the classical platforms that can achieve this dream combination is superconducting single flux quantum (SFQ) electronics. A major roadblock towards implementing scalable quantum computers and practical SFQ circuits is the lack of suitable and compatible cryogenic memory that can operate at 4 Kelvin (or lower) temperature. Cryogenic memory is also critically important in space-based applications. A multitude of device technologies have already been explored to find suitable candidates for cryogenic data storage. Here, we review the existing and emerging variants of cryogenic memory technologies. To ensure an organized discussion, we categorize the family of cryogenic memory platforms into three types: superconducting, non-superconducting, and hybrid. We scrutinize the challenges associated with these technologies and discuss their future prospects.

1. Introduction

Cryogenic memory is presented as a key missing component for scalable quantum computers and practical SFQ systems, while space electronics are another potential application. The review surveys memory technologies, their challenges, and their prospects.

1. Introduction

  • SFQ circuits offer faster, more energy-efficient operation than CMOS, but compatible fast, low-power, high-density cryogenic memory remains a challenge for practical systems.The review also identifies cryogenic memory as a major challenge for scalable quantum computers.Source: §1 · p. 1
  • The review organizes cryogenic memories into non-superconducting, superconducting, and hybrid approaches, and examines their challenges and prospects.The approaches include charge- and resistance-based memories, JJ- and SQUID-based memories, and designs combining both technologies.Source: §1 · p. 2

2. Why Cryogenic Memory?

  • Moving quantum-computer control from room temperature toward the 4 K qubits could reduce wiring demands, but requires memory compatible with the cryogenic processor.Room-temperature connections create thermal leakage and noise; the passage says this can destroy noise-sensitive qubit states.Source: §2 · pp. 2–3
  • Higher-temperature memory can reduce cooling costs: cooling to 4 K is ≃ 200 times costlier than room-temperature memory, though warmer placement may add thermal leakage.The review identifies 77 K as a lower-cost alternative to 4 K memory.Source: §2 · p. 3
  • SFQ systems need nearby 4 K memory to retain the lower power and latency associated with physical proximity; a lack of scalable, compatible memory has limited them to niche applications.Figure 1 also illustrates possible memory placements at 4 K, 77 K, and 300 K.Source: Figure 1 · p. 2, §2 · p. 3

3. Overview of State-of-the-art Cryogenic Memories

The review surveys cryogenic memory architectures and identifies non-superconducting memories as mature, high-capacity candidates. Their operation at lower temperatures can improve performance, but temperature choice involves cost and scaling trade-offs.

3. Overview of State-of-the-art Cryogenic Memories

  • Cryogenic memory architectures span charge- and resistance-based non-superconducting devices, JJ- and SQUID-based superconducting devices, and hybrid combinations.The review presents this as its organizing taxonomy for state-of-the-art approaches.Source: §3 · p. 3

3.A. Cryogenic Non-Superconducting Memories

  • Non-superconducting memories are described as technologically mature and capable of high storage capacity, while their speed and power demand can lag a 4 K control processor.The review divides them into charge-based and resistance-based families.Source: 3.A. Cryogenic Non-Superconducting… · pp. 3–4
  • 40%–50% higher speed and 30% lower power dissipation were reported for digital circuits at 4 K than at room temperature, depending on circuit operation.The cited work concerns devices and circuits manufactured using several sub-micron CMOS processes.Source: 3.A. Cryogenic Non-Superconducting… · p. 3
  • Memory at 77/120 K can reduce cooling costs and improve CMOS operation, but numerous connections to a 4 K processor can limit scaling through thermal loss.The passage says these temperatures are within the ideal operating range for CMOS devices and may suit smaller quantum computers.Source: 3.A. Cryogenic Non-Superconducting… · p. 4

3.A.1. Charge-based Memories

Charge-based memories store data through capacitor states, and the review discusses both capacitor-based and capacitorless DRAM. Cryogenic operation has been explored for DRAM devices, with reported performance gains and practical integration constraints.

3.A.1.1. 1-Transistor 1-Capacitor (1T1C) DRAMs

  • 1T1C DRAMs are considered candidates because of their maturity, high storage capacity, and expected low-temperature benefits, including reduced refresh power and switching energy.Reduced junction leakage and increased carrier mobility are described as mechanisms behind the expected improvements.Source: 3.A.1.1. 1-Transistor 1-Capacitor… · p. 4
  • 55 DIMMs containing 750 DRAM chips from six vendors were tested from 80 K to 160 K; many chips worked, and observed errors were described as correctable with conventional schemes.The cited study reports mainly transient and permanent errors and identifies forward error correction approaches including Chipkill and sparing.Source: 3.A.1.1. 1-Transistor 1-Capacitor… · p. 4
  • 77 K DRAMs reportedly operated without functional errors, but connecting them to a 4 K processor requires a low-thermal-conductivity interface.The cited work identifies a flexible cable as one such interface.Source: 3.A.1.1. 1-Transistor 1-Capacitor… · p. 4
  • At 4 K, 3T DRAM was reported to improve speed by 40% and reduce power consumption by 30% versus 300 K; it also uses simpler peripheral circuitry for read/write.The characterization was performed for a hybrid Josephson-CMOS memory implementation.Source: 3.A.1.1. 1-Transistor 1-Capacitor… · p. 4
  • Figure 2 contrasts capacitor-based 1T1C storage with parasitic-capacitance storage in 3T DRAM and depicts a floating-body transistor used for capacitorless DRAM.Its temperature plots concern retention time and current sense margin, which the caption says improve at lower temperatures.Source: Figure 2 · p. 5

3.A.1.2. Capacitorless 1-Transistor (1T) DRAMs

The section presents capacitorless 1T-DRAM as a scalable, high-capacity cryogenic-memory candidate and describes resistance-based memories through their two-state hysteretic behavior. At 80 K, a demonstrated 1T-DRAM showed longer dynamic retention and a larger current sense margin than at 300 K.

3.A.1.2. Capacitorless 1-Transistor (1T) DRAMs

  • Capacitorless 1T-DRAM is presented as a scalable, high-capacity candidate for cryogenic memory, with low temperature reducing carrier generation and recombination.The passage identifies carrier generation and recombination as a major retention-failure mechanism in 1T-DRAM cells.Source: 3.A.1.2. Capacitorless 1-Transistor… · p. 5
  • At 80 K, the 1T-DRAM achieved 10^4 times longer dynamic retention time and 2.5 times larger current sense margin than at 300 K.The demonstrated cell used a partially depleted silicon-on-insulator n-MOSFET with a floating body and operated over a reported temperature range of 380 K to 80 K.Source: 3.A.1.2. Capacitorless 1-Transistor… · p. 5

3.A.2. Resistance-based Memories

  • Resistance-based memories use high- and low-resistance states to encode data, and Fig. 3 depicts structures and hysteretic characteristics for several memory types.The examples include memristive, ferroelectric, spintronic, and QAHE-based memories.Source: 3.A.2. Resistance-based Memories · p. 5, Figure 3 · p. 6

3.A.2.1. Memristive Memories

The section reviews HfO2-based ReRAM as a candidate for cryogenic storage and compares its behavior across devices and temperatures. It also summarizes ferroelectric memory architectures, low-temperature material studies, and the readout and voltage trade-offs reported for FeCap and FeFET.

3.A.2.1. Memristive Memories

  • HfOx-based ReRAM devices have demonstrated resistive switching down to 4 K, but their resistance and temperature dependence vary across device structures.Reported changes include increased resistance in both states for some devices, little significant switching change in another, and improved ROFF/RON at lower temperatures at the cost of larger set/reset voltages.Source: 3.A.2.1. Memristive Memories · p. 6

3.A.2.2. Ferroelectric Memories

  • FeCap memories use a ferroelectric layer for non-volatility and offer nanosecond-range switching, endurance of about 10^10 to 10^14 cycles, and retention beyond 10 years, but have destructive readout.The passage distinguishes FeCap 1T–1C cells from FeFET-based 1T memories.Source: 3.A.2.2. Ferroelectric Memories · pp. 6–7
  • FeFETs avoid destructive readout through separate read and write paths, and a Si:HfO2 n-type device study down to 6.9 K reported a larger memory window alongside higher program/erase voltage as temperature fell.The reported program/erase time is approximately nanoseconds.Source: 3.A.2.2. Ferroelectric Memories · p. 7
  • Low-temperature ferroelectric studies found material-dependent changes: coercive field rose in PbZr0.5Ti0.5O3 films and fell in antiferroelectric zirconia, motivating design trade-offs.The studied materials included samples characterized down to 4 K and 50 mK; saturation and remnant polarization also increased in the PbZr0.5Ti0.5O3 films at low temperatures.Source: 3.A.2.2. Ferroelectric Memories · p. 7

3.A.2.3. Spintronic Memories

The section describes cryogenic MRAM studies and other resistance-based approaches, including QAHE-based and phase-change memories. Reported demonstrations span low-temperature spintronic switching, nanoampere-level QAHE memory operation, and phase-change resistive states.

3.A.2.3. Spintronic Memories

  • At 9 K, a CoFeB/MgO MTJ showed reliable switching with error rate below 10^-4 and endurance above 10^12 cycles; a CoFeB orthogonal spin-transfer device switched in about 200 ps at 4 K.The orthogonal device's low write error rate was limited to a pulse condition and it had low magnetoresistance; toggle MRAM was also operated at 4.2 K with enhanced magnetoresistance.Source: 3.A.2.3. Spintronic Memories · p. 7

3.A.2.4. Other resistance-based Memories

  • QAHE memory uses quantized Hall-resistance states in twisted bilayer graphene to define memory states and supports write and read with nanoampere-level bias currents.The cited proposal describes this as an attractive route to ultra-low-power, highly scalable cryogenic memory.Source: 3.A.2.4. Other resistance-based Memories · p. 7
  • In (La, Pr, Ca)MnO3, resistance hysteresis was observed up to 10 K, with stable resistive states that could be switched repeatedly using voltage pulses.The passage identifies this behavior as a basis for a fast, non-volatile, scalable cryogenic phase-change memory.Source: 3.A.2.4. Other resistance-based Memories · pp. 7–8

3.B. Superconducting Memories

SIS JJ- and SQUID-based memories offer compatibility with superconducting SFQ systems but face low capacity and large-scale energy-efficiency challenges. The section also identifies flux trapping as an integration constraint and presents fabrication advances and alternative memory approaches as possible paths forward.

3.B. Superconducting Memories

  • SIS JJ- and SQUID-based memories face low storage capacity from large cell area, transformer-coupled address lines, and flux trapping, while large-scale energy efficiency is also a concern.The passage contrasts these limits with non-superconducting memories, which can scale well but have higher power demand and lower speed than SFQ systems.Source: 3.B. Superconducting Memories · pp. 8–9
  • Trapped flux can penetrate JJs or couple to magneto-sensitive gates; shielding alone is insufficient, and reserving chip space around frozen vortices limits integration density.The passage notes fabrication of circuits with over 7 × 10^4 JJs on a 5 × 5 mm2 chip as a development that may support scalable JJ-based memory.Source: 3.B. Superconducting Memories · p. 9
  • The review distinguishes SIS JJ-, magnetic JJ-, superconducting memristor-, and ferroelectric SQUID-based memories, while Fig. 4 traces SIS JJ memory development and compares performance metrics.The figure includes schematics of several SIS JJ memory-cell designs.Source: Figure 4 · p. 9, 3.B. Superconducting Memories · p. 10

3.B.1. SIS JJ-based Memories

SIS JJ-based memories offer ultrahigh speed and low power, but their scalability remains a major concern. Designs progress from vortex-transition and SQUID cells to multi-state cells, with demonstrations reaching 16 kbit.

3.B.1. SIS JJ-based Memories

  • A revised vortex-transition design reduced the Nb-layer count from three to two and supported a demonstrated 16 kbit RAM in four 4 kbit blocks.Earlier vortex-transition RAM demonstrations reached 4 kbit; a pipelined DC-powered structure was later proposed for the 16 kbit memory.Source: 3.B.1. SIS JJ-based Memories · p. 10
  • SQUID-based nondestructive-readout cells supported a 2 kbit RAM and used three sense gates to address the half-select problem.The earlier vortex-transition cell used one sense gate.Source: 3.B.1. SIS JJ-based Memories · p. 10
  • Polonsky et al. 80 proposed serial single-junction SQUIDs on bit lines, inductively coupled to word lines, with write and read operations driven by directional pulses.Source: 3.B.1. SIS JJ-based Memories · p. 10
  • Nair et al. 88,89 developed a three-state cell demonstrated in 2019 90; one sensing mechanism gives a half-destructive read, while weaker pulses enable nondestructive readout 91,92.Source: 3.B.1. SIS JJ-based Memories · p. 10
  • SIS JJ memories combine ultrahigh speed and low power with a major scalability concern; performance comparisons cover cell area, access time, capacity, and power.The cited figures compare notable designs, but the supplied passages give no individual comparison values.Source: 3.B.1. SIS JJ-based Memories · p. 10

3.B.2. Magnetic JJ-based Memories

Magnetic Josephson junctions store data through magnetic-field-dependent critical-current states and can be integrated with SIS junctions. The section describes approaches to improve switching speed and capacity, alongside material-selection and array-design challenges.

3.B.2. Magnetic JJ-based Memories

  • A ferromagnetic layer produces hysteretic critical-current dependence on external field, enabling high- and low-current states that can be changed nonvolatily by a small control current.MJJs share a fabrication process with SIS JJs, supporting integration on one chip.Source: 3.B.2. Magnetic JJ-based Memories · pp. 10–11
  • MJJ switching speed depends on control-line inductance and the SFS junction's intrinsic switching time; Ryazanov et al. 96 demonstrated an SFS junction as a Josephson magnetic switch.Source: 3.B.2. Magnetic JJ-based Memories · p. 11
  • SI(S)FS junctions reached a maximum characteristic voltage of ~700 µV, implying ~200 GHz switching while retaining magnetic-memory properties.Adding an insulator raises characteristic voltage over SFS junctions; a further superconducting layer increased it further.Source: 3.B.2. Magnetic JJ-based Memories · p. 12
  • Spin-valve JJs tune ground-state phase difference and critical current through ferromagnetic-layer orientation, and Bell et al. demonstrated spin-valve JJ-based cryogenic memory 113.Source: 3.B.2. Magnetic JJ-based Memories · p. 12
  • Quantized Abrikosov-vortex cells offer attojoule-order write energy, non-volatility, and nanometer scaling, but smaller structures require magnetic fields of ~1 kOe.Vortices are introduced or removed with positive or negative currents of ~20 µA.Source: 3.B.2. Magnetic JJ-based Memories · p. 12
  • Ferromagnet choice trades lower switching energy and larger characteristic length in weak magnets against their severe critical-current reduction; strong magnets have ξ_F < 1 nm.Low critical current narrows the hysteresis window and makes memory states harder to sense.Source: 3.B.2. Magnetic JJ-based Memories · p. 12
  • Large MJJ arrays remain an unsolved challenge: write fields may disturb neighboring cells, while current-carrying coils lead to slow switching (~milliseconds).Source: 3.B.2. Magnetic JJ-based Memories · p. 12

3.B.3. Superconducting Memristor-based Memory

A conductance-asymmetric SQUID can serve as a superconducting memristor whose resistance states store data. Its array-level implementation has been proposed, but experimental implementation is still awaited.

3.B.3. Superconducting Memristor-based Memory

  • A superconducting memristor can use a conductance-asymmetric SQUID with two parallel SIS junctions, combining memristor scalability with JJ speed and energy efficiency.The junctions are designed for equal critical current but asymmetric conductance.Source: 3.B.3. Superconducting Memristor-based… · p. 12
  • At flux bias Φ = Φ0/2, critical-current effects are suppressed while asymmetric conductance remains, producing a pinched I–V hysteresis whose resistance states define memory.The CA-SQUID dynamics are described with a modified RCSJ model and four shunt paths, including phase-dependent conductance.Source: 3.B.3. Superconducting Memristor-based… · pp. 12–13
  • A superconducting-memristor cell with an hTron access device has been proposed for an array, but experimental implementation awaits.Source: 3.B.3. Superconducting Memristor-based… · p. 13

3.B.4. Ferroelectric-SQUID-based Memory

Ferroelectric-SQUID memory uses voltage-controlled polarization states to alter SQUID critical current and distinguish stored states. Hybrid memories instead pair scalable non-superconducting storage with superconducting access, with feasibility demonstrations and application-specific boundaries described.

3.B.4. Ferroelectric-SQUID-based Memory

  • FeSQUID polarization states produce distinct critical currents; negative polarization yields the higher current, and an intermediate read bias distinguishes the states by zero versus nonzero voltage.Voltage bias writes the nonvolatile polarization states, providing separate read and write paths.Source: 3.B.4. Ferroelectric-SQUID-based Memory · p. 13

3.C. Hybrid Memories

  • The hybrid approach uses scalable memories such as DRAM or MRAM for storage and JJ-based devices for access, aiming to combine capacity with speed and energy efficiency.Figure 6 illustrates this division between storage and access.Source: Figure 6 · p. 13, 3.C. Hybrid Memories · p. 14
  • A 3T DRAM/JJ-access hybrid was demonstrated as a 64 kb (256 × 256) system; other designs used CMOS SRAM at 4 K or three-terminal nano-cryotrons for DRAM access.Source: 3.C. Hybrid Memories · p. 14
  • An SHE-MTJ and hTron demonstrated a 4 × 4 array with 6 picojoules per switching operation, accessed using 100 µA signals compatible with SFQ control circuits.Source: 3.C. Hybrid Memories · p. 14
  • A room-temperature semiconductor memory paired with a 4.2 K RSFQ cache is unsuitable for large-scale quantum computers because of interconnection, but is suited to digital RF receivers.Source: 3.C. Hybrid Memories · p. 14

4. Comparison of Cryogenic Memories: Pros, Cons, Challenges and Future Prospects

Cryogenic memory options trade maturity and capacity against compatibility with fast, energy-efficient superconducting processors. Hybrid approaches may address this trade-off, but interfaces and reliability at varying temperatures remain challenges.

4. Comparison of Cryogenic Memories: Pros, Cons, Challenges and Future Prospects

  • The review compares memory variants against quantum-computing and superconducting-electronics requirements to clarify their advantages, disadvantages, and challenges.Source: §4 · p. 14
  • Non-superconducting memories are mature, scalable, and can operate at 4 K, but their speed and power mismatch with SFQ systems requires CMOS control and creates a large-scale power constraint.The passage notes that CMOS power consumption at large scale cannot be sustained at 4 K.Source: §4 · p. 14
  • SIS JJ and SQUID memories offer 4 K operation and compatibility with control processors, while magnetic JJ memories could address scalability but face material, critical-current, and array-design challenges.The magnetic JJ passage identifies thickness-related fluctuations and severe critical-current depression as material challenges.Source: §4 · p. 14
  • Hybrid memories combine the maturity and capacity of non-superconducting memories with superconducting speed and energy efficiency, but suitable interfaces must avoid added speed or energy bottlenecks.The SHE-MTJ and hTron memory approach is noted as not requiring an interface circuit.Source: §4 · p. 15

5. Conclusion

  • Non-superconducting memories offer maturity and scalability, while JJ-based memories are processor-compatible but less scalable; hybrids combine advantages but still face interface and reliability challenges.Reliability also requires operating well below the superconducting material’s critical temperature, and the effect of temperature fluctuations remains unexplored.Source: §5 · p. 15
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