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DeepGate: Learning Neural Representations of Logic Gates

Min Li, Sadaf Khan, Zhengyuan Shi, Naixing Wang, Yu Huang, Qiang Xu

arXiv:2111.14616v3cs.LGcs.AI

TL;DR

EDA research has not yet addressed how to obtain a general, effective circuit representation that can serve varied tasks. DeepGate learns gate vectors using AIG-transformed circuits, signal-probability supervision, and a circuit-specific GNN; the authors report generalization to large circuits, including a 73.56% prediction error reduction on Arbiter.

  • Problem

    A general, effective neural representation of circuits for varied EDA tasks remains unaddressed, despite existing learning-based EDA solutions.

    Source: §I · p. 1

  • Method

    DeepGate transforms circuits to AIGs and learns gate representations with signal-probability supervision and a dedicated GNN using circuit knowledge as priors.

    Source: §I · p. 2, B. Circuit Data Preparation · p. 3

  • Results

    DeepGate generalizes to large circuits and achieves a 73.56% prediction error reduction on Arbiter.

    Source: §I · p. 2, 2) Results on Large Circuits · p. 6

  • Takeaways & Limitations

    DeepGate learns circuit representations that embed logic functions and structural information as gate vectors, with accurate large-circuit predictions without pre-computed features.

    Source: §V · p. 6

Abstract

from arXiv · show

Applying deep learning (DL) techniques in the electronic design automation (EDA) field has become a trending topic. Most solutions apply well-developed DL models to solve specific EDA problems. While demonstrating promising results, they require careful model tuning for every problem. The fundamental question on "How to obtain a general and effective neural representation of circuits?" has not been answered yet. In this work, we take the first step towards solving this problem. We propose DeepGate, a novel representation learning solution that effectively embeds both logic function and structural information of a circuit as vectors on each gate. Specifically, we propose transforming circuits into unified and-inverter graph format for learning and using signal probabilities as the supervision task in DeepGate. We then introduce a novel graph neural network that uses strong inductive biases in practical circuits as learning priors for signal probability prediction. Our experimental results show the efficacy and generalization capability of DeepGate.

I. INTRODUCTION

Task-specific EDA models map circuit graphs directly to outputs, but general, effective circuit representations for varied EDA tasks remain unaddressed. DeepGate learns gate representations that combine logic and structural information using AIG circuits, signal-probability supervision, and a dedicated GNN.

I. INTRODUCTION

  • DeepGate addresses the open problem of learning general, effective circuit representations, rather than mapping circuit graphs directly to individual EDA-task outputs.The learned gate representations account for both logic computation and circuit structure.Source: §I · p. 1
  • Transforming circuits to AIG form reduces graph heterogeneity to 2-input AND gates and inverters without changing functionality.The authors state that logic synthesis introduces practical-circuit inductive bias for GNN learning.Source: §I · p. 1
  • Signal probability—the probability that a node is logic 1—provides supervision reflecting circuit logic relationships and is obtained through simulation of random input patterns.The paper motivates this target as especially practical for small circuits and useful for analyzing reconvergent structures.Source: §I · p. 1
  • The dedicated circuit GNN uses attention to mimic logic computation, reversed propagation for logic implications, and explicit treatment of reconvergence structures.Reconvergence is described as inevitable under logic sharing and a main challenge for logic analysis.Source: §I · p. 2
  • DeepGate learns gate representations from small subcircuits extracted from benchmark circuits, with experiments on large circuits showing efficacy and generalization.The stated flow combines AIG transformation, logic-simulated probability supervision, and a dedicated graph model.Source: §I · p. 2

II. RELATED WORKS

GNNs learn graph representations through message passing, while DAG-GNN variants respect node order by aggregating predecessor states. Recurrent application of the model yields another DAG-GNN variant.

A. Graph Neural Networks

  • GNN message passing aggregates neighboring-node information to update hidden states, then uses READOUT to form a graph representation.Attention-based aggregation can weight neighbors by importance.Source: A. Graph Neural Networks · p. 2
  • DAG-GNNs aggregate predecessor states in topological order, executing each node’s aggregation after its predecessors’ states are computed.They differ from general GNNs by restricting aggregation to predecessors.Source: A. Graph Neural Networks · p. 2
  • Applying a DAG-GNN recurrently for T iterations produces DAG-RecGNN, alongside DAG-ConvGNN as the non-recurrent variant.The two variants are named using the taxonomy in.Source: A. Graph Neural Networks · p. 2

B. GNN-Based Solutions for EDA Problems

Existing GNN-based EDA methods typically learn task-specific solutions from circuit features or labels, rather than transferable representations that encode circuit logic. DeepGate is proposed to address this gap.

B. GNN-Based Solutions for EDA Problems

  • Existing GNN-based EDA methods use task-specific features and labels, so their learned node features cannot transfer among related tasks.These methods commonly obtain labels from commercial EDA tools.Source: B. GNN-Based Solutions for EDA Problems · pp. 2–3
  • Prior EDA GNNs model circuit structure but ignore logic functions, although effective circuit representations should encode both.Examples include testability classification, congestion prediction, power estimation, and net-length estimation.Source: B. GNN-Based Solutions for EDA Problems · pp. 2–3
  • DeepGate aims to learn general circuit representations without precomputing task-specific features.It is motivated by the transfer limitation of existing task-specific approaches.Source: B. GNN-Based Solutions for EDA Problems · p. 3

III. PROPOSED SOLUTION

DeepGate’s representation-learning pipeline prepares circuits and then trains a circuit-specific GNN to predict node signal probabilities. The learned gate representations are intended to capture circuit structure and logic behavior.

A. Overview of DeepGate

  • Circuit preparation converts designs to unified AIGs and obtains node signal probabilities through logic simulation for supervision.The signal probability is the probability that a node is logic 1.Source: A. Overview of DeepGate · p. 3
  • DeepGate uses the simulated probabilities as a prediction task for a circuit-focused GNN that learns gate representations.The learned representations are intended to encode both structural and logic information.Source: A. Overview of DeepGate · p. 3

B. Circuit Data Preparation

DeepGate standardizes heterogeneous circuit designs as AIGs and supervises learning with simulated node signal probabilities. Its GNN combines recurrent propagation, attention, and reverse-order information to represent circuit structure and logic behavior.

B. Circuit Data Preparation

  • AIG conversion standardizes heterogeneous circuit designs, with large designs reduced to 30–3k-gate subcircuits for training and larger circuits used to test generalization.The designs include RTL circuits and gate-level netlists mapped with different libraries.Source: B. Circuit Data Preparation · p. 3
  • AIG preprocessing limits circuits to 2-input AND and 1-input NOT gates, adds relational inductive bias, and reduces training and supervision-preparation costs.The size constraint facilitates efficient GNN training.Source: B. Circuit Data Preparation · p. 3
  • Signal probability—the probability that a node is logic 1—provides accessible, logic-informative supervision and captures reconvergent structures through simulation.The passage states that logic probability is important in many EDA tasks.Source: B. Circuit Data Preparation · p. 3

C. GNN Model in DeepGate

  • DeepGate predicts each AIG node’s genuine signal probability while learning both circuit structure and computational behavior as gate vectors.Its input uses one-hot gate-type features for primary inputs, AND gates, and NOT gates, rather than probability-based input measurements.Source: C. GNN Model in DeepGate · p. 3
  • Attention aggregation uses the current node representation as a query and predecessor representations as keys, weighting inputs to reflect controlling-value importance.The model is designed to assign greater weights to controlling inputs than non-controlling inputs.Source: C. GNN Model in DeepGate · p. 3
  • Recurrent learning is used because one forward propagation is insufficient to capture circuit function and structure, and recurrence can stabilize node embeddings quickly.The model applies the GNN function repeatedly.Source: C. GNN Model in DeepGate · p. 4
  • Backward propagation in reverse topological order incorporates logic implication and backtracking information that can help predict node states and stabilize training.The stated training-stability rationale is supported by sequence-to-sequence learning tasks.Source: C. GNN Model in DeepGate · p. 4
  • A shared-per-gate-type MLP maps final node states to scalar probability predictions and is trained with L1 loss against simulated probabilities.The regressor operates after T iterations.Source: C. GNN Model in DeepGate · p. 4

D. Skip Connection for Reconvergence Structure with Positional Encoding

DeepGate addresses reconvergence nodes with skip connections that carry information from source fan-out nodes. Positional encodings represent the logic-level distance between those nodes and reconvergence nodes.

D. Skip Connection for Reconvergence Structure with Positional Encoding

  • Reconvergence nodes are a distinct challenge for logic-probability inference because they arise from logic sharing in multi-level networks.DeepGate therefore adds special processing for them.Source: D. Skip Connection for Reconvergence… · p. 4
  • DeepGate records each reconvergence node's source fan-out node and their logic-level difference, then adds a direct skip edge between them.The edge enables information exchange from the source fan-out node to the reconvergence node.Source: D. Skip Connection for Reconvergence… · p. 4
  • A positional encoding of the logic-level distance is assigned to each skip edge and used in coefficient calculation; longer distances generally imply less impact.The encoding maps distance D into alternating sine and cosine components.Source: D. Skip Connection for Reconvergence… · p. 4

A. Datasets

The dataset combines subcircuits from four benchmark suites, transformed into AIGs and labeled with simulated signal probabilities. The evaluation compares GNN baselines using mean absolute prediction error under broadly matched model settings.

A. Datasets

  • Subcircuits from ITC’99, IWLS’05, EPFL, and Open-Core are transformed into AIGs and labeled using simulations of up to 100k random input patterns.The simulations provide signal probabilities for every node.Source: A. Datasets · p. 5
  • The dataset contains 10,824 circuits spanning tens to thousands of nodes and differing logic levels, split 90/10 for training and testing.Table I reports the dataset statistics.Source: A. Datasets · p. 5

B. Evaluation Metric and Baselines

  • Performance is measured by the average absolute difference between simulated and predicted node probabilities, with smaller error indicating better performance.The candidate GNNs are GCN, DAG-ConvGNN, DAG-RecGNN, and DeepGate, tested with four aggregator designs.Source: B. Evaluation Metric and Baselines · p. 5
  • Models use 64-dimensional node states and similar parameter counts; recurrent models use forward and reversed layers with 10 message-passing iterations.All models are trained for 60 epochs with Adam at a learning rate of 1 × 10^-4.Source: B. Evaluation Metric and Baselines · p. 5

C. Probability Prediction

DeepGate's attention and skip-connection design improves logic-probability prediction over the evaluated GNN baselines. Its recurrent, ordered propagation also outperforms simpler architectures, and the later large-circuit comparison focuses on DeepGate and DeepSet.

C. Probability Prediction

  • 22.76% relative prediction-error improvement over the best baseline, DAG-RecGNN with DeepSet, is achieved by DeepGate with attention alone.Adding skip connections further reduces error from 0.0234 to 0.0204.Source: 1) Comparison of DeepGate with… · p. 5
  • The best GCN prediction error, 0.1386 with Conv. Sum, exceeds the worst-performing DAG-RecGNN model.The authors attribute GCN and DAG-ConvGNN's poorer performance mainly to their inability to model circuit computation, and report that recurrent propagation with logical ordering performs well.Source: 1) Comparison of DeepGate with… · p. 5
  • For later large-circuit comparisons, the authors compare DeepGate with skip connections against DeepSet.The comparison covers five large circuits.Source: 1) Comparison of DeepGate with… · p. 5, Table III · p. 6

2) Results on Large Circuits:

DeepGate generalizes to circuits far larger than its training examples and benefits from AIG transformation and a merged multi-benchmark dataset. The reported comparisons show lower prediction error across large circuits and transformed or unified datasets.

2) Results on Large Circuits:

  • The five large test designs have two orders of magnitude more gates than the training circuits, while DeepGate achieves accuracy similar to its small-circuit results.The authors present this evaluation as evidence of generalization to larger circuits.Source: 2) Results on Large Circuits · p. 6
  • 73.56% prediction-error reduction on Arbiter accompanies DeepGate's large margin over DeepSet across five large circuits.The authors link Arbiter's result to its repeated logic units and reconvergence structures, which DeepGate treats explicitly.Source: 2) Results on Large Circuits · p. 6

1) Effectiveness of Circuit Transformation:

  • 33.94% relative prediction-error reduction on EPFL is reported for DeepGate trained on AIGs rather than original circuits, with the same observation on IWLS.The controlled EPFL comparison uses 375 extracted subcircuits.Source: Table IV · p. 6, 1) Effectiveness of Circuit… · p. 6
  • AIG transformation reduces representation-learning difficulty by limiting circuits to two gate types without changing their functionality.The authors also report that some original gate types, such as XOR and NAND, are used much less frequently, potentially causing insufficient training and higher errors.Source: 1) Effectiveness of Circuit… · p. 6
  • 51.37% further prediction-error reduction is reported when DeepGate is trained on the merged dataset of different benchmarks rather than directly applying the pretrained model.The authors say this supports unifying circuit designs in a common intermediate representation.Source: 1) Effectiveness of Circuit… · p. 6

2) Impact of Recurrence Iterations:

Increasing recurrence iterations reduces prediction loss, but the error converges quickly around T = 10. The conclusion also reports generalization to large circuits and identifies the model as still in its infancy.

2) Impact of Recurrence Iterations:

  • Prediction error converges quickly around T = 10 as recurrence iterations increase, despite circuit size.The model's prediction loss decreases as T increases; higher T also raises computational cost.Source: 2) Impact of Recurrence Iterations · p. 6

V. CONCLUSION AND FUTURE WORK

  • DeepGate generalizes from small sub-circuits to large circuits with accurate predictions and no pre-computed features.It uses signal probability as supervision and embeds logic functions and circuit structure on each gate.Source: §V · p. 6
  • The current DeepGate model is still in its infancy, with other supervision tasks and more training circuits proposed as future directions.The authors also plan to apply its learned representations to downstream EDA tasks, including power estimation, logic reduction, and equivalence checking.Source: §V · p. 6
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