Source-linked AI summary
Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
Yinxiao Feng, Kaisheng Ma
TL;DR
As process scaling slows and reticle limits approach, large monolithic dies face stagnating transistor growth and higher costs from poor yield. Chiplet Actuary models multi-chip costs and identifies conditions under which multi-chip architectures can reduce system cost.
Problem
As process scaling slows and reticle limits approach, large monolithic dies face stagnating transistor growth and higher costs from poor yield.
Source: §1 · p. 1Method
Chiplet Actuary models total system costs across three multi-chip integration technologies and supports architectural decisions about partitioning, reuse, and heterogeneity.
Source: §1 · p. 1Results
Multi-chip architecture pays off when die-defect costs exceed packaging costs; smaller chiplet granularity has marginal utility, so two or three chiplets are usually sufficient.
Source: §6 · p. 6Takeaways & Limitations
The model lets designers validate alternative multi-chip costs early, while the benefits depend on system-specific factors rather than being unconditional.
Source: §6 · p. 6The idealized results assume substantial chiplet reuse and system demand, conditions that may not hold for most design teams or production quantities.
Source: §5.3 · p. 6
Abstract
from arXiv · showhide
Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic SoC. In this paper, we build a quantitative cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture.
1 INTRODUCTION
Multi-chiplet designs may improve yield and reduce cost, but packaging, die-to-die interfaces, and engineering costs can erase the advantage. The paper introduces a quantitative cost model and an architecture-analysis method that account for these costs and assess chiplet reuse and heterogeneity.
1 INTRODUCTION
- Repartitioning a monolithic SoC into chiplets can improve overall die yield and thereby reduce cost.The paper frames this as a response to slowing process improvements, reticle-area limits, and the poorer yield associated with large dies.Source: §1 · p. 1
- Chiplet reuse can save non-recurring engineering costs by avoiding repeated system verification and chip-physics redesign.The passage contrasts chiplet reuse with IP or module reuse, which still requires repeating those tasks.Source: §1 · p. 1
- Earlier cost evaluations of multi-chip systems are difficult, and adopting chiplets without careful evaluation may increase costs because packaging and die-to-die overhead matter.Previous work focused on die and silicon-interposer manufacturing while neglecting substrates, die-to-die overhead, and non-recurring engineering costs.Source: §1 · p. 1
- Chiplet Actuary quantitatively evaluates total costs for three typical multi-chip integration technologies using external and in-house data.The model is intended to guide VLSI design and address architecture challenges such as partitioning.Source: §1 · p. 1
- The paper abstracts systems into module, chip, and package levels, then uses a unified architecture and cost model to support chiplet-architecture decisions.The decision questions include integration scheme, chiplet count, packaging reuse, chiplet reuse, and heterogeneity.Source: §1 · p. 1
2 BACKGROUND
The background distinguishes multi-chip integration technologies by their packaging characteristics and design trade-offs. It also introduces yield modeling and separates system cost into recurring production costs and one-time engineering costs.
2.1 Multi-chip Integration
- MCM, InFO, and silicon-interposer-based 2.5D integration differ in package size, I/O count, data rates, and cost, so designers select among them according to design objectives and cost constraints.The passage identifies CoWoS as TSMC's name for silicon-interposer-based 2.5D integration and describes InFO's redistribution layer as offering smaller footprints and better electrical performance than a conventional substrate.Source: §2.1 · pp. 1–2, Figure 1 · p. 1
2.2 Yield Model
- The yield model follows widely used Seed and Negative Binomial forms, with defect density, die area, and a model-specific parameter used to predict die yield.The paper says it uses more realistic parameters and presents yield-area and cost-area relations across technologies.Source: §2.2 · p. 2, Figure 2 · p. 2
2.3 NRE and RE Cost
- Total VLSI-system cost comprises non-recurring engineering costs and recurring fabrication costs, with the final engineering cost including amortized NRE.NRE covers one-time design-related costs, while RE covers production costs such as wafers, packaging, and testing.Source: §2.3 · p. 2
3 CHIPLET ACTUARY MODEL
Chiplet Actuary models system cost through module, chiplet, and package abstractions, estimating both recurring and non-recurring costs across multi-chip integration schemes.
3.1 High Level Abstraction
- The model treats modules as indivisible functional-unit groups, forms chips from modules and systems from chips, and assumes shared D2D interfaces per process node.It excludes performance and power and estimates independent NRE components separately.Source: §3.1 · p. 2
3.2 RE Cost Model
- The recurring-cost model includes D2D interface area and packaging costs, including wasted known-good dies, and prioritizes chip-last because poor packaging yield can waste dies.Wasted-die costs are especially significant when die costs are high and packaging yield is poor; the model also distinguishes interposer and bonding yields.Source: §3.2 · p. 3
3.3 NRE Cost Model
- The NRE model estimates module-, chip-, and package-design costs, using area-based factors and fixed per-chip and per-package costs.Its factors represent design complexity and capability, while the fixed chip cost includes items such as IP licensing and full masks.Source: §3.3 · p. 3
- The model distinguishes module reuse from chip reuse: a shared module is designed once, while each chip is designed individually.Multi-chip integration also includes NRE for designing the D2D interface for each process node.Source: §3.3 · p. 3
4 MODEL VALIDATION AND DISCUSSION
The model compares multi-chip integration costs across technologies and finds that yield savings depend on process, area, and packaging overhead. For a single system, multi-chiplet NRE costs can outweigh savings until production volume or area is sufficiently large.
4 MODEL VALIDATION AND DISCUSSION
- Experimental inputs combine commercial databases, public information, and in-house data; applying the model elsewhere requires updating parameters with the latest relevant data.The analysis also explores different chiplet counts and integration methods using recent data.Source: §4 · p. 3, §4.1 · p. 4
4.1 Validation and Comparison of RE cost
- At 5nm and 800 mm², die defects exceed 50% of monolithic SoC manufacturing cost; at 14nm, yield improvement saves up to 35%, but D2D and packaging overhead limits the advantage.The turning point comes earlier for advanced than mature technology, and advanced packaging is cost-effective only with advanced process technology.Source: Figure 4 · p. 4, §4.1 · p. 4
- In AMD’s Zen3 comparison, multi-chip integration saves up to 50% of die cost, but packaging overhead reduces the advantage, reaching 30% of cost for the 16-core system.The analysis uses relatively high defect-density parameters for 7nm and 12nm; improved 7nm yield further narrows the advantage.Source: §4.1 · pp. 3–4, Figure 5 · p. 4
- Increasing chiplets from three to five yields less than 10% additional die-defect savings at 5nm, 800 mm², and MCM, while increasing overhead.Explorations normalize costs to a 100 mm² SoC and assume 10% D2D overhead without reuse.Source: §4.1 · p. 4
4.2 Total Cost Comparison of Single System
- At 500k units, multi-chip NRE reaches 36%; for 5nm systems it starts to pay back at two million units, making monolithic SoC often preferable below sufficient area or volume.The comparison models an 800 mm² module area, two-chiplet MCM, and 10% D2D overhead.Source: §4.2 · pp. 4–5, Figure 6 · p. 5
5 CHIPLET REUSE SCHEME EXPLORATION
The section compares chiplet and package reuse schemes, showing that their cost benefits depend on reuse patterns, package costs, and system composition.
5 CHIPLET REUSE SCHEME EXPLORATION
- The section explores industry reuse architectures and argues that appropriate multi-chiplet designs can reduce costs.It examines SCMS, OCME, and FSMC reuse schemes.Source: §5 · p. 5, Figure 7 · p. 5
5.1 Single Chiplet Multiple Systems (SCMS)
- In SCMS, package reuse cuts package NRE by two-thirds for the largest 4X system, but raises total cost by more than 20% for the smallest 1X system.For high-cost 2.5D integration, reusing a 4x interposer in a 1x system makes packaging cost more than 50%, so package reuse is uneconomic even though chiplet reuse can still help.Source: §5.1 · p. 5, Figure 8 · p. 5
5.2 One Center Multiple Extensions (OCME)
- Heterogeneous OCME reduces total costs by more than 10%, with nearly half the cost-saving for the single C system.It is more cost-effective for systems sharing large areas of modules that do not benefit from advanced process nodes.Source: Figure 9 · p. 5, §5.2 · p. 6
5.3 A few Sockets Multiple Collocations (FSMC)
- FSMC offers extensive reuse through packages with multiple sockets, but its modeled savings are idealized because not every chiplet or system can be reused or produced at scale.With full reuse, NRE amortization becomes small enough to ignore, and savings include both RE and NRE costs.Source: §5.3 · p. 6, Figure 10 · p. 6
6 SUMMARY
The paper presents multi-chip cost benefits as conditional on design and cost factors, and offers a quantitative model to compare alternatives. It concludes that yield improvement and reuse can benefit appropriate architectures, while advanced packaging and interposer limits remain constraints.
6 SUMMARY
- The quantitative cost model supports early comparison of multi-chip alternatives, whose benefits depend on yield improvement, chiplet and package reuse, and heterogeneity.The paper presents the model as a way to validate costs at the early design stage.Source: §6 · p. 6
- Multi-chip architecture pays off when die-defect costs exceed packaging costs, with greater benefits closer to the Moore Limit.The paper says splitting a system into two or three chiplets is usually sufficient because RE benefits from smaller chiplet granularity have marginal utility.Source: §6 · p. 6
- For multiple system grades, SCMS, OCME, and FSMC offer different reuse advantages, while multi-chip architecture does not fundamentally extend Moore’s Law.The paper also notes that ultra-high-performance systems near the Moore Limit require advanced packaging, which still faces interposer yield and area limits.Source: §6 · p. 6