Source-linked AI summary
Distributed quantum error correction for chip-level catastrophic errors
Qian Xu, Alireza Seif, Haoxiong Yan, Nam Mannucci, Bernard Ousmane Sane, Rodney Van Meter, Andrew N. Cleland, Liang Jiang
TL;DR
The paper addresses chip-level catastrophic erasures and develops distributed erasure correction across separate chips. It uses encoded blocks and teleportation-based Knill QEC, while also comparing this approach with erasure-flag correction. The analysis shows a trade-off between Knill’s speed and simplicity and the alternative’s lower resource and connectivity demands.
Problem
The supplemental material addresses how to correct catastrophic erasures distributed across separate quantum chips.
Method
The paper uses distributed encoded blocks, encoded Bell-pair preparation, teleportation, and erasure-flag protocols to correct chip-level erasures.
Results
The Knill scheme is simpler and faster, while the erasure-flag scheme is more resource-efficient and requires less complex connectivity.
Takeaways & Limitations
The erasure-flag scheme extends in principle to planar surface codes of arbitrary distance and can correct up to d −1 arbitrary erasures.
Takeaways & Limitations
Recovery operations occupy logical qubits and require inter-node gates using physical Bell pairs, potentially delaying subsequent application gates.
Abstract
from arXiv · showhide
Quantum error correction holds the key to scaling up quantum computers. Cosmic ray events severely impact the operation of a quantum computer by causing chip-level catastrophic errors, essentially erasing the information encoded in a chip. Here, we present a distributed error correction scheme to combat the devastating effect of such events by introducing an additional layer of quantum erasure error correcting code across separate chips. We show that our scheme is fault tolerant against chip-level catastrophic errors and discuss its experimental implementation using superconducting qubits with microwave links. Our analysis shows that in state-of-the-art experiments, it is possible to suppress the rate of these errors from 1 per 10 seconds to less than 1 per month.
Supplemental Information for “Distributed quantum error correction for chip-level
The supplemental information accompanies “Distributed quantum error correction for chip-level catastrophic errors.” It identifies the paper’s authors and arXiv version.
- Qian Xu, Alireza Seif, Haoxiong Yan, Nam Mannucci, and Bernard Ousmane are listed among the authors.
- The document lists Rodney Van Meter, Andrew N. Cleland, and Liang Jiang as additional authors.
- The listed preprint is arXiv:2203.16488v1, dated 30 March 2022.
I. FAULT-TOLERANT CRITERIA FOR THE ERASURE ERROR CORRECTION
The erasure-error protocol is defined as fault tolerant when bounded erasures preserve ideal decoding and limit output errors to the number of protocol erasures. The presented erasure-flag scheme satisfies these criteria.
- Fault tolerance requires that input errors plus protocol erasures totaling at most t leave ideal input and output decoding equivalent.
- For at most t protocol erasures, the output may differ from a codeword by an error of weight no greater than the number of erasures.
- The erasure-flag scheme satisfies both fault-tolerance criteria for erasure errors.
II. THE KNILL QUANTUM ERROR CORRECTION FOR ERASURE ERRORS
The Knill scheme distributes encoded blocks across chips, prepares an encoded Bell pair, and teleports information to an unaffected block. Fault tolerance requires detecting and restarting preparation when erasures occur during the non-transversal state-preparation stage.
- II. THE KNILL QUANTUM ERROR CORRECTION FOR ERASURE ERRORS: The scheme uses black, blue, and orange encoded blocks with each qubit placed on a distinct chip.
- II. THE KNILL QUANTUM ERROR CORRECTION FOR ERASURE ERRORS: It corrects erasures by preparing a blue-orange encoded Bell pair and teleporting information from the black block to the orange block.
- II. THE KNILL QUANTUM ERROR CORRECTION FOR ERASURE ERRORS: The protocol succeeds when the remaining unaffected qubits support faithful logical X and Z measurements.
- II. THE KNILL QUANTUM ERROR CORRECTION FOR ERASURE ERRORS: Non-transversal preparation of |00⟩L can spread erasures across chips, so detected bad erasures require replacing affected chips and restarting preparation.
- II. THE KNILL QUANTUM ERROR CORRECTION FOR ERASURE ERRORS: After verified preparation, transversal gates create the Bell state and a transversal Bell measurement teleports information using intact qubits.
- II. THE KNILL QUANTUM ERROR CORRECTION FOR ERASURE ERRORS: The [[4, 1, 2]] circuit corrects 1 erasure, whereas the [[7, 1, 3]] circuit corrects 2 and adaptively repeats |00⟩L preparation when needed.
III. COMPARISON BETWEEN THE KNILL SCHEME AND THE ERASURE-FLAG SCHEME
The Knill scheme trades greater resource and connectivity demands for simpler, faster recovery than the erasure-flag scheme. The comparison quantifies this trade-off in patches and estimated recovery times.
- III. COMPARISON BETWEEN THE KNILL SCHEME AND THE ERASURE-FLAG SCHEME: The Knill scheme is simpler and faster, whereas the erasure-flag scheme is more resource-efficient but more complex and slower.
- III. COMPARISON BETWEEN THE KNILL SCHEME AND THE ERASURE-FLAG SCHEME: For the [[4, 1, 2]] code, Knill requires 12 surface patches compared with 5 for the erasure-flag scheme.
- III. COMPARISON BETWEEN THE KNILL SCHEME AND THE ERASURE-FLAG SCHEME: Estimated maximal recovery times are approximately 210µs and 342µs for Knill, versus 270µs and 1000µs for erasure-flag, for the four- and seven-qubit codes respectively.
- III. COMPARISON BETWEEN THE KNILL SCHEME AND THE ERASURE-FLAG SCHEME: Including lattice-surgery ancilla patches, the general requirements are 4n patches for Knill and n + 2 for erasure-flag.
- III. COMPARISON BETWEEN THE KNILL SCHEME AND THE ERASURE-FLAG SCHEME: The Knill scheme may require complex connectivity between data chips, while erasure-flag needs connectivity only between an ancilla chip and data chips.
IV. APPLICATION OF THE ERASURE-FLAG SCHEME TO OTHER CODES
The erasure-flag scheme extends beyond small stabilizer codes to surface and toric codes of arbitrary distance, correcting up to d −1 erasures through adaptive stabilizer measurement.
- IV. APPLICATION OF THE ERASURE-FLAG SCHEME TO OTHER CODES: The scheme applies to CSS surface codes and, more generally, Kitaev toric codes with arbitrary distance.
- IV. APPLICATION OF THE ERASURE-FLAG SCHEME TO OTHER CODES: A d × d planar surface code can correct up to d −1 arbitrary erasures using the erasure-flag scheme.The argument treats erasures as arbitrary Pauli errors with known locations.
- IV. APPLICATION OF THE ERASURE-FLAG SCHEME TO OTHER CODES: Adaptive measurement of an appropriate stabilizer sequence keeps the erasure-flag set correctable while no more than d −1 erasures occur.The proof bounds the occupied rows and columns so products of flagged errors cannot form logical operators.
- IV. APPLICATION OF THE ERASURE-FLAG SCHEME TO OTHER CODES: Only a minimal set of stabilizers covering the known faulty qubits is measured to diagnose and correct the flagged errors.For s known X-error locations, at most s Z-type stabilizers are measured, with an analogous procedure for Z errors.
V. SYSTEM PERFORMANCE IMPLICATIONS
The distributed architecture mitigates catastrophic CRE damage but introduces recovery-time and hardware costs that affect application performance and system design.
- V. SYSTEM PERFORMANCE IMPLICATIONS: Distributed nodes can initially run the entire application without affecting execution time to first approximation, but CRE recovery occupies logical qubits for extended periods.Recovery uses inter-node gates mediated by physical Bell pairs and dedicated transceiver qubits.
- V. SYSTEM PERFORMANCE IMPLICATIONS: Qubit placement and dynamic Bell-pair scheduling can delay forthcoming application gates, making recovery-process optimization an open research problem.The relevant static qubit-mapping problem is NP-complete, while inter-chip recovery changes preferred logical-qubit locations.
- V. SYSTEM PERFORMANCE IMPLICATIONS: A factor-of-six or factor-of-nine hardware cost yields a projected four- to six-order-of-magnitude gain in memory lifetime.The factors correspond to the [[4,1,2]] and [[7,1,3]] codes, respectively.