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Physical Unclonable Functions (PUF) for IoT Devices

Abdulaziz Al-Meer, Saif Al-Kuwari

arXiv:2205.08587v1cs.CR

TL;DR

IoT networks need lightweight approaches to authenticity and confidentiality because conventional cryptography can impose computational demands on resource-constrained devices and may face quantum-era challenges. This survey reviews PUF architectures, authentication protocols, and security attacks, concluding that PUFs offer low-complexity, lower-energy security while leaving confidentiality and integrity mechanisms as open challenges.

  • Problem

    IoT networks require authenticity and confidentiality, while conventional cryptography can impose computational demands on lightweight devices and may be threatened by advances in quantum computing.

  • Method

    The survey reviews PUF architectures, authentication protocols, and common security concerns and attacks for IoT environments.

  • Results

    The survey concludes that PUF designs provide low computational complexity, lower energy use, and improved randomness, uniqueness, and reliability for IoT security.

  • Takeaways & Limitations

    PUFs provide lightweight authentication without storing secret keys in memory or relying on traditional cryptography methods that increase power and resource consumption.

  • Takeaways & Limitations

    PUF-based confidentiality and integrity for exchanging information between IoT devices remain largely unaddressed, requiring further research.

Abstract

from arXiv · show

Physical Unclonable Function (PUF) has recently attracted interested from both industry and academia as a potential alternative approach to secure Internet of Things (IoT) devices from the more traditional computational based approach using conventional cryptography. PUF is promising solution for lightweight security, where the manufacturing fluctuation process of IC is used to improve the security of IoT as it provides low complexity design and preserves secrecy. It provides less cost of computational resources which prevent high power consumption and can be implemented in both Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASICs). In this survey we provide a comprehensive review of the state-of-the-art of PUF, its architectures, protocols and security for IoT.

1 Introduction

PUFs are presented as lightweight alternatives to conventional cryptography for IoT security, addressing computational, key-management, and upper-layer vulnerabilities. This survey reviews PUF metrics, protocols, architectures, implementations, attacks, and open problems.

  • Motivation: PUFs address IoT authenticity and confidentiality needs while avoiding the heavy computational requirements that can reduce battery efficiency.The paper positions PUFs as lightweight hardware-security alternatives for constrained devices.
  • Motivation: Advances in quantum computing may undermine conventional cryptography based on the hardness of mathematical problems.The authors identify this as a limitation of conventional cryptographic assumptions.
  • PUF approach: PUFs exploit manufacturing variations to generate device-specific secret keys and authenticate IoT devices.The same fabrication process does not produce chips with identical physical properties.
  • Survey scope: The survey responds to a lack of comprehensive reviews combining recent implementations, quality evaluation, and security perspectives across PUF architectures.The authors describe this gap as motivating the survey.
  • Survey scope: The survey covers PUF quality metrics, authentication protocols, IoT-oriented architectures, FPGA implementations, common attacks, and future directions.Its stated contributions span evaluation, protocol comparison, architecture analysis, threat investigation, and open problems.

2 PUF fundamentals

PUFs use uncontrollable manufacturing variation to map challenges to device-specific responses, supporting authentication, key generation, and other security applications. Their properties and categories determine security behavior, while designs such as controlled PUFs restrict challenge access to hinder attacks.

  • PUF operation: A PUF maps a challenge C to an unpredictable response R, forming a challenge-response pair that differs across integrated circuits.Manufacturing variation creates device-specific physical behavior that cannot be deliberately controlled.
  • PUF properties: PUF security relies on unpredictable responses, difficult CRP modeling, and resistance to cloning or reproduction.The paper also describes large challenge spaces and non-reproducibility across manufacturing variations.
  • PUF properties: PUF physical characteristics include signal transmission speed, oscillation frequency, and memory startup states, which can support physical-layer security.These characteristics arise from circuit and manufacturing variation.
  • Applications: PUFs support authentication, secret-key generation, random-number generation, malware detection, degraded-hardware detection, and authenticated self-destruction.The paper lists these as applications with potentially different design requirements.
  • Security criteria: PUF security evaluation considers response reproducibility, inter-device uniqueness, challenge-space size, and resistance to environmental variation.The paper identifies these criteria as important for secrecy and reliable operation.
  • PUF categories: Memory-based PUFs use startup memory states, delay-based PUFs use propagation-delay variation, and weak, strong, and controlled PUFs represent another common classification.Weak PUFs use limited CRPs, strong PUFs offer many CRPs, and controlled PUFs regulate challenge access.

3 PUF performance evaluation

PUF performance is evaluated using four essential metrics: uniformity, uniqueness, reliability, and bit-aliasing. Together, these metrics assess response randomness, device distinctiveness, environmental stability, and response similarity.

  • Four essential PUF evaluation parameters are uniformity, uniqueness, reliability, and bit-aliasing.
  • Uniformity measures whether response bits are evenly distributed and reflects response-bit randomness through Hamming Weight.
  • Uniqueness measures a PUF’s ability to distinguish same-structure ICs under the same challenge, with an ideal inter-device Hamming Distance of 50%.
  • Reliability measures whether the same challenge reproduces the same response despite supply-voltage and temperature fluctuations.
  • Bit-aliasing measures response similarity across PUFs by averaging the Hamming weight of a response bit across devices, with an ideal value of 50%.

4 PUF authentication protocols and key generation

PUF authentication protocols provide a lightweight way to authenticate constrained IoT and RFID devices without conventional cryptography. Authentication uses enrollment and verification phases, while related protocols add error correction, cryptographic primitives, or wireless-channel information.

  • PUF authentication targets low-cost IoT and RFID devices while reducing power consumption and circuit-area overhead compared with conventional cryptography.
  • Authentication has enrollment and verification phases in which challenge-response pairs are stored by a server and later used to authenticate the IoT device.
  • PUF key-generation protocols use error-correction initialization and regeneration to reproduce keys under environmental and power-supply variation, then combine the keys with cryptographic primitives.
  • A lightweight WiFi protocol authenticates IoT devices using only 3 CRPs and addresses MAC spoofing, invasive, and evil-twin attacks.
  • Other protocols provide mutual authentication with on-the-fly keys or use RSSI and wireless-channel properties to distinguish legitimate from eavesdropper channels.

5 PUF Architectures

The survey evaluates PUF architectures using security, quality, and implementation criteria, then describes Arbiter and Ring Oscillator PUFs as common designs for IoT.

  • Architecture criteria: PUF architecture selection considers attack robustness, uniqueness, reliability, and randomness.Reliability requires consistent responses across environmental changes such as temperature and voltage.
  • Arbiter PUF: Arbiter PUF compares two challenge-selected path delays and outputs a bit according to the faster path.Manufacturing variations create different delay paths, while the output latch selects the response.
  • Arbiter PUF: Arbiter PUF is a strong PUF requiring equal-length delay paths for practical statistical properties.It can be implemented in both FPGA and ASIC technologies.
  • Arbiter PUF: Reconfigurable and energy-efficient Arbiter PUF variants increase path connectivity or reduce circuit energy requirements.A 4×4 switch block increases path connections, while current-starved inverters target energy efficiency.
  • Ring Oscillator PUF: Ring Oscillator PUF generates response bits by comparing oscillator frequencies, but environmental sensitivity is its main drawback.Manufacturing variation produces frequency differences even though theoretical oscillator frequencies should match.
  • Ring Oscillator PUF: Configurable Ring Oscillator PUF designs target improved reliability, lower power or area, and higher response entropy.Other implementations reduce overhead and power using frequency dividers with flip-flops instead of counters and comparators.

5.3 SRAM PUF

SRAM PUFs derive responses from unpredictable SRAM power-up states, but their limited challenge-response capacity, noise, and microcontroller focus constrain their use.

  • SRAM operation: SRAM PUF generates response bits from unpredictable initial SRAM cell values during power-up.Each SRAM has a unique boot-up state that acts as a noisy physical fingerprint.
  • Limitations: SRAM PUF is a weak PUF with limited challenge-response pairs and is mainly applicable to microcontrollers.Its limited challenge space requires additional security layers against machine-learning attacks.
  • Limitations: SRAM PUF suffers from noise effects and requires error correction.

5.4 Hybrid PUF

The survey covers hybrid and emerging PUF designs that combine architectures or exploit alternative physical technologies to improve security, efficiency, or uniqueness.

  • Hybrid PUF: Lightweight Hybrid PUF combines Arbiter PUF and Ring Oscillator PUF features using multiplexers, counters, logic gates, and an arbiter.Its response depends on counting the number of 1s or 0s at the counter output.
  • Hybrid PUF: An FPGA-implemented Lightweight Hybrid PUF reportedly provides higher security performance than traditional Arbiter and Ring Oscillator PUFs with less power consumption.
  • Hybrid PUF: FinFET-based hybrid oscillator-arbiter PUF designs improve power consumption and speed relative to traditional Ring Oscillator and Arbiter PUFs.
  • Optical PUF: Optical PUFs use physical optical structures, including three-dimensional glass tokens or PCB-integrated imagers, LEDs, and polymer waveguides.The first described optical system generated a 2400-bit unique key.
  • Memristor PUF: Memristor PUFs exploit variable resistance states and switching behavior to produce unpredictable values.Memristor states transition between high and low resistance through SET and RESET operations.
  • Quantum PUF: Quantum PUF authentication uses quantum challenges and responses, with the no-cloning theorem enabling interception detection.

5.8 MRAM PUF

MRAM PUFs generate keys and authentication data from manufacturing variation in magnetic memory cells, while related CNTFET designs target low-power, high-quality signatures.

  • MRAM PUF: MRAM PUF generates unique keys and supports authentication by exploiting geometric variation in magnetic tunnel junction cells.Manufacturing variation changes cell shape, including rectangular or elliptical geometries.
  • MRAM PUF: TAS-MRAM experimental evaluation reports lower power consumption and higher speed than SRAM.
  • CNTFET PUF: CNTFET PUFs generate signatures by comparing currents or voltages across transistor-based stages.Reported simulations and measurements address reliability under environmental variation and quality metrics such as uniformity and uniqueness.

5.10 Others PUFs

This section surveys additional PUF architectures that exploit circuit, transistor, memory, and magnetic-device variations to improve identification, reliability, security, or implementation flexibility.

  • Glitch PUF exploits variations in the glitch waveforms of logic gates.
  • Butterfly PUF avoids SRAM initialization requirements in some FPGAs, supporting implementation across all FPGA types.
  • Latch PUF uses cross-coupled NOR-gate arrays to introduce unique IC identifiers while improving speed and power consumption.
  • Digital PUF improves the reliability of analog PUFs, while Coin Flipping PUF exploits bistable-ring convergence time.
  • PUF-FSM removes the need for error-correction codes in Controlled PUFs and improves security.
  • SCA-PUF compares output voltages from transistor arrays using their I −V characteristics, while SOT PUF provides reconfigurability through domain-wall motion.

6 PUF implementation

The survey reviews FPGA-oriented PUF implementations, emphasizing architectures that exploit configurable FPGA resources and trade off entropy, reliability, uniqueness, security, speed, power, and hardware cost.

  • 6 PUF implementation: FPGA implementations are attractive because flexibility, customizability, configurable logic, and rapid deployment support PUF design for IoT devices.
  • Arbiter PUFs: Arbiter-PUF variants use multiple arbiters, flip-flops, XOR gates, feedback, or reliability flags to improve uniqueness, entropy, or reliability.The 3-1 Double Arbiter PUF uses three arbiters and one response bit; another flip-flop/XOR design improves uniqueness by 16% but consumes more resources.
  • Ring oscillator PUFs: TERO-PUF uses oscillation in four 64-loop cells and can thwart electromagnetic attacks, but it requires more hardware resources.
  • LFSR-based PUFs: LFSR-based FPGA PUFs address linearity and predictability through nonlinear functions, asynchronous designs, or RO-based logic while targeting entropy, speed, and power efficiency.PL-MRO PUF is reported to provide sufficient entropy, high-speed operation, and low power consumption compared with conventional RO PUF.
  • Other FPGA architectures: Other FPGA PUFs exploit LUTs, flip-flops, NAND gates, multiplexers, or LDPC coding to target area efficiency, entropy, reliability, and uniformity.One design improves reliability under environmental variation and uniformity but has lower uniqueness, limiting authentication suitability.

7 Threat landscape and Security

The survey frames PUF security around communication eavesdropping, physical access, environmental manipulation, invasive probing, side-channel leakage, and machine-learning prediction of challenge-response pairs.

  • Threat model: The threat model includes eavesdroppers with communication access, attackers with physical device access, and active adversaries manipulating temperature or power supply.Active attacks require physical access to the PUF chip, whereas passive adversaries observe or intercept communication data.
  • Exhaustive CRP attacks: Enumerating all challenge-response pairs is time-consuming and produces a large table requiring considerable storage.
  • Invasive attacks: Invasive delay-measurement attacks require removing packaging and metal layers, while probing can alter or destroy delayed-path wiring.The survey characterizes these attacks as costly and impractical because they require specialized laboratory equipment.
  • Machine-learning attacks: Communication-channel attackers can intercept authentication exchanges and train machine-learning models to predict challenge-response pairs; Arbiter-PUF is identified as vulnerable.
  • Noninvasive and semi-invasive attacks: Physical characterization techniques include photonic emission analysis, laser fault injection, optical probing, and electromagnetic analysis for extracting PUF information.
  • Modeling attacks: Machine-learning studies evaluate prediction across PUF architectures using models such as SVM, logistic regression, evolutionary strategies, Naive Bayes, AdaBoost, and neural networks.For an STT-MRAM reconfigurable Arbiter PUF, prediction rates were 65.12% without XOR gates and 44.34% with XOR gates.
  • Countermeasures: Avoiding challenge-response reuse and generating many pairs can hinder prediction, but larger PUF circuits increase computational overhead.
  • Side-channel attacks: Side-channel attacks exploit relationships between power dissipation and PUF responses, including leakage from latch structures that can support cross-PUF prediction.One evaluated STT-MRAM design found no correlation between power consumption and 800 generated responses, while Cross-PUF attacks use a reference PUF to target others sharing a GDS.

8 Conclusion and Outlook

The survey presents PUF architectures, authentication protocols, implementations, quality metrics, and attacks as components of lightweight IoT security, while identifying unresolved security and confidentiality challenges.

  • Conclusion: The survey reviews PUF architectures and authentication protocols as lightweight IoT security solutions with low computational complexity and energy use.It also discusses quality metrics including randomness, uniqueness, and reliability, alongside common attacks and security concerns.
  • Outlook: Further testing is needed to evaluate PUF security strengths and weaknesses across different properties.
  • Outlook: PUF techniques can provide lightweight IoT authentication without traditional cryptography or storing secret keys in memory.
  • Open problems: Designing PUF architectures that resist machine-learning attacks remains an open research need.
  • Open problems: Confidentiality and integrity for exchanging information between IoT devices remain unaddressed by the PUF community.Existing PUF authentication protocols use conventional confidentiality and integrity techniques, trading off circuit and computational complexity.
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