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Relaxing Hardware Requirements for Surface Code Circuits using Time-dynamics

Matt McEwen, Dave Bacon, Craig Gidney

arXiv:2302.02192v2quant-ph

TL;DR

Static QEC-code descriptions can obscure freedom in how circuits are implemented on hardware. The paper designs time-dynamic surface-code circuits directly using detecting regions, obtaining variants with relaxed connectivity, alternative gates, and changed qubit roles. These constructions retain essentially the same logical performance while using four entangling-gate layers rather than adding depth.

  • Problem

    Static QEC-code descriptions hide freedom in decomposing codes into hardware-executable circuits, while hardware implementations face demanding connectivity, gate, and leakage constraints.

  • Method

    The paper designs time-dynamic QEC circuits directly using detectors, detecting regions, and evolving stabilizer structure instead of decomposing static codes into circuits.

  • Results

    The constructions achieve essentially the same logical performance as standard surface-code circuits while using three couplings per qubit, ISWAP gates, or measurements on all physical qubits, without adding entangling-gate layers.

  • Takeaways & Limitations

    Directly constructing time-dynamic circuits can relax hardware requirements while preserving the surface code and its logical performance.

Abstract

from arXiv · show

The typical time-independent view of quantum error correction (QEC) codes hides significant freedom in the decomposition into circuits that are executable on hardware. Using the concept of detecting regions, we design time-dynamic QEC circuits directly instead of designing static QEC codes to decompose into circuits. In particular, we improve on the standard circuit constructions for the surface code, presenting new circuits that can embed on a hexagonal grid instead of a square grid, that can use ISWAP gates instead of CNOT or CZ gates, that can exchange qubit data and measure roles, and that move logical patches around the physical qubit grid while executing. All these constructions use no additional entangling gate layers and display essentially the same logical performance, having teraquop footprints within 25% of the standard surface code circuit. We expect these circuits to be of great interest to quantum hardware engineers, because they achieve essentially the same logical performance as standard surface code circuits while relaxing demands on hardware.

1 Introduction

The paper proposes designing time-dynamic QEC circuits directly, using detecting regions to relax hardware requirements while preserving surface-code performance. It presents circuits with fewer couplings, alternative gates, exchanged qubit roles, and logical-patch motion without adding entangling-gate layers.

  • Motivation and approach: Detecting regions provide an alternative foundation for reasoning about QEC circuits directly rather than first choosing static code stabilizers.The authors use this framework to construct circuits by modifying detector time dynamics in the standard surface-code circuit.
  • Motivation and approach: Designing time-dynamic circuits directly complements hardware-specific code design by showing that hardware need not provide some capabilities when the circuit is redesigned.The paper frames this as replacing “hardware can do X” assumptions with circuits that avoid requiring X.
  • Main contributions: Three couplings per qubit, ISWAP gates, and measurements on all physical qubits enable surface-code circuits with relaxed hardware requirements.These constructions target lower connectivity, alternative entangling operations, and improved leakage resilience.
  • Main contributions: All three exemplar circuits retain four layers of entangling gates and achieve essentially the same logical performance as standard surface-code circuits.The improvements are presented as individually nonexclusive and potentially combinable.
  • Paper organization: The paper organizes its main constructions around hexagonal-grid circuits, ISWAP-based circuits, and circuits that exchange data and measure-qubit roles.It also discusses moving logical patches and applications beyond hardware relaxation, including logical compilation.

2 Concepts and Tools

The paper develops detecting regions as a circuit-level language for fault tolerance: their time-slices track evolving stabilizers, and their overlaps define detectors and circuit structure. This perspective exposes freedom to redesign surface-code circuits while preserving the relevant detection behavior.

  • 2 Concepts and Tools: The paper approaches fault-tolerant circuit construction by propagating stabilizers, introducing detectors and detecting regions, and then addressing circuit fault tolerance directly.This alternative avoids disturbing the desirable code properties or requiring a new decoding or logical-computation strategy.
  • 2.1 Mid-cycle states: The standard surface-code cycle evolves through post-reset, brickwork, half-cycle, modified brickwork, and pre-measure states before returning to the checkerboard state.Mid-cycle states include ancillary stabilizers and provide checkpoints for analyzing circuit evolution.
  • 2.2 Detectors and Detecting Regions: Detecting regions identify circuit locations where errors can affect detectors, with Pauli types specifying which inserted errors are detected.Detectors are measurement sets with deterministic noiseless parity, while detecting regions propagate their error sensitivity through the circuit.
  • 2.2.2 Overlapping structure of detecting regions: In repetition and surface codes, bulk detecting regions span two neighboring cycles and overlap so individual errors can trigger multiple detectors.Their mid-cycle structure covers the code stabilizer while involving both measure and data qubits.
  • 2.2.2 Overlapping structure of detecting regions: An overlapping structure of detecting regions can define both the error-correcting code and its circuit operations through implied stabilizer flows.The authors use this structure as a direct construction primitive rather than treating the circuit as a decomposition of a preselected code.

2.3 Detecting Regions in the Surface Code

Detecting regions provide a time-dynamic view of surface-code circuits, exposing how stabilizer-like regions evolve, overlap, and define boundaries throughout a cycle.

  • Detecting regions: Detecting regions reinterpret circuit states as time-slices of the surface-code stabilizers, including mixed Pauli types within a slice.The CZ compilation produces XZZX/ZXXZ stabilizers at measurement when unnecessary Hadamards are canceled.
  • Detecting regions: Each circuit location is covered by four detecting regions, with two Z-type and two X-type regions forming the separate X- and Z-error graph components.The overlapping structure also makes the correlated nature of Y errors visible.
  • Mid-cycle dynamics: Regions are distinguished as expanding or contracting according to whether they emerge from a reset this round or continue from the previous round’s code-stabilizer coverage.The two classes evolve differently as the cycle proceeds.
  • Equivalent cycle pictures: Equivalent surface-code cycle descriptions can begin from end-cycle, half-cycle, or brickwork states, each emphasizing different stabilizer measurement and reconstruction operations.Brickwork states exchange two- and six-body stabilizers through CNOT layers, while half-cycle operations measure alternating subsets.
  • Boundaries: Temporal boundaries are created by measuring or resetting all qubits in the desired basis and deleting or terminating incompatible bulk detecting regions.Spatial boundaries require more careful construction because naive truncation is wasteful and boundary choices affect graph-like code distance.
  • Software tools: Software visualization and verification tools were necessary to explore these interlocking circuits, check code distance, and benchmark their logical performance.Stim and its visualization tools supported both construction and explanation of the circuits.

3 Hex-grid Surface Code Circuits

The paper constructs a surface-code circuit that uses only three couplings per qubit and embeds on a hexagonal grid without adding entangling-gate layers.

  • Overview: The hex-grid circuit preserves the standard surface code’s code distance and entangling-layer count while reducing each qubit’s required couplers from four to three.The construction uses the same number of entangling layers as the usual square-grid circuit.
  • Half-cycle construction: Folding four-body stabilizers into one-body measurements uses only three of four neighboring couplings, and the fold operations can then be reversed.Diagonal columns of alternating X- and Z-type stabilizers can be measured in parallel.
  • Half-cycle construction: Two alternating cycles measure all half-cycle stabilizers while switching which detecting regions are expanding and contracting.Alternating cycles restore the same half-cycle pattern every two rounds, ensuring both stabilizer sets are measured.
  • Half-cycle construction: The two cycle circuits share a compatible pattern of unused couplings, so their combined connectivity is a hex grid rather than a square grid.This compatibility is the direct geometric reason the construction needs only three neighboring couplers per qubit.
  • Brickwork construction: A complementary brickwork construction measures two-body stabilizers with CNOT–measurement–CNOT sequences and exchanges them with six-body stabilizers using two CNOT layers.The complete cycle performs two measurement stages separated and closed by stabilizer-exchange layers.
  • Boundaries and summary: The resulting strategy uses two distinct cycles and naturally embeds on a hex grid, with boundary shapes chosen through the half-cycle detecting-region pattern.The construction includes flat weight-3 and spiky weight-1 boundary regions to complete diagonal measurement columns.

4 ISWAP Surface Code Circuits

The paper constructs surface-code circuits using ISWAP-like interactions by tracking time-dynamic detecting regions rather than fixed stabilizers. These circuits retain the standard code distance and entangling-layer count while achieving essentially identical teraquop footprints.

  • The ISWAP circuit has the same code distance and number of entangling layers as the usual surface-code circuit.It enables operation on hardware with a native ISWAP-like gate without circuit-depth overhead.
  • The construction uses detecting regions to manage qubit-state movement caused by ISWAP-like gates and recover the required stabilizer measurements.CXSWAP provides a conceptually simpler presentation because its stabilizer flows retain a single Pauli type, while the resulting regions overlap and distort the standard patch.
  • The ISWAP/CXSWAP circuits distort the surface-code patch, shifting data and measure qubits in alternating directions and requiring modified boundaries.The boundary construction preserves graph-like code distance, while the benchmarked ISWAP variant uses slightly different corner and measurement arrangements.
  • 4.4 Benchmarking: The ISWAP circuit’s teraquop footprint is essentially identical to that of the standard circuit.The authors caution that this qualitative comparison depends on the error model.
  • The ISWAP construction completes surface-code implementations across the two-qubit Clifford KAK gate classes and targets hardware with a natural ISWAP interaction.This avoids requiring a CNOT-like native entangling gate for surface-code implementation.

5 Walking Surface Code Circuits

The walking circuits use time-dynamic detecting-region pairings to exchange data and measurement roles while moving a logical surface-code patch across the physical grid. They preserve circuit-layer overhead and code distance, with walking variants showing qualitatively similar teraquop footprints to the standard circuit.

  • Walking circuits move the logical surface-code patch without increasing circuit-layer overhead or reducing code distance.The movement exchanges the roles of data and measure qubits, creating a primitive relevant to leakage mitigation.
  • The stepping trick changes only the directions of the final CNOT layer, selecting which qubit each detecting region contracts onto.This alternative pairing allows contracting regions to terminate on previously data qubits and expanding regions to cover new stabilizers.
  • The moving patch requires carefully designed leading and trailing boundaries, while logical observables move with the patch through measurements at the trailing boundary.The step cycle can be shifted and rotated to continue movement in the four cardinal directions.
  • 5.3 Benchmarking: The walking-code teraquop footprints lie between 1000 and 3000 qubits at an aspirational limiting error rate of 1 × 10^-3.The standard circuit performs slightly better, attributed to the extra qubits entered as the step cycle moves.
  • The circuit exchanges data and measurement roles without additional gate overhead and moves the logical patch, while performing comparably to the traditional circuit without leakage errors.Potential advantages under leakage remain to be simulated and quantified in future work.

6 Conclusion and Outlook

The paper combines and extends time-dynamic surface-code circuits to relax hardware requirements, while identifying important limits for broader deployment and evaluation.

  • Further Constructions: The constructions can be combined, including a circuit using a hex grid, ISWAP gates, and exchanged data and measure qubits, with exact circuits and benchmarking provided.These combined circuits are not discussed in equal detail to the individual constructions.
  • Further Constructions: The heavy-hex circuit uses six entangling-gate layers per measurement cycle and outperforms the heavy-hex and heavy-square codes.A four-layer variant using flag-qubit teleportation was not benchmarked because the authors expected worse performance.
  • Further Constructions: The semi-heavy-hex circuit has below-three average connectivity and requires only three entangling-gate layers per measurement cycle.The additional qubits increase parallelization relative to the hex-grid circuit.
  • Further Constructions: Under the assumed error model, hybrid circuits using native parity measurements perform better than equivalent circuits using only two-qubit gates.The authors expect the true hardware error model to determine relative performance in practice.
  • Open Problems: The constructions are early steps toward tailoring QEC circuit decompositions to relax or improve hardware requirements.The paper identifies applying the ideas to other codes, spatial compatibility, boundary refinement, and more realistic benchmarking as open work.
  • Conclusion: The approach constructs QEC circuits directly from time-dynamic detecting regions rather than decomposing static stabilizer codes, creating additional freedoms for hardware design.The authors present these constructions as evidence that the approach merits further development.

Contributions

The contributions were developed collaboratively around detecting-region-based surface-code circuit construction and software-assisted exploration.

  • Contributions: The authors developed hex-grid, ISWAP, and dynamic surface-code circuit constructions through a collaborative process centered on overlapping detecting regions.The listed contributions include software development, initial wiggling and walking circuits, and initial ISWAP and hex-grid circuits.

A Stabilizer Formalism and Detecting Regions

The appendix develops stabilizer flows as a circuit-level language for tracking Pauli transformations, including irreversible operations, and uses them to identify detecting regions. It also describes algebraic composition, unsigned stabilizers, and applications to QEC circuit analysis.

  • A Stabilizer Formalism and Detecting Regions: Detecting regions are built from deterministic measurement outcomes under noiseless execution, whose choice is non-unique because products of detectors are also valid detectors.The formalism connects measurement records to circuit regions that can be used in time-dynamic QEC analysis.
  • A.1 Stabilizer Flows: Stabilizers describe quantum states through signed Pauli terms, while stabilizer flows generalize this framework to preparations, measurements, resets, and other dissipative operations.A stabilizer flow asserts how a Pauli operator is transformed across an operation.
  • A.1 Stabilizer Flows: The flow definition avoids inverse or controlled operations, allowing it to apply to irreversible measurements and to be tested experimentally through expectation values.For stabilizer operations, the relevant expectations are restricted to 0%, 50%, or 100%.
  • A.1 Stabilizer Flows: A gate may have no flow for a given Pauli, multiple possible output flows, or measurement-dependent phase behavior, reflecting information loss and initialization choices.Initialization can map the identity on a nonexistent input to multiple valid output descriptions, including identity and Z.
  • A.1 Stabilizer Flows: Unitary flows can be obtained by conjugating Pauli operators, and a small generating set suffices because stabilizer flows form a group.The appendix gives product, chaining, folding, and tensor-product rules for composing flows across gates and circuits.
  • A.1 Stabilizer Flows: Stabilizer flow generators can be read from Clifford tableaux, while flows additionally express dissipative operations such as initialization and measurement.The appendix tabulates generators for Clifford operations and other stabilizer-formalism primitives.
  • A.2 Unsigned Stabilizers: Unsigned stabilizers discard phase signs when only commutation structure matters, making the analysis insensitive to time direction and simplifying dissipative operations.In this view, initialization and measurement can be treated as time-reversed counterparts.
  • A.5 KAK Decomposition and equivalence: ISWAP-like gates are relevant to surface-code compilation because identity-like and swap-like gates alone cannot create entanglement, whereas the proposed gate family supports an ISWAP-based circuit.The KAK discussion relates two-qubit gate equivalence to circuit choices for QEC.

B Constructs for the Repetition Code

The repetition code provides a simpler setting for developing walking and ISWAP constructions before applying the ideas to the surface code.

  • B Constructs for the Repetition Code: The repetition code is used pedagogically because its detecting regions are easier to visualize in two-dimensional space-time.The walking and ISWAP constructions were developed first for this simpler code.

B.1 The Stepping Repetition Code

Stepping repetition-code circuits exploit freedom in how half-cycle stabilizers are measured and reconstructed, allowing the logical code to move between physical qubits.

  • B.1 The Stepping Repetition Code: The repetition code also has a half-cycle state in which every qubit participates in code stabilizers, providing multiple valid mappings for stabilizer measurement.This half-cycle freedom underlies the alternative cycle constructions.
  • B.1 The Stepping Repetition Code: A valid repetition-code cycle can measure half-cycle stabilizers and reconstruct the state even when reconstruction uses different physical qubits.This follows from viewing the circuit as a transition between half-cycle states rather than fixed end-cycle states.
  • B.1 The Stepping Repetition Code: Step-code circuits are logically equivalent to the repetition code, use the same decoder, and can move the code by up to one physical qubit per cycle.They arise by allowing all four standard and non-trivial cycle choices.

B.2 CXSWAP Repetition Code

CXSWAP-based repetition-code cycles preserve the code while supporting both fixed qubit roles and stepping cycles that exchange data and measurement roles.

  • B.2 CXSWAP Repetition Code: CXSWAP gates support standard repetition-code cycles that preserve data and measurement roles and stepping cycles that exchange them.The two cycle families are illustrated through their detecting-region structures.
  • B.2 CXSWAP Repetition Code: The CXSWAP construction is presented with cycle circuits and detecting regions for distance-3 codes, including both standard and stepping variants.The figures compare the resulting detecting-region patterns across the cycle choices.

C Sliding Surface Codes for Logical Compilation

Sliding lets a dense register of logical patches shift in parallel, replacing lattice surgery’s quadratic space-time cost with a lower-cost operation that requires an additional parallel qubit row.

  • Hardware implications: Sliding logical patches provides a higher-level lattice-surgery primitive for moving densely packed logical-qubit registers.This extends the role of time-dynamic patch motion beyond the circuit level into logical compilation.
  • Register shifting: Sliding shifts all logical patches in parallel for 2d cycles by distance d, enabling cheaper queue-like register operations.The operation is relevant when register bits are processed iteratively and then shifted.
  • Hardware implications: The walking circuit requires an additional qubit row parallel to the shift direction, without increasing the register’s overall consumed volume as it moves.Surrounding patches can wiggle in phase with the sliding operation.
  • Register shifting: 2NS space-time blocks replace the naive N^2 + NS cost for shifting a register by S distances when S < N.The sliding construction applies across all patches, whereas lattice-surgery shifts each patch serially.

D Numerical Benchmarking and Noise Model

The benchmarks use Stim with hardware-matched or simplified noise models selected by gate family, then extrapolate logical error rates to obtain teraquop footprints.

  • Footprint estimation: Teraquop footprints are obtained by fitting logical error rate versus code distance and extrapolating to 1 × 10^-12.The extrapolated code distance determines the plotted physical-qubit footprint.
  • Noise models: The noise tables define the channels and model-specific rules used to benchmark circuits compiled for CX, CXSWAP, CZ, and ISWAP gates.UniformDepolarizing covers CX-family circuits, whereas SI1000 covers CZ- and ISWAP-family circuits.
  • Noise models: CZ and ISWAP circuits use the SI1000 model, while CNOT and entangling-measurement constructions use UniformDepolarizing noise.The SI1000 model is augmented with an ISWAP gate assigned the same leading fidelity as CZ.

E Further Benchmarking

Further benchmarking organizes teraquop-footprint results by circuit family and error model across planar, toric, and entangling-measurement constructions.

  • Benchmark organization: Figures E.1–E.4 group teraquop footprints by planar or toric geometry, gate family, and the associated SI1000 or UniformDepolarizing model.The groups cover CZ or ISWAP planar circuits, CX or CXSWAP planar circuits, toric CX circuits, and entangling-measurement circuits.
  • Supplementary materials: The supplementary files provide circuit schedules, logical-error plots versus physical error rate and code distance, and raw benchmark data for each circuit.These materials are available with the paper and in the data repository.
  • Planar circuits: Each footprint measures the physical qubits needed for one code patch to reach a logical error rate of 1 × 10^-12 over a d × d × d block.The planar figures average memory experiments in both Z and X bases.
  • Toric circuits: Toric-boundary benchmarks use UniformDepolarizing noise and report the physical-qubit footprint required for the same 1 × 10^-12 logical-error target.The toric figures likewise average memory experiments in both Z and X bases.
  • Hybrid entangling operations: The hybrid-entangling benchmark includes 3-CZ_MZZ, 3-CX_MZZ_MXX, and TORIC-3-CX_MZZ_MXX under the models specified for each circuit.TORIC-3-CX_MZZ_MXX lacks a p = 1 × 10^-4 point because no errors were sampled above d = 4, preventing teraquop extrapolation there.

F Crumble Links

The appendix links benchmarked Stim circuits to Crumble, an interactive editor used to explore cycle circuits and visualize circuit-specific structure.

  • Interactive circuit editor: Crumble can import arbitrary Stim circuits and visualize colored polygons and propagated Pauli flows while exploring cycle circuits.The appendix presents the editor as a starting point for examining the benchmarked constructions.
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