Relaxing Hardware Requirements for Surface Code Circuits using Time-dynamics

1 Introduction

• The motivation is that stabilizer measurements decompose into time-varying native hardware layers, while logical operations also change QEC-circuit structure during execution.The paper therefore emphasizes circuit time dynamics beyond the static stabilizer description traditionally used for QEC codes.Source: §1 · p. 1
• Prior attempts to reduce connectivity or address hardware nonidealities often require greater cycle depth, alternative codes, or performance-harming overhead.Standard surface-code circuits otherwise offer four-fold local connectivity, four CNOT or CZ layers, realistic-noise performance, and efficient matching-based decoding [BK98; Den+02; Fow+12; Kri+22; Goo+22; Fow13b; Hig21].Source: §1 · pp. 1–2
• Directly designing circuits with detectors and detecting regions yields surface-code constructions that relax hardware demands while preserving essentially equivalent logical performance.The approach treats detecting regions as a time-dynamic generalization of code stabilizers and modifies detector dynamics in the standard surface-code circuit.Source: §1 · p. 2
• Three exemplar circuits use three couplings per qubit, ISWAP gates, or measurements on all physical qubits, while retaining four entangling-gate layers and essentially the same logical performance.These improvements target connectivity, native gate type, and leakage resilience, and are not mutually exclusive or exhaustive.Source: §1 · p. 2

1.1 Organization

• The paper presents three improved surface-code circuit families in Sections 3–5, benchmarks each against the standard circuit, and discusses combinations, 24 constructions, and further applications in Section 6.The surrounding material includes detecting-region background, hardware constraints, benchmarking methodology, appendices, supplementary figures, repositories, and circuit-generation and benchmarking code.Source: §1.1 · pp. 2–3

2.1 Mid-cycle states

• Stabilizer flows propagate Pauli terms through Clifford circuits, providing the formal basis for tracking changing states and detecting-region types.The stabilizer formalism transforms state stabilizers under each operation, while operations such as Hadamard gates can change a region from Z-type to X-type.Source: §2.1 · p. 3, §2.2.1 · p. 7
• The standard surface-code cycle passes through flag-like, brickwork, half-cycle, modified-brickwork, and pre-measure states before returning to the checkerboard end-cycle state.The half-cycle state is an unrotated surface-code state with the same distance as the end-cycle state but twice as many qubits and stabilizers.Source: §2.1 · p. 5
• Mid-cycle states provide checkpoints for analyzing circuit segments, shift attention from fixed qubit roles to detecting regions, and reveal alternative ways to map surface-code states.The half-cycle state can be mapped back to an end-cycle state in more ways than the standard circuit uses.Source: §2.1 · p. 5

2.2 Detectors and Detecting Regions

• A detector is a set of measurements with deterministic noiseless parity, and a detection event occurs when an error changes that parity across fault-tolerant stabilizer circuits and related QEC strategies.The framework also applies to single-shot QEC, cluster-state QEC, subsystem codes, and flag-qubit methods [Fuj14] [Bom15] [RHG06] [Bom+21] [Bac05] [Bra+12] [CR18] [CC19] [CR20].Source: §2.2 · p. 5

2.2.1 Examples of detecting regions

• A detecting region is the finite set of circuit locations and Pauli types to which a detector is sensitive, with anti-commuting inserted errors producing detection events.Detectors and regions are transformed into one another by propagating Pauli types backward through stabilizer flows and terminating on resets or measurements.Source: §2.2 · p. 5, §2.2.1 · p. 7

2.2.2 Overlapping structure of detecting regions

• Detecting regions overlap across neighboring cycles so errors can trigger multiple detectors, while their overlaps define error-graph edges and their terminating measurements define detector nodes.For repetition and surface codes, regions cover two neighboring cycles and the intervening code-stabilizer time-slice; matching decoders exploit the resulting graph structure [Den+02] [Fow13b] [Hig21].Source: §2.2.2 · pp. 7, 9

2 Concepts and Tools

• Detecting-region overlap naturally defines both the quantum error-correction code and its circuit, enabling fault-tolerant circuits to be designed directly rather than through static stabilizers.The broader framework tracks stabilizer propagation and uses detecting regions as a primitive for circuit construction.Source: §2 · p. 3, §2.2.2 · p. 9

2.2.3 Detecting Region Slices

• A detecting-region time-slice is a stabilizer of the instantaneous circuit state associated with a specific detector, but uncovered locations need not belong to a region when errors there cannot cause logical failure.This representation connects mid-cycle patterns to stabilizer tableaux and instantaneous stabilizer groups while excluding irrelevant locations such as post-measurement, pre-reset positions.Source: §2.2.3 · p. 9, Figure 4 · p. 9

2.3 Detecting Regions in the Surface Code

• Detecting regions reveal overlapping X- and Z-type structure, with each circuit location covered by two regions of each type and Y errors affecting four regions.This structure produces the two connected components of the surface-code error graph under X and Z errors.Source: §2.3 · p. 10, Figure 5 · p. 11
• Expanding and contracting detecting regions evolve differently, and failing to contract an expanded region enlarges overlaps and worsens logical performance.Tracking these region types is therefore important when constructing circuits.Source: §2.3 · p. 10

2.4 Boundaries

• Temporal logical initialization and measurement are obtained by resetting or measuring all qubits and deleting or terminating anticommuting or commuting detecting regions appropriately.The same strategy applies when circuits mix X- and Z-type stabilizer terms because their states remain CSS-like up to single-qubit rotations.Source: §2.4 · pp. 10, 12
• Efficient spatial boundaries are difficult to design, so the constructions iterate boundary gates until graph-like code distance is preserved and benchmarking is favorable.Different hardware or logical-packing constraints can motivate different boundary choices, including which qubits are measurable in parallel.Source: §2.4 · p. 12

2.5 Software Tools

• Stim and Crumble supported visualization, correctness checks, code-distance verification, boundary exploration, and benchmarking of these annotated circuits.Visualization of interlocking detection regions helped motivate the constructions, while Stim analyzed them without redesign despite their departure from traditional stabilizer-operator measurement circuits.Source: §2.5 · pp. 12–13

2.6 Hardware Requirements

• The hardware-focused constructions target lower-connectivity hex grids without swap overhead, ISWAP-based circuits, and leakage benefits without additional gate layers.Lower connectivity can ease couplings, crosstalk, on-chip structures, control lines, and qubit-frequency constraints; ISWAP may also be higher fidelity than CZ in some superconducting architectures [Fox+20].Source: §2.6 · p. 13
• The work opens possibilities for tailoring surface-code circuit decompositions to hardware strengths rather than designing circuits without hardware feedback.The targeted constraints include connectivity, entangling-gate choice, and correlated hardware errors.Source: §2.6 · p. 13

3 Hex-grid Surface Code Circuits

• The hex-grid circuit preserves code distance and entangling-layer count while reducing each qubit’s required neighboring couplers from four to three.This provides a lower-connectivity alternative to the usual square-grid surface-code circuit.Source: §3 · p. 14

3.1 Bottom-up Circuit-Focused Construction

• Alternating two fold-and-reverse cycle circuits measures all half-cycle stabilizers every two rounds while using only the couplings of a hex grid.The cycles exchange expanding and contracting detecting regions, so repeating one cycle would leave half the stabilizers unmeasured.Source: §3.1 · pp. 14–15, Figure 6 · p. 18

3.2 Top-down Stabilizer-Focused Construction

• The brickwork construction measures disjoint two-body stabilizers and switches between two- and six-body stabilizers, producing two distinct cycles that naturally embed on a hex grid.Two-body measurements use a CNOT–measurement–CNOT decomposition, while stabilizer exchange uses two CNOT layers.Source: §3.2 · p. 15, Figure 7 · p. 19

3.3 Boundaries

• Boundary construction uses flat weight-3 and spiky weight-1 detecting-region terminations, found by iterative gate removal and termination-point manipulation without changing gate-layer count.These boundaries complete diagonal detecting-region columns while preserving graph-like code distance.Source: §3.3 · p. 16

3.4 Benchmarking

• Benchmarking numerically simulates a superconducting-hardware quantum memory using relative experimental error rates, with teraquop footprint as the reported performance metric.The teraquop footprint measures physical qubits needed for a 1 × 10^-12 logical error rate over a d × d × d space-time block; Figure 9 compares standard 4-CZ and hex-grid 3-CZ circuits.Source: §3.4 · p. 16, Figure 9 · p. 20

3.5 Summary

• The hex-grid circuit reduces connectivity with minimal logical-performance cost, while also supporting heavy-hex, semi-heavy-hex, broken-coupling square-grid, and heterogeneous-entangling-operation architectures.The paper notes potential hardware benefits alongside possible yield-related code-distance challenges for hex-grid architectures.Source: §3.5 · pp. 16–17

4 ISWAP Surface Code Circuits

• The construction enables surface-code operation with native ISWAP-like gates while preserving the usual code distance and number of entangling layers.This avoids hardware overhead associated with requiring a CNOT-like native interaction.Source: §4 · p. 21

4.2 Circuit Construction

• Detecting regions overcome ISWAP-induced qubit motion by tiling across modified stabilizer patterns, allowing alternating cycles to implement the surface code.The construction uses CXSWAP for conceptual clarity; the ISWAP circuit differs only by single-qubit gates, while data and measure qubits shift in opposite directions.Source: §4.2 · pp. 21–23

4.3 Boundaries

• Boundary construction adapts rotated surface-code boundaries to the circuit’s distortion while preserving graph-like code distance, though benchmarked ISWAP boundaries differ slightly from the simpler CXSWAP version.The benchmarked variant retained two additional corner qubits and did not preferentially schedule measurements on neighboring qubits; both variants showed essentially the same performance as their standard counterparts.Source: §4.3 · p. 23

4.5 Summary

• The circuit completes the ISWAP-like two-qubit Clifford implementation class for surface-code error correction, offering an alternative for architectures with natural ISWAP gates.ISWAP-like gates both move quantum information and generate entanglement, unlike the non-entangling Identity-like and SWAP-like classes.Source: §4.1 · p. 21, §4.5 · p. 24

4.4 Benchmarking

• The ISWAP circuit has an essentially identical teraquop footprint to the standard surface-code circuit in quantum-memory benchmarks.Figure 13 compares 4-CZ and 4-ISWAP footprints for logical error rate 1 × 10−12 over d × d × d space-time blocks under the SI1000 noise model.Source: §4.4 · p. 24, Figure 13 · p. 25

5 Walking Surface Code Circuits

• Walking circuits exchange measure and data qubit roles without additional gates while moving the logical patch on the underlying physical qubit grid.This offers a low-overhead alternative for mitigating leakage and supports new logical-patch behaviours.Source: §5 · p. 26, §5.1 · p. 26, §5.6 · p. 30

5.1 Leakage Mitigation in QEC Experiments

• Leakage is easier to remove from measure qubits because measurement releases stored quantum information and permits unconditional reset, whereas direct data-qubit removal adds error sources.Role exchange allows each physical qubit to be measured and leakage-cleared every second cycle, assuming entangling interactions do not move leakage.Source: §5.1 · p. 26

5.2 Circuit Construction

• The stepping trick reverses the final CNOT layer, selecting an alternative detecting-region pairing that contracts onto previously data qubits and exchanges physical qubit roles while preserving logical structure.The same trick can be applied to hexagonal circuits and repetition codes.Source: Figure 14 · p. 27, §5.2 · p. 28

5.3 Boundaries

• Walking boundaries create detecting regions at leading edges and measure them out at trailing edges, preserving graph-like code distance while avoiding problematic hook errors.Trailing-boundary measurements move the logical observable with the patch, and shifted or rotated step cycles enable motion in all four cardinal directions.Source: §5.3 · p. 28

5.4 Behaviours for the Logical Patch

• Step cycles support wiggling in place, gliding continuously in one direction, and sliding through alternating perpendicular steps to move a patch laterally.These behaviours exchange roles with minimal qubit overhead and can aid routing and logical compilation.Source: §5.4 · pp. 28, 30, Figure 16 · p. 30

5.5 Benchmarking

• 1000–3000-qubit teraquop footprints at an aspirational limiting error rate of 1 × 10−3 are qualitatively similar across walking behaviours, though standard surface code performs slightly better.Wiggling slightly outperforms gliding and sliding; relative performance depends on the assumed error model.Source: §5.5 · p. 30, Figure 17 · p. 31

5.6 Summary

• Without leakage errors, walking circuits perform comparably to the traditional surface code, while their role exchange may provide additional leakage advantages that remain to be simulated and quantified.The technique is intended to complement direct data-qubit leakage removal rather than eliminate leakage entirely.Source: §5.1 · p. 26, §5.6 · p. 32

6.1 Further Constructions

• The constructions can be combined to produce circuits with multiple hardware benefits, including hex-grid embedding, ISWAP gates, and data–measure exchange, with exact circuits and benchmarking provided.Additional heavy-hex, semi-heavy-hex, and hybrid circuits further target reduced connectivity, parallelization, or pair-measurement hardware.Source: §6.1 · p. 32
• Hybrid circuits outperform equivalent all-two-qubit-gate circuits under the assumed equal-strength error model, but hardware-specific noise will determine their practical advantage.The heavy-hex circuit also outperforms the heavy-hex and heavy-square codes, while the semi-heavy-hex circuit uses three entangling layers per measurement cycle.Source: §6.1 · pp. 32–33

6.2 Open Problems

• Open problems include extending the approach beyond surface codes, ensuring spatial compatibility with other circuits, refining boundaries for hardware and packing constraints, and benchmarking realistic noise effects.The authors specifically highlight color, honeycomb, and biased-noise codes, subsystem-code compatibility, boundary optimization, leakage, crosstalk, and hardware-accurate gate errors.Source: §6.2 · pp. 33–34

6.3 Outlook

• The work introduces direct space-time QEC circuit construction based on detecting regions, giving hardware engineers new freedoms beyond decomposing static stabilizer codes.Slicing detecting regions generates circuits while tracking stabilizers throughout the QEC circuit.Source: §6.3 · p. 34

6.3.1 A note on recent progress in the space-time approach

• Recent space-time fault-tolerance work connects detecting regions with Pauli webs and spacetime-code detectors, supporting spacetime structure as a broader paradigm for fault-tolerant quantum computing.[Bom+23] uses the ZX calculus across multiple computing models, while [DP23] constructs spacetime codes for arbitrary Clifford circuits.Source: §6.3.1 · p. 34

• McEwen and Gidney conceived using detecting regions to produce new surface-code circuits, while Gidney developed vital software tools including Stim.These tools supported exploration and development of the concepts and constructions.Source: Contributions · p. 34
• The authors developed initial wiggling, walking, ISWAP, and hex-grid surface-code circuits through contributions from McEwen, Bacon, and Gidney.McEwen conceived and built the initial wiggling and walking circuits; Bacon and Gidney built the initial ISWAP circuits; Gidney conceived and built the initial hex-grid circuits.Source: Contributions · pp. 34–35
• All authors synthesized the ideas into a coherent narrative centered on overlapping detecting regions, and McEwen compiled the manuscript.Source: Contributions · p. 35

A Stabilizer Formalism and Detecting Regions

• Stabilizers describe quantum states as signed Pauli terms whose eigenvalue matches the stabilizer sign, providing the basic language for analyzing the Clifford circuits used in error correction [Got97].Operations in stabilizer circuits can be understood through their transformations of these stabilizers [Got98] [AG04] [Gid21].Source: A Stabilizer Formalism and Detecting… · p. 39, §A.1 · p. 40

A.1 Stabilizer Flows

• Stabilizer flows generalize stabilizers to describe how Clifford operations, preparations, measurements, resets, and other dissipative operations transform Pauli terms.They avoid requiring inverse or controlled versions of irreversible operations and can be experimentally checked through measurement probabilities.Source: §A.1 · pp. 40, 42
• Stabilizer flows form a group, so flows can be generated, combined, chained, and composed through products, series, and tensor products.For unitary gates, flow generators can be obtained from the stabilizer tableau, while the flow formalism also covers initialization and measurement.Source: §A.1 · pp. 40, 42, §A.3 · p. 43

A.2 Unsigned Stabilizers

• Unsigned stabilizers discard phase signs, simplifying analysis because commutation is sign-independent and sign computation can be substantially more costly.This view also removes dependencies on time direction by assigning reversed counterparts to dissipative operations such as initialization and measurement.Source: §A.2 · pp. 42–43

A.4 Detecting Regions

• A detecting region is a set of circuit locations decorated with Pauli terms that obeys stabilizer flows and terminates on measurements, resets, initializations, or destructive measurements.The measurements on which it terminates define the corresponding detector, and detector choices are not unique because products of detectors are also valid.Source: A Stabilizer Formalism and Detecting… · p. 39, §A.4 · pp. 43–44

A.5 KAK Decomposition and equivalence

• The KAK decomposition places Clifford two-qubit interactions into four equivalence classes: identity-like, CNOT-like, SWAP-like, and ISWAP-like.On hardware with good single-qubit operations, KAK-equivalent interactions are effectively interchangeable, but identity-like and swap-like gates cannot create entanglement.Source: §A.5 · p. 44
• ISWAP-like gates are therefore a viable entangling interaction for surface-code circuits, which the paper develops in Section 4 as an alternative to the commonly used CNOT-like gates.The appendix notes that CNOT-like gates are widely used for surface-code circuits, whereas the proposed construction uses ISWAP-like gates.Source: §A.5 · p. 44

B Constructs for the Repetition Code

• Walking and ISWAP constructions were developed first for the simpler repetition code before progressing to the surface code.The repetition code served as a practical development case for both constructions.Source: B Constructs for the Repetition Code · p. 44
• The repetition-code constructions are included for their pedagogical value.Source: B Constructs for the Repetition Code · p. 44
• Overlapping detecting regions are easier to visualize in the repetition code’s 2D space-time.Source: B Constructs for the Repetition Code · p. 44

Half-cycle construction

• The cycle design proceeds from half-cycle to half-cycle by measuring half of the half-cycle stabilizers as one-body stabilizers and reconstructing the half-cycle state.Any strategy that measures half-cycle stabilizers and then reconstructs the state constitutes a reasonable cycle, even when reconstruction uses different physical qubits.Source: §B.1 · pp. 44–45

Step code circuits

• Step code circuits are logically equivalent to the repetition code, use the same decoder, and can move the code up to 1 physical qubit in either direction each cycle.They arise by allowing four possible cycles, including non-trivial cycles that construct and deconstruct half-cycle stabilizers on different qubits.Source: §B.1 · p. 45

CXSWAP cycle circuits

• CXSWAP gates implement bit-flip repetition-code cycles, including standard cycles that preserve qubit roles and stepping cycles that exchange them.The construction is illustrated in Figure B.2.Source: §B.2 · p. 45, Figure B.2 · p. 47

Detecting regions

• The distance-3 CXSWAP step-code sequence produces detecting regions with the same size and overlapping structure as the standard repetition code.Figure B.2 uses the sequence [Standard Down, Standard Down, Step up, Standard Up].Source: Figure B.2 · p. 47

Boundary corrections

• Stepping boundaries include effective X-basis measurement and Z-basis classical feedback to correct the distance-1 X observable.These corrections are unnecessary when treating the repetition code as a classical code.Source: Figure B.2 · p. 47

Application

• The sliding behavior introduces a lattice-surgery-level primitive that can make selected logical operations cheaper by moving logical patches laterally.The application demonstrates this freedom on a densely packed linear register.Source: C Sliding Surface Codes for Logical… · p. 48

Motivation

• Shifting dense logical registers supports iterative algorithms that consume register bits as a queue, allowing compilation to operate on the least-significant bit before shifting.Register shifting is a common lattice-surgery compilation operation.Source: C Sliding Surface Codes for Logical… · p. 48

Problem

• Serial lattice-surgery shifting costs N^2 + NS in d^3 units for an N-patch register shifted by S distances, making short shifts of large registers especially expensive.Each logical patch must be shifted serially.Source: C Sliding Surface Codes for Logical… · p. 48

Cost comparison

• 2NS versus N^2 + NS space-time blocks: sliding shifts all N logical patches by distance S in parallel, reducing cost when S < N.The sliding circuit performs a distance-d shift in 2d cycles and requires an additional parallel qubit row.Source: Figure C.1 · p. 48, C Sliding Surface Codes for Logical… · p. 48

Simulation and decoding

• Numerical simulations used Sinter with up to 1 × 10^8 shots per circuit, stopping after 1 × 10^3 logical errors, and an internal correlated-error-aware matching decoder.Decoded X- and Z-basis memory results were combined into a statistic for a combined XZ basis by projecting the likelihood that neither basis experienced a logical error.Source: D Numerical Benchmarking and Noise Model · p. 49

Teraquop footprint

• Teraquop footprints are obtained by fitting logical error rate versus code distance and extrapolating to a logical error rate of 1 × 10^-12.Maximum-likelihood envelopes quantify uncertainty in logical-error-rate, lambda, and teraquop-footprint estimates.Source: D Numerical Benchmarking and Noise Model · p. 49

Noise models

• CZ and ISWAP circuits are benchmarked with SI1000 noise, while CX and CXSWAP circuits use UniformDepolarizing noise.SI1000 is inspired by superconducting transmon-array errors; ISWAP is assigned the same leading fidelity as CZ. [GNM22]Source: D Numerical Benchmarking and Noise Model · p. 49, Table D.2 · p. 50
• Table D.2 provides error-model details: circuits compiled for CX or CXSWAP gates are benchmarked using UniformDepolarizing, whereas circuits compiled for CZ or ISWAP gates use SI1000.Table D.1 contains definitions of the noisy gates.Source: Table D.2 · p. 50

Benchmark organization

• Teraquop footprints benchmark all constructions across planar CZ/ISWAP, planar CX/CXSWAP, toric CX, and entangling-measurement circuits.The benchmarks use SI1000 for planar CZ/ISWAP circuits and UniformDepolarizing for the other listed two-qubit-gate groups.Source: E Further Benchmarking · p. 50

Noise-model comparison

• Entangling-measurement circuits perform significantly better than circuits using only two-qubit gates because the noise models assign entangling measurements the depolarizing error of two-qubit gates.This comparison follows the noise-model treatment described in Appendix D.Source: E Further Benchmarking · p. 50

Reproducibility

• Supplementary materials provide schedules, logical-error plots versus physical error rate and code distance, raw benchmark data, and reproducible generation code.Schedules are automatically generated with Stim’s diagram functionality, and the circuits are included in the data repository.Source: E Further Benchmarking · p. 50

Teraquop metric

• 1 × 10−12 logical error over a d × d × d space-time block is the target used to measure each circuit’s required physical-qubit footprint.Figures E.1–E.4 average memory experiments in both Z and X bases, with circuit-specific noise models and details given in Table 1.Source: Figure E.1 · p. 51, Figure E.2 · p. 52, Figure E.3 · p. 53

F Crumble Links

• Crumble imports arbitrary Stim circuits and visualizes colored polygons and Pauli flows, supporting interactive exploration of the presented circuits.The appendix links benchmarked Table 1 circuits with a detecting region already marked; other circuits can be imported from the data or code repositories.Source: F Crumble Links · p. 55
• The appendix provides Crumble links for the 4-CX, 3-CX, 4-CXSWAP, and CX-GLIDING circuits.Source: F Crumble Links · p. 55