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ChipGPT: How far are we from natural language hardware design

Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li

arXiv:2305.14019v4cs.AIcs.ARcs.PL

TL;DR

Hardware logic design still requires substantial expertise and manual effort, while LLM outputs are not automatically reliable or PPA-optimized for EDA workflows. ChipGPT addresses this gap with a four-stage, zero-code framework that generates prompts, produces and refines Verilog, and searches candidate designs without retraining. The evaluation reports improved programmability and scalability, a 9.25-fold code-volume reduction versus HLS, and a 5.32-fold reduction versus Chisel.

  • Problem

    Manual hardware design is labor-intensive, and LLMs lack reliable HDL prompting, hardware-level correctness, and PPA awareness for seamless EDA integration.

  • Method

    ChipGPT uses prompt management, LLM-generated Verilog, output correction and optimization, and enumerative search in a four-stage framework without retraining or modifying LLM weights.

  • Results

    ChipGPT improves programmability and scalability, while reducing code volume by 9.25 times versus HLS and 5.32 times versus Chisel.

  • Takeaways & Limitations

    The evaluation supports the feasibility of using natural-language specifications with current LLMs for automated chip logic design and broader design optimization.

Abstract

from arXiv · show

As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficiency logic design via natural language interaction. To estimate the potential of the hardware design process assisted by LLMs, this work attempts to demonstrate an automated design environment that explores LLMs to generate hardware logic designs from natural language specifications. To realize a more accessible and efficient chip development flow, we present a scalable four-stage zero-code logic design framework based on LLMs without retraining or finetuning. At first, the demo, ChipGPT, begins by generating prompts for the LLM, which then produces initial Verilog programs. Second, an output manager corrects and optimizes these programs before collecting them into the final design space. Eventually, ChipGPT will search through this space to select the optimal design under the target metrics. The evaluation sheds some light on whether LLMs can generate correct and complete hardware logic designs described by natural language for some specifications. It is shown that ChipGPT improves programmability, and controllability, and shows broader design optimization space compared to prior work and native LLMs alone.

I. INTRODUCTION

ChipGPT targets the effort, correctness, and optimization limitations of natural-language hardware design by placing prompt and output management around an LLM. Its four-stage framework generates and refines Verilog without retraining, then supports design selection and reports improved programmability and scalability.

  • Manual logic design requires substantial effort, motivating higher-level interfaces and ultimately natural-language specifications for more accessible chip development.
  • Existing synthesis methods generate Verilog from formal representations or input-output pairs, while LLMs accept natural-language input but remain difficult to integrate into EDA workflows.
  • A prompt manager improves generated prompts, while an output manager uses machine and human feedback to correct programs and collect candidate designs for later selection.
  • ChipGPT uses a scalable four-stage zero-code framework that interfaces natural-language specifications with LLM-generated Verilog and reduces manual design effort.
  • ChipGPT avoids retraining or modifying LLM weights and adds post-LLM search to address power, area, and performance limitations.
  • ChipGPT improves programmability and scalability compared with previous agile chip logic design methods and native ChatGPT.

II. BACKGROUND AND MOTIVATION

Agile hardware design methods use higher-level representations to improve productivity, but existing approaches still require either hand-crafted programming, complete examples, or difficult formal specifications. ChipGPT is positioned as a natural-language alternative evaluated across expressiveness, soundness, and completeness.

  • Agile hardware design methods: Agile chip design approaches comprise programming-language-based and program-synthesis-based workflows.Programming-language methods include HLS and Chisel, while synthesis methods generate programs from specifications, examples, or input-output pairs.
  • Programming-language-based methods: HLS and Chisel improve RTL productivity through higher-level languages but still require hand-crafted design programming rather than natural expression.
  • Program-synthesis-based methods: Program synthesis can reduce manual development effort, but inductive synthesis may be incomplete and deductive synthesis requires difficult correctness proofs.
  • Comparison framework: ChipGPT uses natural language as its input representation, which the paper identifies as the most efficient representation among the compared methods.
  • Productivity dimensions: The paper evaluates agile design productivity using expressiveness, soundness, and completeness as dimensions of comparison.Soundness concerns correctness, while completeness concerns how much of the design space a method covers.
  • LLM-based design: The selected transfer-learning approach is in-context learning, which elicits responses from a pretrained LLM without retraining.Its prompt manager uses templates to guide responses through natural-language context.

D. Motivation

The motivation is to address gaps between LLM-generated natural-language hardware descriptions and practical chip-design requirements. ChipGPT targets ambiguous specifications, PPA-unaware generation, and limited scalability through coordinated preprocessing and postprocessing methods.

  • Ideal agile method: The ideal agile method combines natural-language expression, broad hardware-generation coverage, and guaranteed correctness.
  • Motivation: LLMs enable natural-language hardware descriptions but may produce programs lacking soundness, making correctness central to chip-design adoption.
  • Challenge 1: ambiguous inputs: Ambiguous specifications make it difficult to prompt LLMs for desired HDL modules and integrate their outputs into chip-design flows.ChipGPT addresses this challenge with specification splitting and template-based prompt management.
  • Framework response: ChipGPT’s framework overview separates implicit preprocessing control from explicit postprocessing control.Specification Split and Prompt Manager perform preprocessing, while Output Manager and Enumerative Search perform postprocessing.
  • Challenge 2: PPA awareness: LLMs are PPA-agnostic, so their generated programs may be intuitively good without being optimized for power, area, and performance.The output manager is proposed to address this limitation.
  • Challenge 3: scalability: LLM-generated programs are limited to known modules, constraining the generation of unlimitedly nested architectures with customized submodules.The proposed response is a bottom-top method for improving scalability.

III. AUTOMATIC CHIP GENERATION FRAMEWORK

ChipGPT is an EDA frontend that converts chip specifications into Verilog through controlled prompting and iterative output handling. Its framework avoids direct raw-program modification, instead generating multiple versions and searching them for PPA-oriented output selection.

  • Framework purpose: ChipGPT takes a chip specification as input and generates a target hardware-module description as a Verilog program.
  • Output control: ChipGPT controls generation through context prompts, code-query prompts, and post-generation program handling, emphasizing prompt-based and search-based control.
  • Iterative generation: Rather than directly amending raw GPT programs, ChipGPT generates multiple code versions and refines them to obtain the final output.
  • Four-stage flow: Each iteration applies preprocessing before GPT invocation and postprocessing afterward to address descriptive information and design constraints.The output manager and search modules operate after generation, including selection based on power, performance, and area.
  • Pre-processing: Specification splitting translates chip specifications into a formal and unambiguous form.
  • Pre-processing: Specification serialization converts irregular split partitions into an available GPT input sequence within the prompt manager.
  • Post-processing: The output manager improves the quality of the code generated by the GPT model.
  • Post-processing: Enumerative search ranks GPT-generated programs and identifies a final version according to performance, power, and area requirements.

A. Specification Split

ChipGPT splits chip specifications into structured components and uses a prompt manager to serialize them into an interconnected query sequence for GPT-based Verilog generation.

  • Specifications are manually divided into module, test, interface, and input-output example descriptions, while extraneous content is discarded.
  • Input-output examples are excluded from prompts because they are too complicated for the transformer model, then used during post-processing to verify correctness.
  • The interface defines input and output ports, the function describes module behavior, and compose specifies top-level module composition.
  • The prompt manager formats specifications into structured prompts so GPT can capture implementation details and module purpose.
  • Its template-based query sequence establishes a Verilog environment, generates basic modules, and then creates a top module connecting those submodules.

1) Principle for Interface Model:

The interface model makes port declarations explicit in prompts, while the post-addition principle delays cross-module handshake information until after the initial raw program is generated.

  • 1) Principle for Interface Model:: Including interface declarations preserves port specifications such as bit widths and array sizes, enabling generated modules to integrate with testbenches.
  • 1) Principle for Interface Model:: Port definitions comprise direction, data width, variable name, array size, and port description.
  • 1) Principle for Interface Model:: Variable names are especially important because GPT uses them to infer the appropriate program structure.
  • 2) Post Addition Principle:: Handshake declarations are appended after the first raw program rather than included in the initial interface prompt.
  • 2) Post Addition Principle:: This post-addition ordering produced a correct implementation in the example, whereas including handshake signals in the same prompt produced an incorrect one.

3) Module Composition Principle:

The bottom-up composition principle declares submodule interfaces before the top module, improving the information available for hierarchical generation; correction managers then validate raw programs.

  • 3) Module Composition Principle:: Directly prompting for a top module leaves GPT without information about the submodules it must reference.
  • 3) Module Composition Principle:: The bottom-up composition principle declares submodule interfaces before the top module so GPT can reference their ports during generation.
  • 3) Module Composition Principle:: For the complex-module example, composition enabled correct submodule implementations that were incorrect when modules shared one prompt.
  • Correction Manager: A correction manager uses compiler and simulator feedback first, followed by manual checking, to correct raw GPT programs.
  • Correction Manager: Human feedback may be needed when machine correction stalls at compile errors or when machine-provided examples are incomplete.

2) Cost Manager:

ChipGPT adds a cost manager because GPT’s ranking does not consistently reflect power, performance, and area, so design-tool measurements guide target-dependent search.

  • 2) Cost Manager:: GPT lacks comparable PPA configurations and provides only general ranking, motivating a cost manager for PPA optimization.
  • 2) Cost Manager:: The cost manager measures each generated program with design tools, appends PPA results to a program list, and searches for the target version.
  • 2) Cost Manager:: GPT ranking does not consistently match PPA ranking, so the selected final program depends strongly on the chosen target.

IV. EVALUATION

The evaluation compares ChipGPT with ChatGPT and agile design methods across workloads, using PPA, code quality, programmability, and human-correction measures.

  • The research questions examine PPA and programmability against ChatGPT, workload sensitivity, prompt-principle ablations, and the effect of human feedback.
  • Design Compiler with 65nm technology measures power and area, while simulation provides cycle counts and cloc measures code lines.
  • Programmability measurement: The evaluation defines quality = raw + correct − prompt, combining generated lines, human-corrected lines, and prompt-query count.Here, raw is generated-program lines, correct is human-modified lines, and prompt is the number of queries.
  • The study compares ChipGPT with native ChatGPT and conventional agile methods across workloads of differing architectural complexity.The benchmarks include composition, complex single-module, and simple single-module workloads.

4) Baseline:

Across baseline comparisons and workloads, ChipGPT reduces code volume, improves code quality, and optimizes PPA most clearly for complicated designs while requiring limited correction.

  • Baseline: PPA comparisons show workload-dependent trade-offs: HLS can reduce area and power relative to Chisel for matrix multiplication but may have much higher latency.The reported scheduling difference is that HLS favors state machines, whereas Chisel counterparts may use pipelines.
  • Baseline: 9.25 times less code than HLS and 5.32 times less than Chisel are generated on average by ChipGPT for equivalent designs.
  • Baseline: 2.01 times fewer incorrect code lines represent the maximum quality improvement of the framework over the original ChatGPT model.
  • Baseline: ChipGPT improves program quality across workloads and primarily optimizes PPA for complicated designs, while simple workloads offer limited PPA opportunity.The stated reasons for limited simple-workload benefits are a small raw-candidate pool and limited optimization opportunity.
  • Baseline: Less than 10 lines require correction across workloads, with no feedback needed for a 4x1 multiplexer and fewer than three corrections in vector matrix multiplication programs.Complex modules and integrated accelerators up to 100 lines require only minor corrections in the reported examples.

V. CONCLUSION

ChipGPT explores automatic chip logic design from natural-language specifications through an LLM-integrated framework without retraining. It reports lower code volume than traditional agile methods and improved PPA and correctness versus original ChatGPT.

  • ChipGPT uses natural-language specifications for automatic chip logic design and integrates language models into EDA tools without retraining.
  • Code volume is reduced by 5.32-9.25 compared with traditional agile methods.
  • Area is reduced by 47% compared with original ChatGPT in area-target optimization mode, while correctness improves from probable right to rule right.
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