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Disentangling Hype from Practicality: On Realistically Achieving Quantum Advantage
Torsten Hoefler, Thomas Haener, Matthias Troyer
TL;DR
The paper asks when quantum computing can achieve practical speedups over classical hardware. It models operation throughput and oracle costs across hypothetical quantum and classical chips, finding that the comparison depends strongly on oracle parallelism and hardware assumptions.
Problem
The paper examines how operation costs and oracle structure determine whether quantum computers can achieve practical speedups over classical chips.
Method
The analysis estimates classical and quantum operation throughputs and compares runtime models for polynomial quantum speedups under explicit hardware and oracle assumptions.
Results
10.5k op/s is the estimated rate for the hypothetical quantum chip’s fp16 multiplier under the stated construction and resource assumptions.
Takeaways & Limitations
Practical quantum speedups require accounting for oracle operation counts, execution parallelism, and the relative throughput of classical and quantum hardware.
Takeaways & Limitations
The comparison assumes massively parallel oracle execution on both classical and quantum computers, an assumption that may not hold for every oracle.
Abstract
from arXiv · showhide
Quantum computers offer a new paradigm of computing with the potential to vastly outperform any imagineable classical computer. This has caused a gold rush towards new quantum algorithms and hardware. In light of the growing expectations and hype surrounding quantum computing we ask the question which are the promising applications to realize quantum advantage. We argue that small data problems and quantum algorithms with super-quadratic speedups are essential to make quantum computers useful in practice. With these guidelines one can separate promising applications for quantum computing from those where classical solutions should be pursued. While most of the proposed quantum algorithms and applications do not achieve the necessary speedups to be considered practical, we already see a huge potential in material science and chemistry. We expect further applications to be developed based on our guidelines.
METHODS
The methods compare the quantum computer with a single microprocessor chip modeled on the NVIDIA A100 GPU.
- The comparison baseline is a single A100-like microprocessor chip fabricated in TSMC’s 7nm N7 process, measuring around 850 mm^2 with approximately 54.2 billion transistors and a 0.7 ns cycle time.The chip serves as the classical comparison system for the reported numbers.
Determining peak operation throughputs
The section estimates operation throughputs for classical GPUs, specialized ASICs, and hypothetical quantum computers across logical, fp16, and int32 operations. For a 10-bit fp16 multiplier, the quantum design achieves only 10.5 kop/s with 10 μs cycle time and 200-cycle latency.
- Determining peak operation throughputs: Table 1 compares logical, 16-bit floating-point, and 32-bit integer operation throughputs across the modeled architectures.The methodology can also model other datatypes.
- Classical Special Purpose ASIC: The classical ASIC analysis models an A100-sized specialized circuit using execution units measured in gate equivalents, including approximately 7 kGE for a 16-bit floating-point unit and 18 kGE for a 32-bit integer unit.The analysis assumes similar underlying technology to the classical GPU.
- Hypothetical future quantum computer: The quantum fp16 multiplier requires 200 CCZ states, 50 data qubits, and 473.5 total qubits per multiplier, with 5.5 factories pipelining magic-state production.The construction uses N single-bit controlled adders and sequential multiplication to fit more units on one chip.
- Hypothetical future quantum computer: 10.5 kop/s is the estimated throughput for the quantum 10-bit fp16 multiplier with 10 μs cycle time and 200-cycle latency.The estimate uses 10,000 logical qubits and 21 parallel multiplier units.
A note on parallelism
The comparison assumes massively parallel oracle execution for both classical and quantum computers; without such parallelization, the comparison becomes more favorable toward the quantum computer.
- A note on parallelism: The analysis assumes massively parallel oracle execution for both computers, with oracle depth set to one.If oracle depth equals work in the worst case, the comparison shifts toward the quantum computer.
- A note on parallelism: At 2 GHz, restricting a classical computer to one operation per cycle would cause about a 100,000-fold slowdown for fp.
Determining maximum operation counts per oracle call
The analysis derives the maximum number of operations per oracle evaluation that still permits a quantum speedup within 106 seconds. It models classical and quantum runtimes using oracle-operation counts, invocation counts, and per-operation execution times.
- Determining maximum operation counts per oracle call: Within 106 seconds, a single classical chip can perform 0.55 fp16, 0.22 int32, and 77.4 bin Zop operations, compared with 7, 4, and 2,350 Gop on a quantum chip.These operation-rate estimates are used as the basis for calculating allowable oracle sizes.
- Determining maximum operation counts per oracle call: The framework compares classical time T_c = N^k·M·t_c with quantum time T_q = N·M·t_q, where M is operations per oracle call and N is the required invocation count.The quantum advantage condition is that the quantum runtime is both faster than the classical runtime and within 106 seconds.
- Determining maximum operation counts per oracle call: The resulting calculation determines the maximal number of basic operations per oracle evaluation for which the quantum computer retains a practical speedup.This maximum is obtained by imposing both the runtime limit and the requirement that the quantum solution be faster than the classical one.
Determining I/O bandwidth
The I/O bandwidth estimate uses NVIDIA’s A100 datasheet for classical chips and assumes one quantum gate per bit of I/O across 10,000 qubits, yielding B≈10,000.
- The estimate uses NVIDIA’s A100 datasheet to specify classical-chip I/O bandwidth.
- Assuming one quantum gate per bit of I/O and using all 10,000 qubits for reading and writing yields B≈10,000.