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High-threshold and low-overhead fault-tolerant quantum memory

Sergey Bravyi, Andrew W. Cross, Jay M. Gambetta, Dmitri Maslov, Patrick Rall, Theodore J. Yoder

arXiv:2308.07915v2quant-phcs.ET

TL;DR

Scalable quantum computing requires error correction because quantum information is fragile and physical noise is difficult to eliminate. The paper develops an end-to-end fault-tolerant memory protocol using high-rate LDPC codes, syndrome circuits, and decoding. Its codes achieve a pseudo-threshold close to 1% while substantially reducing qubit overhead, although some fault-tolerant logical-operation constructions remain resource-intensive.

  • Problem

    Quantum information is fragile under diverse noise sources, so practical scalable quantum computing requires fault-tolerant error correction with suitable thresholds and hardware overhead.

  • Method

    The paper constructs Bivariate Bicycle LDPC codes with syndrome measurement circuits, efficient BP-OSD decoding, and fault-tolerant memory operations.

  • Results

    A pseudo-threshold close to 0.007 is achieved for 144-qubit and 288-qubit codes, nearly matching the surface code while offering nearly 15x lower qubit overhead in the relevant error-rate regime.

  • Takeaways & Limitations

    The proposed LDPC protocols provide a low-overhead route toward fault-tolerant quantum memory on near-term superconducting-quantum hardware.

  • Takeaways & Limitations

    Ancilla systems for fault-tolerant logical operations can add 1380 qubits to the [[144, 12, 12]] code, and their resource optimization is left for future work.

Abstract

from arXiv · show

Quantum error correction becomes a practical possibility only if the physical error rate is below a threshold value that depends on a particular quantum code, syndrome measurement circuit, and decoding algorithm. Here we present an end-to-end quantum error correction protocol that implements fault-tolerant memory based on a family of LDPC codes with a high encoding rate that achieves an error threshold of $0.8\%$ for the standard circuit-based noise model. This is on par with the surface code which has remained an uncontested leader in terms of its high error threshold for nearly 20 years. The full syndrome measurement cycle for a length-$n$ code in our family requires $n$ ancillary qubits and a depth-7 circuit composed of nearest-neighbor CNOT gates. The required qubit connectivity is a degree-6 graph that consists of two edge-disjoint planar subgraphs. As a concrete example, we show that 12 logical qubits can be preserved for nearly one million syndrome cycles using 288 physical qubits in total, assuming the physical error rate of $0.1\%$. We argue that achieving the same level of error suppression on 12 logical qubits with the surface code would require nearly 3000 physical qubits. Our findings bring demonstrations of a low-overhead fault-tolerant quantum memory within the reach of near-term quantum processors.

1 Introduction

Quantum information is fragile because noise is difficult to eliminate, making error correction essential for scalable quantum computing. The paper focuses on LDPC-based protocols that combine high encoding efficiency with practical hardware requirements.

  • Motivation: Noise from qubits, control systems, materials, measurements, and environmental effects makes quantum information fragile and difficult to isolate.Some error sources can be reduced, but others appear difficult or impossible to remove.
  • Motivation: Error correction is essential because persistent noise threatens the construction of a functioning scalable quantum computer.
  • Existing approaches: The surface code combines an error threshold close to 1% with fast decoding and compatibility with 2D square-lattice processors.
  • Existing approaches: Scaling the surface code to hundreds of logical qubits is prohibitively expensive because of its poor encoding efficiency.
  • Existing approaches: LDPC codes are attractive because they may provide quantum fault tolerance with substantially higher encoding efficiency than surface-code architectures.
  • Contribution: The paper presents high-rate LDPC codes with low-depth syndrome measurement, efficient decoding, fault-tolerant logical operations, and more than 10X lower encoding overhead than the surface code.The proposed hardware connectivity gives each physical qubit at most six two-qubit-gate neighbors and decomposes into two planar degree-3 subgraphs.

2 Code selection criteria

The paper seeks a practical fault-tolerant quantum memory that combines high-rate, large-distance LDPC codes with shallow syndrome circuits, high pseudo-thresholds, manageable connectivity, and logical-qubit operations.

  • Problem: The target is a fault-tolerant quantum memory with small qubit overhead, large code distance, and compatibility with superconducting-circuit capabilities and limitations.
  • Encoding efficiency: The net encoding rate is r = k/(n + c), where k logical qubits use n data qubits and c ancillary check qubits.
  • Encoding efficiency: The surface code has net encoding rate r ≈ 1/(2d^2), motivating LDPC codes with r ≫ 1/d^2 for large-distance memory.
  • Syndrome measurement: A syndrome measurement circuit repeatedly couples check-supported data qubits to ancillary qubits through CNOT sequences, then measures the check qubits.
  • Noise threshold: A useful protocol should use a low-depth circuit and achieve pseudo-threshold close to 1% or higher under the circuit-based noise model.The pseudo-threshold satisfies pL(p) = kp, comparing logical error probability with the estimated error probability of k unencoded qubits.
  • Fault tolerance: The syndrome circuit should limit faulty-operation pathways to preserve circuit distance, although distance preservation is preferred rather than required.
  • Hardware connectivity: Hardware-compatible designs should support low-depth gates over limited-connectivity Tanner graphs, including graphs with small thickness and planar edge layers.A Tanner graph connects check operators to data qubits on which they act nontrivially; graph thickness partitions edges into planar subgraphs.
  • Logical operations: The memory must support measurement, initialization, readout, and Pauli-product operations for individual logical qubits.

3 Main results

The paper presents Bivariate Bicycle LDPC codes with high encoding rates, constant-depth syndrome measurement, and fault-tolerant memory capabilities. These codes achieve near-1% pseudo-thresholds and substantially reduce physical-qubit requirements relative to surface codes.

  • Code construction: Bivariate Bicycle codes are CSS-type LDPC codes with weight-6 checks arranged on a two-dimensional grid with periodic boundary conditions.Their check operators are not geometrically local, unlike toric-code stabilizers.
  • Code construction: 144 data qubits encode 12 logical qubits at distance 12 and net encoding rate r = 1/24.The distance-13 surface code has net encoding rate r = 1/338.
  • Syndrome measurement and decoding: Each length-n code uses n ancillary check qubits and a seven-layer CNOT syndrome-measurement cycle, giving net encoding rate r = k/(2n).The full error-correction protocol repeats syndrome cycles and decodes the measured syndromes to infer the data error.
  • Error suppression: The observed pseudo-threshold for the 144-qubit and 288-qubit codes is close to 0.007, nearly matching the surface-code threshold.Logical error rates were computed numerically for p ≥ 10^-3 and extrapolated to lower physical error rates using a fitting formula.
  • Resource requirements: At physical error rate p = 10^-3, the distance-12 code preserves 12 logical qubits for nearly one million syndrome cycles using 288 physical qubits.The distance-12 BB code provides more than 10X savings in physical qubits compared with the surface code.
  • Logical memory operations: Extensions attach ancilla systems for fault-tolerant logical X- and Z-basis measurements, enabling load-store operations for all logical qubits.The extended Tanner graph has a thickness-2 implementation and an effectively planar X-ancilla extension.

4 Bivariate Bicycle quantum LDPC codes

Bivariate Bicycle codes are high-rate CSS LDPC codes defined from commuting bivariate-polynomial matrices, with structured parameters and Tanner graphs designed for low-overhead implementations.

  • Code construction: BB codes use check matrices HX = [A|B] and HZ = [B^T|A^T], where A and B are sums of three commuting permutation matrices.The construction uses binary-matrix arithmetic modulo two and produces codes of length n = 2ℓm.
  • Code parameters: n = 2ℓm and k = 2 · dim(ker(A) ∩ ker(B)) determine the code length and number of logical qubits.The code distance is specified through the associated kernel and row-space conditions.
  • Examples: The [[360, 12, ≤24]] code improves on the [[882, 24, ≤24]] weight-6-check code reported by Panteleev and Kalachev, assuming the distance bound is tight.Two independent copies of the 360-qubit code give [[720, 24, ≤24]].
  • Tanner-graph structure: Each code has weight-6 checks, each qubit participates in six checks, and its Tanner graph has degree 6 and thickness at most 2.The two planar layers can be computed in O(n), and each layer is a degree-3 graph.
  • Code parameters: dX = dZ, so the code offers equal distance against X-type and Z-type errors.The equality follows from the symmetry relating the X- and Z-check matrices.
  • Tanner-graph structure: The Tanner graph is connected exactly when the matrices AiA_j^T generate the group M; otherwise, the construction can split into isomorphic components.Some parameter choices create separable code blocks, although the Table 3 examples are connected.

5 Syndrome measurement circuit

The syndrome-measurement protocol repeatedly measures all checks using nearest-neighbor CNOT layers on the Tanner graph while preserving logical operators. Its optimized unitary cycle has depth 7.

  • Circuit overview: Each syndrome cycle measures all n check operators using n data qubits and n ancillary check qubits.The full syndrome-measurement circuit therefore uses 2n physical qubits before any additional architecture is considered.
  • Circuit structure: The circuit is divided into rounds of depth-1 CNOT and single-qubit operations, with CNOTs restricted to nearest-neighbor Tanner-graph edges.The design uses non-overlapping operations within each round.
  • Circuit structure: Ignoring initialization and measurement, the optimized syndrome cycle is a depth-7 CNOT circuit rather than the depth 14 obtained by the generic construction.The reduction exploits symmetries of the explicit LDPC-code family.
  • Circuit function: The circuit maps each check ancilla’s single-qubit stabilizer to the corresponding data-check operator, allowing final ancilla measurements to reveal the syndrome.The data-code check operators remain unchanged during the measurement.
  • Circuit implementation: The seven unitary rounds apply CNOTs associated with A1, A2, A3, B1, B2, and B3 across the four registers q(X), q(L), q(R), and q(Z).The listed round sequence implements the required check transformations.
  • Fault-tolerant operation: The syndrome cycle acts trivially on logical X-type operators, and the analogous construction preserves the encoded logical information during repeated measurement.The proof tracks the vector transformation through the CNOT sequence.

6 Decoder for the circuit-based noise model

The decoder converts circuit-based faults into a sparse linearized noise model, then uses BP-OSD to infer data-qubit errors from measured syndromes. It replaces exact minimum-weight decoding with a practical heuristic while accounting for X- and Z-type errors separately.

  • Noise representation: The circuit-based depolarizing model assigns fault probabilities according to operation type: p/15 for faulty CNOTs, p/3 for idle qubits, and p for initialization or measurement.The model assumes independent operation failures with probability p.
  • Decoder objective: A decoder maps measured, potentially faulty syndromes to a guessed final Pauli error on the data qubits.Decoding succeeds when the guess matches the actual error up to check operators, preserving the same logical action.
  • Noise representation: The offline stage enumerates single-fault circuit realizations and records their measured, final-error, and logical syndromes.For a code with n data qubits and N_c cycles, the syndrome vectors have lengths nN_c, n, and 2k respectively.
  • Sparse decoding matrix: Syndrome sequences are sparsified by replacing each cycle’s measurement with its change from the preceding cycle.The transformation m → m′ concentrates information at locations where consecutive syndrome measurements differ.
  • Practical decoder: BP-OSD approximates minimum-weight decoding by belief-propagation marginals followed by an ordered-statistics search over reliable information sets.This avoids solving the NP-hard exact optimization directly for the large instances required by logical-error simulations.
  • Practical decoder: Because the codes are CSS-type, the decoder solves separate X-type and Z-type decoding problems using corresponding syndrome matrices.The resulting guesses are combined into the final estimated data-qubit error.

7 Proof of Lemma 1

The proof establishes the parameters of the code QC(A, B) and shows that its X- and Z-type distances are equal. This equality implies balanced protection against the two Pauli error types.

  • Code parameters: Lemma 1 states that QC(A, B) has parameters [[n, k, d]], with n and k determined by ℓ, m, and the common kernel of A and B.The distance is specified by the lemma’s parameter formula.
  • Distance equality: The code offers equal distance for X-type and Z-type errors.The proof derives d_Z ≤ d_X and then establishes the reverse inequality.
  • Distance equality: A minimum-weight logical X-type operator of weight d_X is paired with an anticommuting logical Z-type operator to derive d_Z ≤ d_X.The construction uses the CSS check matrices and the logical operators’ commutation relation.
  • Distance equality: The reverse inequality follows by an analogous argument, yielding d_X = d_Z.The equality can also be established by viewing QC(A, B) as a Lifted Product code.

8 Numerical simulation details

The numerical section describes simulation and fitting procedures for BB LDPC codes and compares them with rotated surface-code simulations. Logical error probability is evaluated per syndrome cycle.

  • Simulation procedure: Figure 2 data for BB LDPC codes uses BP-OSD extended to the circuit-based noise model, with MIN-SUM belief propagation limited to 10,000 iterations.The simulations use combination-sweep ordered-statistics decoding, and most points accumulate at least 100 logical errors.
  • Fitting procedure: BB LDPC logical-error data are fitted with pL(p) = p^(d_circ/2)(c0 + c1p + c2p^2).The fitting parameters c0, c1, and c2 are listed for the codes in Table 1.
  • Surface-code comparison: Surface-code simulations use rotated codes [[d^2, 1, d]] with d ∈ {9, 11, 13, 15} and the standard syndrome-measurement circuit.Encoding 12 logical qubits uses 12 separate surface-code patches.
  • Reported metric: The plotted quantity is pL, the logical error probability per syndrome cycle.This definition applies to the logical-error-rate comparison in Figure 2 B).

9 Logical memory capabilities

BB LDPC codes support fault-tolerant access to individual logical qubits through logical operators, automorphism-based gates, ZX-duality, and Tanner-graph probes. These capabilities enable logical measurements and teleportation-based data transfer, but some access constructions carry substantial overhead or unclear scalability.

  • 9.2 Logical Gates based on Automorphisms: Depth-four automorphism circuits implement commuting logical CNOTs that translate operators within each logical block.These permutations use connectivity already required for syndrome measurements and support translations across the operator grids.
  • 9.4 Logical Measurements: Combining translations, block exchange, and probe measurements enables measurement of any logical qubit and teleportation-based data transfer into and out of the code.The measurement ancilla can be implemented in an effectively planar Tanner graph, allowing connection to another code such as a surface code.
  • Limitations: The logical-memory construction has important resource and functionality limits: probe ancillas add substantial overhead, while automorphism gates are not clearly useful for computation.The authors also leave more efficient ancilla systems and additional ZX-duality discovery for future work.
  • 9.1 Logical Pauli Operators: BB LDPC logical Pauli operators split into primed and unprimed blocks with identical commutation structure.Each block contains |M| = ℓm X operators and Z operators, and the blocks commute with one another.
  • 9.3 Accessing the Primed Block via a ZX-duality: A ZX-duality swaps the primed and unprimed blocks while applying logical Hadamard gates, enabling access to operators in the other block.For the [[144, 12, 12]] code, the circuit has a six-link nearest-neighbor chain before swap operations are applied.
  • 9.4 Logical Measurements: Extended Tanner-graph ancilla systems act as probes for fault-tolerant measurement of one logical X and one logical Z operator.For the [[144, 12, 12]] code, achieving d = 12 with the described construction requires 2 × 30 × (2d −1) = 1380 additional qubits.

10 Conclusion

The proposed high-rate LDPC codes offer surface-code-like error suppression with substantially lower qubit overhead, while requiring a thickness-two connectivity architecture. The paper identifies several hardware, decoding, circuit-design, code-parameter, noise-model, and logical-gate questions that remain open.

  • Conclusion: Nearly 15x lower qubit overhead achieves the same error suppression as the surface code for p ≥0.1%.Numerical simulations use the circuit-based noise model and compare the proposed LDPC codes with the surface code.
  • Conclusion: Thickness-two connectivity can be implemented with two planar degree-3 layers of qubit couplers.The codes are not geometrically local, but their syndrome-measurement connectivity admits this architectural implementation.
  • Hardware challenges: Three hardware challenges are a low-loss second layer, seven qubit connections, and long-range couplers.The paper describes these requirements for realizing the codes with superconducting qubits.
  • Hardware challenges: Long-range couplers are the most difficult hardware challenge because some buses for the 144-qubit code require frequency engineering.Filtering resonators are proposed as one possible approach, with a proof-of-principle experiment cited by the paper.
  • Open questions: Open code-design questions concern tradeoffs among n, k, and d, including whether constant non-zero encoding rate and growing distance are achievable.These questions define an unresolved boundary for the code family’s asymptotic properties.
  • Open questions: Faster decoding, measurement-biased-noise analysis, improved circuit scheduling, and more powerful logical gates remain open directions.The current decoder may be too slow for real-time correction, and the demonstrated logical gates primarily support memory capabilities.
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