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Constant-Overhead Fault-Tolerant Quantum Computation with Reconfigurable Atom Arrays
Qian Xu, J. Pablo Bonilla Ataides, Christopher A. Pattison, Nithin Raveendran, Dolev Bluvstein, Jonathan Wurtz, Bane Vasic, Mikhail D. Lukin, Liang Jiang, Hengyun Zhou
TL;DR
Surface-code-based error correction is costly, while qLDPC codes face long-range-connectivity and circuit-level validation challenges. The paper develops a reconfigurable atom-array architecture using qLDPC product structure, proves fault tolerance, and evaluates memory and logical operations. It reports practical overhead savings and competitive performance at experimentally relevant scales, while noting substantial time overhead and the absence of an asymptotic threshold with idling errors.
Problem
Surface-code-based error correction is costly, while qLDPC codes require challenging long-range connectivity and lacked established full circuit-level performance evidence.
Method
The paper implements high-rate qLDPC fault-tolerant computation on reconfigurable atom arrays using product structure, atom rearrangement, proofs, and circuit-level simulations.
Results
The architecture maintains subthreshold qLDPC scaling during computation and achieves competitive HGP and LP performance, with thresholds around 0.6% when idling errors are neglected.
Takeaways & Limitations
The work brings high-rate qLDPC fault-tolerant computation into a practical regime, including over an order-of-magnitude savings below 3000 physical qubits in reported finite-size estimates.
Takeaways & Limitations
The scheme retains substantial time overhead, and idling errors eliminate an asymptotic threshold despite constant overhead remaining achievable at physically relevant sizes.
Abstract
from arXiv · showhide
Quantum low-density parity-check (qLDPC) codes can achieve high encoding rates and good code distance scaling, providing a promising route to low-overhead fault-tolerant quantum computing. However, the long-range connectivity required to implement such codes makes their physical realization challenging. Here, we propose a hardware-efficient scheme to perform fault-tolerant quantum computation with high-rate qLDPC codes on reconfigurable atom arrays, directly compatible with recently demonstrated experimental capabilities. Our approach utilizes the product structure inherent in many qLDPC codes to implement the non-local syndrome extraction circuit via atom rearrangement, resulting in effectively constant overhead in practically relevant regimes. We prove the fault tolerance of these protocols, perform circuit-level simulations of memory and logical operations with these codes, and find that our qLDPC-based architecture starts to outperform the surface code with as few as several hundred physical qubits at a realistic physical error rate of $10^{-3}$. We further find that less than 3000 physical qubits are sufficient to obtain over an order of magnitude qubit savings compared to the surface code, and quantum algorithms involving thousands of logical qubits can be performed using less than $10^5$ physical qubits. Our work paves the way for explorations of low-overhead quantum computing with qLDPC codes at a practical scale, based on current experimental technologies.
INTRODUCTION
High-rate qLDPC codes could reduce the resource cost of fault-tolerant quantum computing, but their long-range connectivity and incomplete circuit-level validation have hindered practical adoption. This work addresses these challenges with a reconfigurable atom-array architecture and analyzes its fault-tolerant performance.
- Traditional quantum error-correction schemes such as the surface code require millions of qubits for problems of interest.
- qLDPC codes encode multiple logical qubits per block, offering asymptotically constant encoding rates and better distance scaling than planar surface codes.
- Long-range connectivity requirements make physical implementation of qLDPC codes challenging.
- Circuit-level fault tolerance and near-term performance relative to surface codes remained insufficiently established for finite-size qLDPC codes.
- The proposed atom-array architecture combines experimental blueprints, fault-tolerance proofs, and circuit-level simulations for HGP and LP codes.The approach uses qLDPC product structure and reconfigurable connectivity, with simulated thresholds around 0.6% under a depolarizing noise model that neglects idling errors.
- Subthreshold scaling of high-rate qLDPC codes can be maintained during computation, supporting low-overhead fault-tolerant quantum computing.
OVERVIEW OF QLDPC-BASED QUANTUM COMPUTER
The proposed computer separates dense qLDPC memory from computational logical qubits and connects them through mediating ancillae. In relevant regimes, the memory block dominates the resource cost while preserving constant encoding-rate scaling.
- The architecture contains a high-rate qLDPC memory block, a processor with computational logical qubits, and mediating ancillae.The memory stores quantum information, the processor performs logical gates, and ancilla-assisted lattice surgery teleports information between them.
- The qLDPC memory provides constant encoding rate k/n and a logical failure rate that decays exponentially with code distance.
- The processor uses computational code patches whose distance scales as Θ(polylog(kT)) with logical-circuit depth T.
- When the number of computational qubits grows more slowly than the memory size, the memory block dominates physical-qubit overhead and yields constant-rate quantum computation.
IMPLEMENTATION IN NEUTRAL ATOM ARRAYS
Reconfigurable atom arrays implement qLDPC connectivity by shuttling atoms and exploiting product structure for parallel rearrangements and entangling operations. The resulting procedures have favorable scaling and experimentally plausible timescales for finite-size codes.
- Atom arrays use optical-tweezer shuttling to reconfigure connectivity with minimal decoherence and perform parallel two-qubit gates across the system.Acousto-optic deflectors can simultaneously control rectangular grids containing thousands of atoms.
- A divide-and-conquer rearrangement algorithm orders checks and bits in logarithmic depth before parallel entangling operations.The method recursively compacts array halves and applies global laser pulses to entangle neighboring checks and bits.
- HGP codes match the crossed-AOD product structure because their connectivities are inherited from horizontal and vertical classical LDPC codes.Parallel row reordering and column reordering interleaved with entangling gates implement the required syndrome-extraction connectivity.
- The total rearrangement time scales as O(4√n) for a two-dimensional array of length L.
- For a 10000-qubit HGP code, each rearrangement layer is estimated to require 3 ms, versus demonstrated coherence times exceeding 10 s.The estimate is described as a small fraction of the available coherence time under existing experimental parameters.
QLDPC MEMORY
The qLDPC memory uses fault-tolerant syndrome extraction and space-time decoding, with simulations showing competitive thresholds, maintained subthreshold scaling, and substantial qubit savings over surface codes at practical sizes.
- Fault tolerance: A circuit-level single-shot threshold is proven for qLDPC codes with linear confinement under single-ancilla syndrome extraction and size-independent depolarizing noise.The proof applies to qLDPC codes possessing the linear confinement property.
- Circuit and decoding: The product coloration circuit uses one ancilla per stabilizer generator, with entangling-gate depths 16 for HGP codes and 20 for LP codes.A space-time BP+OSD decoder jointly processes multiple QEC cycles using the full circuit details.
- Numerical memory performance: 0.63% and 0.62% are the simulated thresholds for HGP and LP codes, respectively, under depolarizing noise without idling errors.Finite-size LP codes show better subthreshold scaling than HGP codes.
- Numerical memory performance: With idling errors included, good logical failure rates and subthreshold scaling are maintained for both code families at practically relevant sizes.Idling errors grow as O(n^1/4) for HGP codes and O(n^1/2) for LP codes, but are negligible when 3pi(n) ≪ pg.
- Resource overhead: At physical error rate 10^-3, both HGP and LP codes outperform surface codes with as few as 25 logical qubits.LP codes using less than 3000 physical qubits achieve over an order-of-magnitude qubit savings below 200 logical qubits; extrapolated HGP estimates reach this savings at 1000 logical qubits and 10^5 physical qubits.
LOGICAL OPERATIONS
The architecture performs logical operations by teleporting states between qLDPC memory and topological-code processors through ancilla-assisted lattice surgery, with simulations indicating that fault-tolerant gate performance remains close to memory performance.
- Numerical gate performance: Simulations find that thresholds and logical performance remain almost unchanged during fault-tolerant gates.The simulations evaluate errors during merge and split operations in the XX lattice-surgery building block using the space-time decoder.
- Operation scheme: Logical information is teleported between qLDPC memory and topological-code ancillae, where standard techniques implement universal logical operations.Prescribed logical measurements are implemented through lattice surgery in a measurement-based circuit.
- Resource overhead: Using o(k) topological and teleportation patches keeps ancilla-patch space overhead subleading, while the proposed scheme halves the ancilla patch size relative to Ref..This reduces the space overhead of teleportation between qLDPC and topological codes.
- Operation scheme: The teleportation ancilla is formed as the hypergraph product of classical codes associated with the logical operators of the two code patches.For surface-to-HGP teleportation, min{dcomp,dmem} syndrome-extraction rounds provide tolerance against measurement errors.
DISCUSSION AND OUTLOOK
The work places high-rate qLDPC computation within a practical hardware regime, while leaving substantial time overhead and algorithm-dependent compilation as important open constraints.
- Discussion: The architecture brings high-rate qLDPC fault-tolerant computation into the practical regime through space savings, logical-gate performance, and compatibility with existing hardware capabilities.The claimed practical advantages combine resource reductions with a hardware implementation blueprint.
- Limitations and outlook: Substantial time overhead remains because fault-tolerant gates require Θ(d) QEC cycles and low-rate ancilla and computational patches limit logical parallelism.The authors identify limited-parallelism algorithm compilations as natural candidates and call for end-to-end compilation studies.
- Architecture: The proposed teleportation architecture connects dense qLDPC storage with topological-code processing through ancilla-mediated lattice surgery.The ancilla patch is constructed from classical codes associated with selected logical operators and mediates joint measurements between code blocks.
METHODS
The methods combine product-structured HGP and LP qLDPC codes with atom-array rearrangement, pipelined syndrome extraction, circuit-level decoding, and simulations of idling-error effects. The analysis establishes fault-tolerance properties and evaluates practical thresholds and logical failure rates.
- Code constructions: HGP codes are formed from two classical LDPC codes, while LP codes apply a symmetry-reducing lift to a hypergraph product of two protographs.The LP construction replaces protograph entries with circulant-matrix representations and uses the resulting lifted check matrices.
- Atom-array implementation: Product-structured qLDPC connectivity is implemented through row and column atom rearrangements matched to the underlying classical codes.The approach uses efficient rearrangement algorithms while respecting AOD constraints on shared row and column operations and non-crossing trajectories.
- Syndrome extraction: The pipelined product coloration circuit reduces d rounds of syndrome extraction to (2d + 2)∆C entangling layers while preserving valid X- and Z-syndrome ordering.Pipelining overlaps the X syndrome of one round with the Z syndrome of the preceding round.
- Idling errors: For experimental parameters, idling errors are approximated by p_g → p_g + 3p_i(n), remain negligible up to n ∼ 10^7, and allow logical failure rates below 10^-24.The effective circuit depth is ∆[1 + 3p_i(n)/p_g], becoming effectively 4D-local when 3p_i(n) ≫ p_g.
- Decoding: A circuit-level space-time decoder uses belief propagation and ordered statistics decoding to jointly infer faults across multiple QEC cycles.The decoding graph connects detector parities to circuit-fault variables, with BP followed by BP+OSD in the final round.
- Fault tolerance and simulations: Under a depolarizing noise model, the work proves a circuit-level single-shot threshold for qLDPC codes with linear confinement and evaluates memory and logical operations numerically.The simulations use Stim and the same space-time decoder, including repeated QEC rounds for fault-tolerant logical operations.
I. CIRCUIT-LEVEL FAULT TOLERANCE
This section analyzes qLDPC fault tolerance under circuit-level noise, including space-time decoding, numerical thresholds, and idling errors from atom rearrangement.
- The analysis covers fault tolerance under circuit-level noise, space-time decoding, numerical thresholds, and atom-rearrangement idling errors.
- The space-time decoder is used to evaluate qLDPC codes across multiple syndrome-extraction cycles.
- Idling errors associated with atom rearrangement are analyzed alongside the fault-tolerance properties of the codes.
A. Threshold theorem
The threshold argument connects circuit-level depolarizing noise to local stochastic syndrome-data noise, then uses confinement to establish sustainable single-shot decoding thresholds.
- Circuit-level depolarizing noise at rate p induces local stochastic syndrome-data noise at a rate determined by the extraction-circuit depth.
- For sufficiently small errors, linear confinement requires syndrome weight to grow proportionally with reduced error weight.
- A qLDPC family with confinement admits a single-shot decoder with a sustainable threshold, yielding exponentially small recovery failure after any constant number of faulty cycles.
- Local greedy decoders imply linear confinement, so qLDPC families with polynomially growing correctable reduced weight are single-shot decodable under circuit-level depolarizing noise.
- The proof applies the confinement implication together with the constant-depth extraction circuit's local-stochastic noise characterization.
B. Numerical simulations
Numerical simulations test memory decoding with space-time BP+OSD methods and report stable single-shot behavior, improved thresholds, and stronger circuit-level performance than phenomenological decoding.
- The logical failure rate per code cycle is computed from the total failure probability over many syndrome-extraction cycles, with adaptive Monte Carlo sampling controlling uncertainty.
- Stable logical failure rates as code cycles increase numerically verify the single-shot property for HGP and LP codes with the space-time decoder.
- 0.33% is the HGP threshold with the space-time decoder, exceeding the reported < 0.23% threshold using a phenomenological decoder.
- (0.63 ± 0.01)% and (0.62 ± 0.02)% are the fitted HGP and LP thresholds, respectively, without idling errors.
- The space-time decoder improves both thresholds and subthreshold scaling relative to the phenomenological decoder.
C. Effect of idling errors
The simulations compare explicit gate and idling errors with an effective gate-error rescaling, finding similar logical failure rates under the two treatments.
- The simulations compare combined gate and idling errors against gate-only errors with rate pg + 3pi.
- Similar logical failure rates confirm that idling errors can be approximated by rescaling the gate error as pg → pg + 3pi.
- The comparison is performed for HGP and LP codes across code-cycle schedules that vary with the gate-error rate.
A. Teleportation of a single logical qubit
The protocol constructs an ancilla hypergraph-product patch for teleporting a logical qubit and merges it with code A to measure a joint logical operator fault-tolerantly. Under non-degeneracy assumptions, the ancilla and merged subsystem retain distance guarantees tied to the input codes.
- Ancilla patch construction: The ancilla patch is built from restricted stabilizers on the supports of selected logical operators XA and ZB, using a hypergraph product construction.The selected supports define mA = |supp XA| and mB = |supp ZB|, which determine the classical check matrices and ancilla geometry.
- Ancilla patch construction: 17? The non-degenerate ancilla patch encodes one logical qubit and has distance min(|XA|,|ZB|).Minimal-weight logical representatives are supported on rows or columns of the ancilla patch.
- Merged patch: The (A,ℓ)-merged patch adds interface qubits and combines stabilizers from code A with ancilla stabilizers so that XA XC becomes a stabilizer.The merged stabilizers mutually commute, and their product realizes the joint logical measurement operator.
- Fault tolerance: Fault tolerance is analyzed by mapping merging and splitting to gauge fixing of a subsystem code.The recovery procedure follows the subsystem-code recovery procedure, while complete gauge-fixings have distance at least the dressed distance.
- Fault tolerance: The merged subsystem code has dressed distance at least min(dA,dB), where dA and dB are the distances of the two input codes.The bound is stated for the subsystem code generated from the original code, non-degenerate ancilla patch, merged-patch stabilizers, and an additional logical operator.
B. Parallel teleportation
The teleportation construction extends to multiple qLDPC logical qubits in parallel by using separate ancilla patches and exploiting HGP logical representatives with distinct coordinates. With an appropriate computation-code distance, the total ancilla size scales linearly with the target logical-qubit count.
- Parallel teleportation: Teleportation can be performed in parallel for multiple qLDPC logical qubits using separate ancilla patches and simultaneous qLDPC/surface-code merges.For HGP codes, suitable logical representatives yield ancilla patches whose distance is lower bounded by the minimum of the HGP and surface-code distances.
- Parallel teleportation: HGP logical X representatives can be chosen on distinct columns, allowing any set of m ≤ k0 logical qubits to teleport to separate surface-code patches.The representatives are labeled by coordinates and each selected logical qubit uses a distinct column coordinate.
- Overhead: Choosing m = O(k/poly log kT) and dcomp = O(poly log kT) gives total ancilla size O(k), maintaining constant space overhead during logical computation.The computation-code distance is selected to suppress the logical failure probability of a depth-T logical circuit.