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Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator
Haocong Luo, Yahya Can Tuğrul, F. Nisa Bostancı, Ataberk Olgun, A. Giray Yağlıkçı, Onur Mutlu
TL;DR
Existing cycle-accurate DRAM simulators lack the modularity and concise specification mechanisms needed for rapidly evaluating intrusive memory-system changes. Ramulator 2.0 addresses this with interface-based components, reusable DRAM command models, and plugin-based controller extensions, and demonstrates the approach through RowHammer studies while maintaining fast simulation and rigorous validation.
Problem
Existing cycle-accurate DRAM simulators are insufficiently modular and extensible for rapidly implementing and evaluating intrusive memory-controller and DRAM changes.
Method
Ramulator 2.0 models memory-system components through shared interfaces and independent implementations, uses concise string-based DRAM specifications and reusable templated lambda functions, and adds controller changes as plugins.
Results
Ramulator 2.0 implements six RowHammer mitigations as plugins, supports newer DRAM standards, is rigorously validated, and maintains fast simulation speed despite increased modularity and extensibility.
Takeaways & Limitations
Ramulator 2.0 provides an open, modular infrastructure for more agile implementation and evaluation of DRAM-based memory-system research ideas.
Abstract
from arXiv · showhide
We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the performance, security, and reliability of memory systems. Ramulator 2.0 abstracts and models key components in a DRAM-based memory system and their interactions into shared interfaces and independent implementations. Doing so enables easy modification and extension of the modeled functions of the memory controller and DRAM in Ramulator 2.0. The DRAM specification syntax of Ramulator 2.0 is concise and human-readable, facilitating easy modifications and extensions. Ramulator 2.0 implements a library of reusable templated lambda functions to model the functionalities of DRAM commands to simplify the implementation of new DRAM standards, including DDR5, LPDDR5, HBM3, and GDDR6. We showcase Ramulator 2.0's modularity and extensibility by implementing and evaluating a wide variety of RowHammer mitigation techniques that require different memory controller design changes. These techniques are added modularly as separate implementations without changing any code in the baseline memory controller implementation. Ramulator 2.0 is rigorously validated and maintains a fast simulation speed compared to existing cycle-accurate DRAM simulators. Ramulator 2.0 is open-sourced under the permissive MIT license at https://github.com/CMU-SAFARI/ramulator2
1 INTRODUCTION
Ramulator 2.0 addresses the limited modularity and extensibility of existing cycle-accurate DRAM simulators with independent component implementations, concise DRAM specifications, and reusable command models. It demonstrates these capabilities through RowHammer plugins, support for newer DRAM standards, validation, and open-source release.
- Motivation: Existing cycle-accurate DRAM simulators make intrusive memory-system design changes difficult because key components are not modeled modularly.Existing designs also couple DRAM specifications with controllers and aggregate standards in verbose implementations.
- Modular architecture: Ramulator 2.0 separates memory-system components into shared interfaces and independent implementations, allowing design changes without modifying unrelated components.The framework supports changes such as address mapping, request scheduling, new DRAM standards, and RowHammer mitigation.
- DRAM specifications: Human-readable DRAM definitions, command permutations, and reusable templated lambda functions simplify adding commands, timing constraints, and standards.The same command implementation can be reused across DDR5, LPDDR5, GDDR6, and HBM3 without sacrificing simulation speed.
- Evaluation and contributions: Six RowHammer mitigation techniques plug into one unmodified baseline memory controller as separate implementations.This demonstrates modular controller extension for techniques requiring different additional functionalities.
- Evaluation and contributions: Ramulator 2.0 is implemented in C++20, supports standalone and library use, covers multiple DRAM standards, is rigorously validated, and is released under the MIT license.The paper also integrates the simulator with gem5.
2 RAMULATOR 2.0 DESIGN FEATURES
Ramulator 2.0 achieves extensibility by separating interfaces from implementations and by representing controller extensions as plugins. It also makes DRAM organizations, commands, timing constraints, and command behavior concise, human-readable, reusable, and efficiently encoded.
- 2.1 Modular and Extensible Software Architecture: Interfaces define shared component functionality, while implementations provide behavior, so components can be replaced without changing unrelated code.Implementations inherit from interfaces and communicate through interface pointers.
- 2.1 Modular and Extensible Software Architecture: New components can be added through separate implementation files and classes, avoiding intrusive changes to existing code.The documented extension process creates a new source file, inherits the relevant classes, and implements the new functionality.
- 2.1.1 Memory Controller Plugins: Controller plugins receive each issued DRAM command and address, update internal state, and can enqueue high-priority refresh requests for victim rows.This design supports multiple RowHammer mitigation behaviors within the same controller framework.
- 2.2 Concise and Intuitive DRAM Specifications: DRAM organizations, commands, and command scopes are defined with human-readable string literals and queried through the specification model.Ramulator 2.0 statically encodes these names into integers for efficient lookup-table indexing and decouples specifications from other components.
- 2.2 Concise and Intuitive DRAM Specifications: Timing constraints use permutations of preceding and following commands, merging definitions with the same numerical latency.For example, nRCD can specify the delay from ACT to either RD or WR.
- 2.2 Concise and Intuitive DRAM Specifications: Templated lambda functions define DRAM command behavior once and reuse it across similar commands and standards.The RFMab implementation is shared across DDR5, LPDDR5, GDDR6, and HBM3.
3 VALIDATION & EVALUATION
The evaluation validates Ramulator 2.0's command behavior and compares its runtime with existing simulators, then uses controller plugins to study RowHammer mitigation overhead. The study finds substantial low-threshold overhead and a scalability problem for existing mitigations.
- 3.1 Validation: Ramulator 2.0 verifies issued DRAM-command traces against Micron's DDR4 Verilog Model to check timing constraints and state transitions.A controller plugin records commands, addresses, and timestamps for comparison.
- 3.2 Performance of Ramulator 2.0: The simulation-speed comparison uses four cycle-accurate simulators, two five-million-request traces, ten runs per simulator and trace, and comparable system parameters.The traces use random and streaming access patterns with a 4:1 read-write ratio.
- 3.3 Cross-Sectional Study of RowHammer Mitigations: Six RowHammer mitigation techniques are implemented as memory-controller plugins and evaluated using weighted speedup normalized to an unmitigated baseline.The evaluation varies the RowHammer threshold and uses a simplistic out-of-order core model.
- 3.3 Cross-Sectional Study of RowHammer Mitigations: All evaluated RowHammer mitigations except Ideal incur significant overhead as tRH decreases to very low values.The comparison is against the ideal mitigation in the reported RowHammer study.
- 3.3 Cross-Sectional Study of RowHammer Mitigations: For tRH < 50, RRS overhead becomes too high for simulation to make progress because row swaps trigger further row swaps.The paper concludes that existing mitigations are not scalable enough at these thresholds.
4 CONCLUSION
Ramulator 2.0 is a modern, modular, and extensible DRAM simulator designed to support memory systems research. Its architecture and DRAM modeling aim to make research more agile.
- Ramulator 2.0 succeeds Ramulator 1.0 as a modern, modular, and extensible DRAM simulator.
- The paper demonstrates Ramulator 2.0's high modularity, extensibility, and performance.
- Its software architecture and concise, intuitive DRAM modeling facilitate more agile memory systems research.