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Spatially parallel decoding for multi-qubit lattice surgery

Sophia Fuhui Lin, Eric C. Peterson, Krishanu Sankar, Prasahnt Sivarajah

arXiv:2403.01353v3quant-phcs.ARcs.ET

TL;DR

Large lattice-surgery patches strain real-time decoders, and prior work has not resolved hardware-specific constraints alongside decoding accuracy. The paper configures spatially parallel overlapping windows for these operations and studies their accuracy and throughput. It finds that buffer width must balance those demands and depends on device noise.

  • Problem

    Lattice surgery can create merged patches that strain real-time decoders, while prior work has not addressed relevant hardware constraints alongside maintaining logical-qubit fidelity.

    Source: §I · p. 2

  • Method

    The scheme assigns decoder modules to overlapping, locally viewed windows and coordinates their corrections at seams under hardware-compatible configurations.

    Source: §I · p. 2

  • Results

    Buffer width trades decoding accuracy against throughput and should depend on physical noise; inter-window communication is not the bottleneck even for windows wider than 100.

    Source: §I · p. 2

  • Takeaways & Limitations

    Window size must be at least an isolated code patch to maintain logical-qubit fidelity, while buffer width should be chosen to balance accuracy and throughput.

    Source: §I · p. 2

    A patch intersection with a commit region should not be smaller than half that commit region.

    Source: E. Implications · p. 10

Abstract

from arXiv · show

Running quantum algorithms protected by quantum error correction requires a real time, classical decoder. To prevent the accumulation of a backlog, this decoder must process syndromes from the quantum device at a faster rate than they are generated. Most prior work on real time decoding has focused on an isolated logical qubit encoded in the surface code. However, for surface code, quantum programs of utility will require multi-qubit interactions performed via lattice surgery. A large merged patch can arise during lattice surgery -- possibly as large as the entire device. This puts a significant strain on a real time decoder, which must decode errors on this merged patch and maintain the level of fault-tolerance that it achieves on isolated logical qubits. These requirements are relaxed by using spatially parallel decoding, which can be accomplished by dividing the physical qubits on the device into multiple overlapping groups and assigning a decoder module to each. We refer to this approach as spatially parallel windows. While previous work has explored similar ideas, none have addressed system-specific considerations pertinent to the task or the constraints from using hardware accelerators. In this work, we demonstrate how to configure spatially parallel windows, so that the scheme (1) is compatible with hardware accelerators, (2) supports general lattice surgery operations, (3) maintains the fidelity of the logical qubits, and (4) meets the throughput requirement for real time decoding. Furthermore, our results reveal the importance of optimally choosing the buffer width to achieve a balance between accuracy and throughput -- a decision that should be influenced by the device's physical noise.

I. INTRODUCTION

Lattice surgery creates merged surface-code patches that challenge monolithic real-time decoders, while prior window-parallel approaches leave hardware and accuracy questions unresolved. This work configures spatially parallel windows for lattice surgery and analyzes how window size, buffer width, noise, and decoder throughput shape performance.

I. INTRODUCTION

  • A monolithic decoder struggles with multi-qubit gates because lattice surgery merges patches, while decoder throughput falls as patch size grows.Prior real-time decoders meet throughput demands only up to individual logical-qubit patches of distance 20 to 30.Source: §I · p. 1
  • Prior window-parallel work addresses temporal backlog or other spatial partitions, but leaves large spatial windows or hardware feasibility unresolved [4],, [37].One approach requires dynamic routing of parity information, which may be difficult for hardware decoders to realize.Source: §I · pp. 1–2
  • Spatially parallel windows assign decoder modules to overlapping regions, coordinate corrections at seams, and can scale independently of how many patches are merged or how far apart they are.The scheme uses local views and schedules neighboring decoders at different time steps; it is agnostic to the inner decoder.Source: §I · p. 2
  • Window size must be at least an isolated code patch to maintain logical-qubit fidelity, while buffer width trades decoding accuracy against throughput and resource use.At modest physical noise, the recommended buffer width is one-half to two-thirds of an individual patch width.Source: §I · p. 2
  • Inter-window communication does not become the throughput bottleneck even for windows wider than 100; real-time throughput depends on each inner decoder running fast enough.The work also estimates supported patch sizes assuming an FPGA-based inner decoder.Source: §I · p. 2
  • The analysis focuses on surface codes, though the authors say the results are also relevant to other local codes such as color codes.The surface-code setting uses nearest-neighbor grid connectivity.Source: §I · pp. 1–2

II. BACKGROUND

The background explains how surface-code stabilizers detect errors and how lattice surgery measures logical Pauli products by merging patches. It then introduces decoding graphs and matching-based correction.

A. Surface code, lattice surgery, and decoding

  • A distance-d square surface-code patch encodes one logical qubit, with stabilizer measurements detecting Pauli errors through flipped syndrome readouts.The code distance is the minimum weight of a nontrivial undetectable logical error chain.Source: A. Surface code, lattice surgery, and… · pp. 2–3
  • Lattice surgery implements logical multi-qubit Pauli measurements by merging and splitting patches; a Z ⊗Z measurement can be inferred from stabilizers spanning a merge boundary.Y measurements can use twist-based surgery or an alternative protocol.Source: A. Surface code, lattice surgery, and… · p. 3
  • Surface-code decoding uses graphs whose vertices represent stabilizers and whose edges represent detectable error mechanisms, including data and measurement errors.The full graph stacks the spatial graph across time to represent syndrome-measurement errors.Source: A. Surface code, lattice surgery, and… · p. 3, Figure 2 · p. 3
  • Minimum-weight perfect matching identifies lowest-weight error patterns, while Union-Find offers better runtime complexity with slightly lower accuracy than MWPM.Sparse Blossom and Fusion Blossom are cited as fast software MWPM implementations.Source: A. Surface code, lattice surgery, and… · p. 3

B. Real time decoding with FPGA

FPGAs offer parallel, pipelinable processing for high-throughput decoding, but their fixed fabric and communication constraints require decoder designs that fit predetermined hardware resources.

B. Real time decoding with FPGA

  • FPGA fabrics provide parallelism, pipelinability, and specified timing for high-throughput tasks, but are generally programmed once for an application's lifetime.Their trade-off is limited ability to change component behavior after programming.Source: B. Real time decoding with FPGA · p. 3
  • Surface-code syndrome streams make decoding a candidate FPGA application, but arbitrarily long patches can arise during lattice surgery beyond an individual FPGA's fixed capacity.An FPGA has a fixed set of components and therefore supports decoding only up to a certain size.Source: B. Real time decoding with FPGA · p. 3
  • Inter-fabric communication can lose the speed of lock-step FPGA components, so communication must be controlled to avoid dominating runtime.Local component connections are set at compile time and can carry significant layout cost.Source: B. Real time decoding with FPGA · p. 3
  • Because FPGA reprogramming during operation is limited, decoder designs must accommodate changing lattice-surgery patches with only modest on-the-fly reconfiguration.The paper identifies masking read and write operations as a simple form of reprogrammability.Source: B. Real time decoding with FPGA · p. 3

III. RELATED WORK

Prior real-time decoders include FPGA, ASIC, and superconducting implementations, while earlier windowed approaches mainly target temporal parallelism or software latency. The paper frames a hardware-oriented scheme around fixed windows, constrained communication, and limited reprogramming.

III. RELATED WORK

  • Real-time decoder implementations include FPGA Union-Find systems demonstrated up to distance 21, FPGA/ASIC Union-Find results up to distance 23, and MWPM-equivalent FPGA designs at smaller distances.Other work explores ASIC Union-Find, SFQ circuits, and hierarchical decoding.Source: §III · pp. 3–4
  • Earlier overlapping-window work primarily uses temporal parallelism to contain backlog; spatial consequences and the accuracy cost of narrow buffers were not explored in, [37].The information passed between neighboring windows is similar for temporal and spatial parallelism, but their constraints and goals differ.Source: §III · p. 4
  • The prior lattice-surgery-block study [4] emphasizes software latency and dynamic window assignment, whereas this work emphasizes accelerator constraints, throughput, fixed window positions, and noise-dependent buffer effects.Both studies report numerical results on buffer width and decoding accuracy.Source: §III · p. 4

IV. FRAMEWORK OF THE DECODING SCHEME

  • The framework starts with fixed, small windows, analyzes a single communication burst over a fixed nearest-neighbor topology, and limits reprogramming to masking cell reads and writes.The section introduces decoder-module connections, buffer overlap, performance metrics, and a hardware-compatible configuration.Source: §IV · p. 4
  • Non-overlapping windows can cause easy decoding failures unless matching choices are supplemented by communication between neighboring decoders.The figure contrasts suboptimal corrections when matching across an artificial boundary is allowed versus disallowed.Source: Figure 3 · p. 4

A. Connecting decoder modules

Spatially parallel decoding divides a large patch into coarse-grained windows, avoiding a single decoder’s area-dependent processing burden. Overlapping windows in different layers exchange artificial defects so their corrections remain consistent, though a final-layer decoding failure can still reveal errors from earlier layers.

A. Connecting decoder modules

  • A window is the area handled by one decoder module, roughly the size of an individual logical-qubit patch, rather than a per-qubit decoding unit.Processing time for a monolithic decoder scales at least linearly with patch area.Source: A. Connecting decoder modules · p. 4
  • Non-overlapping windows without communication risk logical errors whether matching is allowed across their boundaries or forbidden.The two boundary choices can misdirect syndromes that should match the lower boundary or one another.Source: A. Connecting decoder modules · p. 4
  • Overlapping windows run in different layers: each decoder commits corrections only in its commit region, leaving buffer corrections for a neighboring window.In Figure 4, window A's dotted-edge corrections lie in the buffer and are not committed by A.Source: A. Connecting decoder modules · pp. 4–5, Figure 4 · p. 5
  • After A finishes, it passes artificial defects to B, which flips the corresponding boundary nodes before decoding to keep corrections consistent.These are the nodes on B's left boundary flipped by corrections in A's commit region.Source: A. Connecting decoder modules · p. 5
  • A final-layer graph with no rough boundaries cannot match an odd number of defects; decoding terminates and reports a logical error caused by suboptimal earlier layers.The final-layer window has no artificial rough boundary with neighboring windows.Source: A. Connecting decoder modules · p. 5

B. Metrics

The section frames throughput, accuracy, and latency as decoder metrics, then describes fixed hardware-compatible window configurations. General lattice-surgery operations motivate a staggered three-color layout, because some Y-measurement patches do not fit a two-color checkerboard.

B. Metrics

  • Throughput must match syndrome generation to prevent exponential backlog; temporal parallelism alone adds layers and hardware costs for long lattice-surgery patches.More temporal layers also slow the logical clock rate.Source: B. Metrics · p. 5
  • Ideally, logical qubits undergoing an operation retain the fidelity they have when isolated; this requires sufficiently large windows and buffers.Source: B. Metrics · p. 5

C. Window configuration for hardware decoding

B. Metrics

  • At p ∼0.1%, increasing d by 2 suppresses logical error rate by ∼10X, enough to overcome the scheme's latency of a few cycles.The passage says computation time increases linearly with latency and code distance should increase logarithmically to compensate.Source: B. Metrics · pp. 5–6

C. Window configuration for hardware decoding

  • Hardware-compatible windows and links should be fixed, with disjoint commit regions within each layer and window sizes no smaller than isolated patches.A patch spanning multiple commit regions should intersect each region by more than a minimal amount.Source: C. Window configuration for hardware… · p. 6
  • A three-coloring of staggered squares accommodates general lattice-surgery operations with commit regions the size of individual code patches.Without staggering the rows, four colors are required, unnecessarily increasing latency.Source: C. Window configuration for hardware… · p. 6

V. LOGICAL ERROR RATES

The simulations examine how overlapping-window decoding affects logical error rates on merged surface-code patches. Increasing buffer width improves accuracy, but the useful width depends on physical noise and larger buffers constrain decoder throughput.

A. Methodology for simulations

  • The simulations use PyMatching2 as both the per-window decoder and global baseline, on merged rectangular patches with two overlapping windows and A decoded first.Each memory-simulation shot includes d stabilizer-measurement cycles under a circuit-level noise model parameterized by p.Source: A. Methodology for simulations · p. 6

B. Logical errors along the short edge

  • At p = 0.1%, parallel and global decoding LER confidence intervals overlap for w ≥10 (ratio ∼1.32 at w = 10); at p = 0.5%, the ratio is below 1.3 for w ≥6 and ∼1.05 at w = 10.The accuracy gap narrows as w grows, before the buffer reaches the short-edge length.Source: B. Logical errors along the short edge · p. 7, Figure 8 · p. 7
  • For short-edge errors, strings can confuse window A when exactly one endpoint is committed there and A matches the other to a rough boundary outside the buffer.The analysis gives examples where parallel decoding produces logical errors from strings that a global decoder can correct.Source: B. Logical errors along the short edge · pp. 7–8
  • At modest physical noise, the minimum uncorrectable weight alone does not explain LER; the number of failing higher-weight errors can dominate when its entropy outweighs their lower probability.For example, the cited d = 15, w = 3 case has minimum weight 4 yet over two orders of magnitude lower LER than a globally decoded distance-8 code at p = 0.1%.Source: B. Logical errors along the short edge · pp. 8–9

C. Logical errors along the long edge

Along the long edge, the LER gap between parallel and global decoding stays constant as buffer width grows. When window A’s horizontal dimension exceeds d, the added long-edge LER is negligible compared with short-edge errors.

C. Logical errors along the long edge

  • A weight-5 string can confuse a distance-9 window within a distance-13 patch: the window prefers a weight-4 incorrect matching, producing a long-edge logical error.The string is not long enough to confuse a global decoder on the full patch.Source: C. Logical errors along the long edge · p. 9
  • When window A’s horizontal dimension exceeds d, added long-edge LER is negligible compared with short-edge errors and need not guide buffer-width selection.The reported parallel-decoding LER also coincides with that of global decoding on a patch the size of window A.Source: C. Logical errors along the long edge · p. 9

D. Generalizing to 2D configurations

The study tests staggered-window decoding on wider merged patches motivated by lattice-surgery operations. In these configurations, LER falls exponentially with buffer width and can pass the isolated-patch baseline before the buffer exceeds half the commit-region width.

D. Generalizing to 2D configurations

  • The simulations use two vertically stacked square patches deformed into rectangles for Y ⊗Y measurement before merging, with baselines from isolated square or rectangular patches.The tested window layouts use five windows stacked in two rows.Source: D. Generalizing to 2D configurations · p. 9, Figure 13 · p. 10
  • LER is suppressed exponentially with w and falls below the pre-merge isolated-patch baseline before w exceeds half the commit-region width.The buffers extend in both directions, using extra distance present during the logical operation.Source: D. Generalizing to 2D configurations · pp. 9–10, Figure 14 · p. 10
  • In one layout, vertical-operator errors are higher because two windows with short horizontal intersections act before a neighboring window; the alternative schedule avoids this condition.The difference between the layouts is attributed to the order in which windows act.Source: D. Generalizing to 2D configurations · p. 10, Figure 14 · p. 10

E. Implications

Buffer width should be tuned to physical noise and the desired match to global-decoder fidelity. Window intersections also constrain achievable fidelity, especially when a patch spans multiple commit regions.

E. Implications

  • A buffer width around d/2 is a general starting point, adjusted for physical noise and the desired match to the global decoder’s logical error rate.Use a larger width for lower physical noise or a closer match; a smaller width may suffice for higher noise or a looser match.Source: E. Implications · p. 10
  • Linear settings require larger buffer widths than multi-row settings, and their logical error rate is dominated by errors along the shorter edge.Source: E. Implications · p. 10
  • When a patch spans multiple commit regions, its intersection with a commit region should not be smaller than half that region.Too-small intersections can produce large logical errors; with w at least d/2 in the described case, the patch intersection is at least d wide.Source: E. Implications · p. 10

VI. THROUGHPUT

Spatially parallel decoding is pipelined across overlapping windows, with throughput determined by the slower of inter-window communication and the inner decoder. The section assesses communication and inner-decoder limits against the roughly 1 µs measurement-cycle target.

VI. THROUGHPUT

  • The throughput benchmark is average decoder time per measurement round, with ∼1 µs set as the real-time target.Source: §VI · p. 10
  • Each window receives control-system information and data from neighboring windows, then sends committed corrections to runtime and artificial defects to later-layer neighbors.Source: §VI · p. 10
  • The decoder’s throughput is set by the slower of inter-window communication and the inner decoder in the pipeline.Source: §VI · pp. 10–11
  • Figure 15 diagrams the spatially parallel real-time decoder, with colored squares corresponding to the windows in Figure 6.Source: Figure 15 · p. 11

A. Inter-window communication

The analysis estimates the data exchanged between neighboring windows and compares FPGA communication time with the real-time measurement-cycle target. It concludes that inter-window communication does not constrain window size.

A. Inter-window communication

  • The message-size estimate combines bits per defect with the expected defect count; Figure 16 plots defect counts from the same simulations as Figure 8 and fits Poisson curves.Source: A. Inter-window communication · p. 11, Figure 16 · p. 11
  • Each artificial defect requires ⌈log2(d2/2)⌉ bits in the staggered-square configuration, including 9 bits for d = 23–32 and 12 bits for d = 65–89.The estimate assumes d × d commit regions and d measurement cycles processed at once.Source: A. Inter-window communication · p. 11
  • Artificial-defect counts are independent of buffer width, depend strongly on physical noise, and are fit by Poisson distributions whose mean is roughly proportional to noise and intersection area.Source: A. Inter-window communication · p. 11
  • At p = 0.1% and d ∼30, the mean is ∼5 artificial defects, requiring about 90 bits total across both decoding graphs per neighboring-window link, without further optimization.Source: A. Inter-window communication · p. 11
  • 7 ns per measurement cycle at p = 0.1% for d ≤30 and below 3 ns at d = 151; at p = 0.5%, overhead falls from 44 ns at d = 5 to below 9 ns at d = 151.The authors conclude inter-window communication does not limit window size.Source: A. Inter-window communication · p. 11

B. Inner decoders

The maximum supported window size depends on inner-decoder design and throughput, while lower physical noise creates competing effects on buffer size and decoder speed. The conclusion identifies inner-decoder scalability, rather than inter-window communication, as the window-size constraint.

B. Inner decoders

  • The approach is layered over any real-time inner decoder, so the maximum window size has no single answer independent of decoder choice.Source: B. Inner decoders · p. 12
  • Helios uses O(d3) processing elements and its runtime decreases with d until board-to-board FPGA communication is needed; a later update supports 51 × 51 patches at increased latency.Source: B. Inner decoders · p. 12
  • CC’s FPGA runtime increases with d but stays below 1 µs through d = 23; the analysis estimates a d = 51 inner decoder corresponds to a commit-region width of ∼25.The estimate accounts for sliding windows and assumes a buffer slightly wider than half the commit region; ASICs may support larger distances longer term.Source: B. Inner decoders · p. 12
  • At low physical noise, wider accuracy-preserving buffers enlarge windows, while many decoders run faster because physical errors are sparse.For throughput-limited decoders such as CC, these effects compete in setting maximum window size.Source: B. Inner decoders · p. 12

VII. CONCLUSION

  • Inter-window communication is not the window-size bottleneck; inner-decoder scalability limits window size, so accuracy, throughput, and hardware cost require balancing.Larger windows reduce inner-decoder throughput and/or require more resources.Source: §VII · p. 12

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