Roadmap to Neuromorphic Computing with Emerging Technologies

1.1. Taxonomy & Motivation

• AI’s rising energy demands and environmental impact motivate improving computing-system energy efficiency for both large models and low-power devices.The passage distinguishes data-center power consumption from running mid-sized models on self-contained systems with milliwatt-level budgets.Source: §1.1 · p. 3
• Neuromorphic computing draws on advantageous features of biological systems, but no single architecture is expected to suit every application.The passage notes that biological systems are specialized and heterogeneous.Source: §1.1 · p. 4
• The roadmap focuses on brain-inspired computing applications and emphasizes materials engineering across CMOS and post-CMOS technologies.It places this focus within broader computing-system challenges and neuromorphic approaches.Source: §1.1 · p. 5

1. Introduction to the roadmap

• The roadmap spans computing challenges, mature and emerging technologies, material challenges, novel computing concepts, and technology maturity.Its coverage includes SRAM and Flash, emerging device materials, spiking systems, analog computing, and content-addressable memory.Source: §1.1 · pp. 5–6

2.1.1. Status

• Von Neumann systems separate CPU and memory, while technology scaling and parallel processing have improved performance and enabled heterogeneous processors.Modern systems integrate specialized accelerators alongside general-purpose processing units.Source: §2.1.1 · p. 6

2.1.2. Challenges

• Slowing Moore’s and Dennard scaling, alongside the memory wall, makes continued performance and energy-efficiency gains increasingly difficult.The end of Dennard scaling has increased the importance of energy efficiency and contributed to dark silicon.Source: §2.1.2 · pp. 6–7

2.1.3. Potential Solutions and Conclusion

• Data movement between memory and processing is a primary performance and energy impediment, while cache and prefetching only partly mitigate the memory bottleneck.Caches depend on locality and have limited capacity; prefetching is ineffective for complicated access patterns and increases complexity and bandwidth consumption.Source: §2.1.2 · pp. 6–7, §2.1.3 · p. 7
• Tighter integration of logic and memory could reduce data-movement costs; processing-in-memory and neuromorphic computing offer a brain-inspired approach but affect the full system stack.Memristive technologies can provide analog data storage that also supports computation.Source: §2.1.3 · pp. 7–8

3.1 What is neuromorphic computing/engineering

• Neuromorphic systems perform event- or data-driven neural computation in physical time, spanning sensing, processing, and learning.Spiking neural networks compute as spikes are transmitted and received, with neurons updating internal states and firing when thresholds are reached.Source: §3.1 · p. 8

3.1.1. Neuromorphic Sensing

• A DVS emits signed, time-stamped address events when pixel illumination changes beyond preset thresholds, providing fine timing resolution for dynamic scenes.The described camera records over 10 million events per second; a 7 KHz spiral produces hundreds of events over about 400 us.Source: §3.1.1 · p. 8, Figure 2 · p. 9

3.1.2. Neuromorphic Processing

• Less than 2 ms is needed for the combined sensor and spiking network to recognize a changing card, versus two typically 25 ms image acquisitions in conventional systems.The example uses frame-free event encoding and a spiking convolutional network to switch recognition between poker symbols.Source: §3.1.2 · p. 9, Figure 3 · p. 10

3.1.3. Challenges and Conclusion

• Training powerful systems directly on neuromorphic hardware remains a challenge; mapping conventionally trained deep networks to spiking counterparts has caused performance loss.Proposals include direct spiking-domain training using Spike-Timing-Dependent plasticity variants and surrogate techniques adapting backpropagation.Source: §3.1.3 · p. 11

3.2.1. Status

• Neuromorphic hardware spans CMOS systems, non-volatile memories proposed for synapses or neurons, and emerging memristive devices and materials.The roadmap describes CMOS platforms as current large-scale systems, while NVMs developed for storage remain emerging in neuromorphic computing despite market introduction.Source: §3.2.1 · pp. 11–13, Figure 4 · p. 12

3.2.2. Challenges

• NVM nonidealities—including variability, drift, limited programmable levels, and endurance constraints—can affect neural-network accuracy and reliability.Emerging materials and concepts remain largely at single-device or early proof-of-concept stages, with ANN or SNN implementations often demonstrated only in simulation.Source: §3.2.2 · p. 14

3.2.3. Potential Solutions

• Advancement calls for common benchmarking and coordinated materials, device, architecture, and algorithm co-design, alongside online-learning algorithms and sustainable fabrication.The roadmap concludes that prototypes remain early-stage and that integrating emerging concepts into functional systems requires long-term materials research and understanding of physical principles.Source: §3.2.3 · pp. 14–15, §3.2.4 · p. 15

3.3. Possible future computational primitives for neuromorphic computing

• Memristive circuits offer candidate neurons, synapses, and in-memory blocks, while volatile-device dynamics and hybrid electronic, spintronic, or photonic designs broaden possible computing primitives.Quantum reservoir computing with quantum memristors is presented as a possible route to larger reservoir state spaces and relaxed decoherence requirements compared with traditional quantum computing.Source: §3.3 · pp. 15–16

4.1.1 Status

• SRAM CIM faces power-delivery and sensing challenges, and analog designs add ADC/DAC area and energy overhead while trading density and accuracy against functionality.Standard 6T cells are common for robustness and speed, but parallel access can short cell contents; modified cells and peripheral circuits seek to support computation while preserving density and limiting requalification costs.Source: §4.1.1 · pp. 17–18

4.1.2 Challenges and Potential Solutions

• Digital CIM embeds element-wise multiplication and accumulation in SRAM arrays, whereas analog current- and charge-based approaches accumulate row operations through readout circuits.Digital CIM reduces data movement and supports runtime voltage/frequency tuning, but its energy efficiency declines as operand precision rises; analog approaches face variability, nonlinearities, SNR, and readout-throughput limits.Source: §4.1.2 · pp. 19–20, Figure 7 · p. 19

4.1.3 Conclusions

• Analog CIM accuracy and throughput depend on readout dynamic range, ADC precision, and MVM parallelism, while noise-aware training still needs validation on larger models and datasets.Charge-based approaches show lower variability than current-based ones, but both remain limited by accumulation dynamic range; noise-aware training evidence is mainly from small academic networks and datasets.Source: §4.1.3 · pp. 20–21
• Digital SRAM CIM offers a deterministic, scalable path for general-purpose edge acceleration, while analog CIM trades accuracy limits for greater parallelism and energy efficiency in suitable applications.The roadmap concludes that both approaches retain substantial scope for improvement and may eventually be combined for different neural-network modalities.Source: §4.1.3 · p. 21

4.2.1 Status

• Flash arrays are being explored as ANN parameter storage and active VMM computing media, but NOR and NAND architectures bring different access, capacity, and cost trade-offs.NOR targets fast random access with independently connected cells, while NAND uses series strings for lower area and higher density; 3-D NAND supports high-capacity storage. Flash-based ANN concepts have been demonstrated with both types.Source: §4.2.1 · pp. 21–22, §4.2.3 · p. 23

Challenges arising from changes in the design strategy of the array

• Adapting Flash arrays for ANNs can alter their cost and performance: changing segmentation affects NOR speed or NAND cost, while capacity and fixed string organization constrain network size and topology.NOR is described as suitable for ANNs with fewer than 1 Giga parameters and NAND for more than 1 Giga parameters; single-cell erase solutions can also affect cost, performance, or reliability.Source: Challenges arising from changes in the… · pp. 22–23

Challenges arising from array reliability

• Flash-array computing reliability is not assured by storage reliability, and the accuracy and stability required for ANN operation remain to be demonstrated under known device constraints.Periodic threshold-voltage recalibration and on-chip learning may mitigate reliability issues; peripheral circuitry must also avoid severe area, cost, power, and reliability burdens.Source: Challenges arising from array… · p. 23, Challenges arising from the peripheral… · p. 23, §4.2.3 · p. 24

4.2.3 Conclusion

• Flash could serve both as ANN storage and as an active computing medium, but realizing that role requires engineering and scientific advances in array design, reliability, and peripheral circuitry.The roadmap identifies these as the challenges to address for Flash-based neuromorphic computing.Source: §4.2.3 · pp. 23–24

• The section passage lists Zhongrui Wang and J. Joshua Yang.Source: §5 · p. 24

5.1.1. Status

• Crossbar arrays store matrices as conductances and use circuit laws for vector-matrix multiplication, keeping data storage and processing in the same location.Resistive switches are electrically tunable resistors whose switching can involve mobile anions or cations.Source: §5.1.1 · pp. 24–25
• Resistive memory has been used for graph, image, audio, text, and structured-data tasks, including graph classification, image learning, sequence modeling, and tabular analysis.The figure caption also summarizes capabilities spanning 3D points and events.Source: §5.1.1 · p. 25, Figure 9 · p. 26

5.1.2. Challenges

• Challenges arise at device, circuit, and algorithm levels, including programming precision, energy and speed, conversion costs, parasitic IR drop, and performance loss from nonlinearities.Source: §5.1.2 · pp. 26–27

5.1.3. Potential Solutions

• Proposed responses include filament confinement, denoising, circuit changes, and hardware-software codesign that can exploit programming or reading noise.Some approaches trade higher program energy or time for lower stochasticity; reducing switching barriers can compromise retention and thermal stability.Source: §5.1.3 · p. 27

5.1.4. Conclusion

• Resistive switch-based in-memory computing has demonstrated a wide spectrum of machine-learning and neuromorphic applications across data types.Device-, circuit-, and algorithm-level improvements are still needed to fully realize its potential.Source: §5.1.4 · p. 27

5.2.1.Introduction

• PCM stores analogue conductance by varying the amorphous region, while successive partial SET pulses progressively crystallize material and increase conductance.Crossbar arrays use the conductance states for matrix-vector multiplication; the accumulative property supports DNN training and other learning dynamics.Source: 5.2.1.Introduction · p. 28, Figure 10 · p. 28
• PCM is commercialized as standalone and embedded memory, with write operations in tens of nanoseconds and endurance that can exceed a billion cycles depending on device geometry.Intermediate-state retention can be substantially shorter than retention of fully RESET states.Source: 5.2.1.Introduction · p. 29, 5.2.2.Challenges · p. 29

5.2.2.Challenges

• High integration density is a primary challenge: smaller features raise edge-effect and thermal-cross-talk concerns, while selector choices must balance precise programming and scalability.DNN inference may require 10–100 million on-chip weights; vertically stacked crossbars can help achieve density.Source: 5.2.2.Challenges · p. 29, Figure 11 · p. 29

5.3.1.Status

• Ferroelectrics offer three readout schemes—switched charge, transistor drain current, and tunnelling-barrier modulation—whose flexibility is useful beyond memory applications.Traditional ferroelectric materials have faced integration difficulties and scaling limits, while hafnia and zirconia improve fabrication compatibility but bring reliability challenges.Source: 5.3.1.Status · p. 30, 5.3.2.Challenges · p. 30

5.3.2.Challenges

• Hafnia- and zirconia-based devices face imprint, wake-up, fatigue, and endurance issues, while neuromorphic use additionally requires suitable switching linearity, retention, and integration density.Source: 5.3.2.Challenges · pp. 30–31

5.3.3. Potential Solutions

• Potential solutions include controlling phase formation under realistic fabrication conditions and engineering film stacks and electrode interfaces to manage oxygen transport.At nanoscale, abrupt accumulative switching may mimic neurons, while tailored retention can support short- and long-term synaptic plasticity.Source: §5.3.3 · p. 31, Figure 12 · p. 32

5.4.1. Status

• MTJ synapses can be binary, multilevel, or analogue; their resistance depends on current history, and several mechanisms can tune storage-layer states.Options include domain-wall propagation, gradual magnetic switching, granular storage, skyrmion nucleation, and changing the relative magnetization angle.Source: §5.4.1 · p. 33, Figure 13 · p. 33

5.4.2. Challenges

• Spintronic neurons may avoid the large area of conventional CMOS integrate-and-fire circuits, but STNO neuron triggering still requires DC power in the mW range.Switching speed, endurance, device variability, and interconnection also need improvement.Source: §5.4.1 · p. 33, §5.4.2 · p. 34

5.4.1. Status

• STNO arrays have demonstrated spoken-digit or vowel recognition, using current-driven conductance oscillations that mimic spike generation.Their oscillation frequency and amplitude vary with applied current and magnetic field.Source: §5.4.1 · p. 33
• Superparamagnetic MTJs can generate Poisson spike trains and support probabilistic computing, while high-stability MTJs can store synaptic weights at low bias and operate as neurons at high bias.Self-heating at high bias reduces the thermal stability factor for neuron operation.Source: §5.4.1 · p. 34

5.4.2. Challenges

• MTJs offer write endurance and narrower resistance-state distributions than RRAM or PCRAM, but their ROFF/RON ratio is about 4 versus 10 to 100.Crossbars need high-resistance MTJs to limit power; resistance change control and temperature effects also challenge circuit design.Source: §5.4.2 · p. 34

5.4.3. Potential Solutions

• Potential development paths include materials to improve magnetoresistance and switching, stacked spintronic structures, and long-range links using spin currents, magnons, magnetic textures, or light.Magnetic stacks can be grown on sufficiently smooth substrates, enabling three-dimensional stacking, though with added complexity and cost.Source: §5.4.3 · pp. 34–35

5.4.4. Concluding remarks

• Spintronic neuromorphic circuits may begin with commercial STT-MRAM, followed by analogue MTJ crossbars and circuits using interacting STNOs for learning and inference.Speed, reliability, scalability, and variation tolerance remain challenges for practical applications.Source: §5.4.4 · p. 35

5.5.1. Status

• Photonic approaches target either task-specific accelerators such as matrix-vector multiplication or hardware emulating neurons, synapses, learning, and spiking networks.Individual photonic neuron and synapse components have demonstrated brain-like behaviors.Source: §5.5.1 · p. 35
• Photonic neuromorphic systems have demonstrated task-specific networks, including on-chip neurosynaptic image recognition using phase-change material for synapses and nonlinear activation.Other demonstrations include vowel recognition and a three-layer deep neural network with in-situ training.Source: §5.5.1 · p. 35

5.5.2. Challenges

• Silicon photonics lacks second-order nonlinearity and light emission, so neural systems may combine silicon synapses with neurons on other material platforms, requiring compact, fabrication-tolerant optical interconnects.The system illustration shows input encoding, photonic processing, detection back to electronics, and memory storage.Source: §5.5.2 · p. 36, Figure 14 · p. 36
• Digital-electrical inputs and analogue optical processing require ADCs and DACs; co-packaging electronics with photonics can significantly increase footprint and cost, reducing throughput.Fabrication imperfections can also shift component operating wavelengths and require active thermo-optic trimming circuitry.Source: §5.5.2 · pp. 36–37
• A smaller EOM VpiL indicates improved power efficiency and a more compact modulator, important as photonic circuits scale under on-chip power and space constraints.VpiL relates the applied voltage and modulator length needed for a pi phase shift.Source: §5.5.2 · p. 37

5.5.3. Potential Solutions

• Electro-optic polymers integrated with silicon waveguides show very low VpiL among fast modulators; micro-transfer printing, flip-chip bonding, and photonic wire bonding are proposed integration routes.Monolithic fabrication is also proposed to co-locate photonics and electronics.Source: §5.5.3 · p. 37
• VCSEL neurons can emit thresholded excitable spikes, and one VCSEL layer combined with a software spiking network has performed 4-bit image recognition.Flip-chip-bonded two-dimensional VCSEL arrays on silicon are proposed for fully hardware systems and larger experiments.Source: §5.5.3 · p. 37

5.5.4. Concluding remarks

• Neuromorphic photonics offers high throughput, low latency, and high power efficiency, but more compact, cascadable, fabrication-friendly implementations are still needed.The roadmap expects large-scale networks to scale through integration of available packaging techniques.Source: §5.5.4 · pp. 37–38

5.6.1. Status

• CVD-grown h-BN memristors have demonstrated bipolar switching endurance above 5 million cycles, threshold-regime switching energy of about 8.8 zJ, and yield near 98%.The reported devices also show highly controllable potentiation and relaxation in the threshold regime.Source: §5.6.1 · p. 38
• Stable ionic-movement resistive switching has been demonstrated in CVD- and LPE-prepared 2D materials, while solution-processed devices have not shown equivalent performance after sub-μm downscaling.CVD-grown h-BN is reported to have the strongest performance so far among these devices.Source: §5.6.1 · pp. 38–39
• 2D materials can also switch through ferroelectric effects, and their responsive properties may support near- or in-sensor neuromorphic functions; reported ferroelectric endurance and retention remain limited to hundreds of cycles.Stable ferroelectric resistive switching at the single-layer limit remains unexplored.Source: §5.6.1 · p. 39

5.6.2. Challenges and Potential Solutions

• Good switching in devices larger than 10 μm2 does not establish performance in devices below 1 μm2, where reduced defect density can raise forming voltage and alter key device metrics.The passage identifies endurance as the most difficult figure of merit to obtain in small devices.Source: §5.6.2 · p. 39
• Scaling examples include CVD h-BN devices with limited yield and device counts at 320 nm × 420 nm, and solution-processed MoS2 devices without reported equivalent performance at 500 nm × 500 nm.Random current overshoot caused irreversible dielectric breakdown in most of the smaller h-BN devices; nanoflake size may limit MoS2 scaling.Source: §5.6.2 · p. 39
• Integrating CVD-grown h-BN onto a CMOS transistor enabled instantaneous current limitation in a 0.053 μm2 device and could support heterogeneous back-end integration of selector devices.Selector devices are identified as fundamental for large memristive synapse arrays.Source: §5.6.2 · p. 39
• Next steps include improving material quality and reproducibility, tuning thickness and defect density for nanoscale devices, and wafer-scale growth; monolayers can produce high leakage under out-of-plane fields.Scalable synthesis of single-crystal multilayer h-BN has been reported, but controlling layer count and conducting electrical studies remain necessary.Source: §5.6.2 · p. 40

5.6.3. Concluding remarks

• The roadmap calls for small devices made by scalable methods, measurement of application-relevant figures of merit across more than 100 devices, clear yield and variability reporting, and disclosure of failure modes.It notes that many academic proof-of-concept studies omit key metrics or use characterization protocols that can overestimate performance.Source: §5.6.3 · p. 40

6.1.1. Scaling

• Scaling advances include 11 nm STT-MRAM cells and nanoscale PCM and ReRAM, but MTJ readout, reliable ultrathin ferroelectric hafnia, PCM RESET current, and ReRAM retention remain challenges.For ReRAM below 10 nm, oxygen loss may limit retention; stable nanoscale filaments and oxygen-vacancy confinement are proposed as potential solutions.Source: §6.1.1 · pp. 41–42

6.1.2. Speed

• Neuromorphic operation is application-timed, while demonstrated memory switching speeds range from picoseconds to milliseconds depending on device and material composition.Human signal timescales are typically milliseconds or longer; PCM crystallization time, for example, can be tuned from 25 ns to 10 ms by adjusting composition.Source: §6.1.2 · p. 42

6.1.4. Endurance

• Endurance requirements differ by use: learning stresses endurance, while inference requires stable states and read-disturb robustness; MRAM endurance is effectively unlimited, but memristive devices have limits.VCM ReRAM has demonstrated > 10^6 cycles, with some reports above 10^10; ferroelectric wake-up and fatigue arise from defect motion, while material confinement and multiPCM synapses may mitigate endurance or variability issues.Source: §6.1.3 · p. 42, §6.1.4 · p. 42

6.1.5. Retention

• Retention, read disturb, and variability depend on device state and material: ReRAM and PCM can degrade gradually, while programmed bipolar VCM ReRAM HRS has been extrapolated stable for years at read voltages up to 350 mV.Device-to-device variation can be reduced through fabrication optimization and cycle-to-cycle variation through programming algorithms, but read-to-read noise remains; variability may also be exploited in neuromorphic systems.Source: §6.1.5 · pp. 42–43, §6.1.6 · p. 43, §6.1.7 · p. 43

6.1.8 Analog operation

• Analog operation requires multiple states, but their control depends on domains in ferroelectric or magnetic devices and on switching kinetics and variability in ReRAM and PCM.FTJ and FeRAM multilevel switching has been demonstrated by tuning programming voltages; PCM partial-reset pulses and controlled ReRAM SET currents can produce intermediate states.Source: §6.1.8 · pp. 43–44

6.2.2.Challenges and Potential Solutions

• Memristive-device characterization requires complementary structural, chemical, and electrical methods, since nanoscale filaments and oxygen movement are difficult to observe directly.CAFM tomography maps connected conductive regions in three dimensions, while combined microscopy, spectroscopy, mass spectrometry, and modelling can probe oxygen movement; moisture and hydrogen also complicate analysis.Source: 6.2.1.Status · p. 44, 6.2.2.Challenges and Potential Solutions · pp. 44–45

6.2.3. Concluding Remarks

• Electrical characterization can reveal transport and switching mechanisms, but electroforming requires fast current limiting; progress also depends on collaboration across experimental techniques and modelling.Integrated resistors or transistors help avoid damaging current overshoot, and close collaboration has enabled advances such as CAFM tomography while hydrogen's role remains insufficiently characterized.Source: 6.2.2.Challenges and Potential Solutions · p. 46, §6.2.3 · p. 46

6.3.1. Status

• The surveyed device families trade off capabilities: nonvolatile TMOs support multilevel states and in-memory computing but face forming, nonlinear programming, variation, and noise; Mott TMOs offer neuron-like threshold switching but remain temperature-sensitive.PCM supports multilevel conductance and MVM but faces conductance drift and slow, energy-intensive crystallization; MRAM offers high endurance and reliability but has low resistance and a small on/off ratio that limits multilevel use.Source: §6.3.1 · pp. 46–47
• FTJs offer low-power programming and multilevel conductance, but ferroelectric materials can suffer retention degradation, while HZO has relatively high coercive voltages and low endurance.PZT and SBT are more mature and used in commercial memory; HZO is CMOS-compatible and scalable, while wurtzite materials offer high on/off ratio, thermal stability, and retention.Source: §6.3.1 · p. 48
• IGTs provide low-power programming and more linear weight modulation, but current devices have limited standard-process compatibility and are difficult to fabricate in large-scale arrays.TMO is a common channel material, and phosphosilicate glass electrolyte is more mature and CMOS-process compatible than previously used Li-ion electrolytes.Source: §6.3.1 · p. 48

6.3.2.Conclusion

• Memristive devices enable promising neuromorphic engines and systems, but material-dependent maturity and cost leave technical challenges that can be addressed or exploited through materials, systems, and algorithms.For example, algorithms can reduce the effects of conductance drift and programming noise or use array variations and noise to accelerate computation.Source: 6.3.2.Conclusion · p. 48

7.1.1. Status

• Nanodevice variability supports lower-power random number generators, adjustable p-bits for Ising machines, and programming-variability-based MCMC training.Cycle-to-cycle and programming variability underpin these approaches; the figure contrasts filamentary memristors with stochastic magnetic tunnel junctions.Source: §7.1.1 · pp. 49–50, Figure 16 · p. 49

7.1.2. Challenges

• Practical use requires controlled imperfection: enough variability for stochastic computation without sacrificing device reliability and stability.Manufacturing, environmental, and atomic-scale factors complicate modeling; superparamagnetic junctions can also be sensitive to magnetic fields.Source: §7.1.2 · p. 50

7.1.3. Potential Solutions

• Potential solutions distinguish read and programming cycle-to-cycle variability from device-to-device variation, which can also support unique PUF signatures.The exploitable physics is device-dependent: hafnium-oxide memristors favor the low-resistance state, while device ensembles can improve statistical properties and robustness.Source: §7.1.3 · pp. 50–51

7.1.4. Concluding remarks

• Variability-based applications require selecting exploitable imperfections, understanding device physics, and maintaining controlled variability; ensembles may improve reliability and stability.The section concludes that these steps are central to harnessing nanodevices for stochastic computing.Source: §7.1.4 · p. 51

7.2.1. Status

• SNNs process inputs as temporal spikes, with membrane-potential dynamics providing internal memory and making sequential event data a promising fit.Analog inputs still require encoding, while event streams can be processed directly; encoding choices affect latency and accuracy.Source: §7.2.1 · pp. 51–53

7.2.2. Challenges and Potential Solutions

• SNN training remains challenging: surrogate-gradient methods can reach high accuracy but retain intensive workloads and substantial inference latency, while large-scale equilibrium-propagation implementation remains difficult.Temporal pruning, regularizers, and modified neuron models have reduced latency to a single timestep in some approaches.Source: §7.2.2 · p. 53
• Neuromorphic hardware must address SNN sparsity and timestep-related memory costs, and available device technologies trade endurance, energy, speed, variability, and precision.The passage notes no single device technology is currently a winner.Source: §7.2.2 · p. 53

7.2.3. Conclusion

• The section positions temporal applications as a likely niche for SNNs and calls for coordinated algorithm and hardware development.Examples include video, reinforcement learning, speech, and control under low-power requirements.Source: §7.2.3 · pp. 53–54

7.3.1. Status

• Crosspoint RRAM arrays implement matrix-vector multiplication by applying input voltages and collecting row currents; the approach has shown more than two orders of magnitude improvement in throughput and energy efficiency.Conductance compensation also supports matrices with negative entries using the same number of transimpedance amplifiers.Source: §7.3.1 · p. 54
• Feedback AMC circuits implement matrix inversion, generalized inverses, and eigenvector computations; inversion can lose precision for ill-conditioned matrices and is suited to analog preconditioning.The eigenvector circuit is self-sustained, while sparse approximation circuits can solve compressed-sensing recovery problems in one step and the microsecond regime.Source: §7.3.1 · pp. 54–55, Figure 18 · p. 55, Figure 19 · p. 55

7.3.2. Challenges

• Closed-loop AMC remains limited to small demonstrations because global feedback can stress devices, amplify non-idealities, and risk instability from parasitic effects.The passage contrasts this with fabricated large-scale arrays used for MVM acceleration.Source: §7.3.2 · p. 56
• Scaling AMC requires balancing array size against accuracy while improving conductance programming, error recovery, reconfigurable circuits, and application-specific software.RRAM endurance remains a critical issue linked to ionic migration; test-method innovations alone are unlikely to resolve it.Source: §7.3.2 · p. 56, §7.3.3 · p. 57

7.3.3. Potential Solutions

• BlockAMC partitions large matrices across arrays and combines MVM and inversion to recover solutions, while bit slicing can extend MVM precision but is difficult to apply to inversion.Analog-digital hybrids may be needed for higher-precision inversion; nonlinear closed-loop tasks may better tolerate analog errors.Source: §7.3.3 · p. 57

7.3.4. Conclusion

• AMC remains largely at the laboratory-prototype stage, with next steps spanning reliable conductance programming, scalable architectures and algorithms, non-ideality mitigation, reconfigurability, and applications.The roadmap also calls for nonlinear AMC circuits and near- and long-term application scenarios.Source: §7.3.4 · pp. 57–58

7.4.1. Status

• Memristor-based analog CAMs store ranges and match analog inputs within them, while decision-tree ensembles can map to parallel, one-cycle inference with digital outputs.Each root-to-leaf path is encoded in a row, with the leaves' predictions stored in conventional RAM.Source: §7.4.1 · p. 59

7.4.2. Challenges

• Analog CAMs still lack large-array validation, with memristor variation, noise, parasitics, and nonlinear programming complicating reliable search.A general architecture with sufficient data bandwidth, multiple cores, programmability, and error resilience also remains to be designed.Source: §7.4.2 · pp. 59–60

7.4.3. Potential Solutions

• Proposed next steps include CMOS-integrated large arrays, more stable memristor stacks, circuit-aware programming, and programmable multi-core architectures.Suggested measures include tailored logic between CAM cells and error detection with device reprogramming.Source: §7.4.3 · p. 60

7.4.4. Conclusion

• CMOS-integrated memristive CAMs and scaled system-level performance analysis have yet to be demonstrated, leaving their application potential open.The conclusion also calls for exploring applications using open-sourced circuit models.Source: §7.4.4 · p. 60

7.5.1. Status

• Optimization solvers target computationally expensive combinatorial problems, and proposed physical realizations include Ising systems, analog neural networks, quantum approaches, and dynamical solvers.These approaches can combine different algorithmic paradigms with flexible physical substrates.Source: §7.5.1 · pp. 60–61

Challenges of mapping to hardware

• Higher-order problems such as k-SAT require auxiliary variables to reduce interactions to quadratic terms, potentially imposing an exponential search-space penalty.Ising models use pairwise binary-spin couplings and provide no explicit mechanism for enforcing additional constraints.Source: Challenges of mapping to hardware · p. 61

Scaling challenges

• For a K-city traveling-salesman problem, the typical QUBO encoding uses N = K^2 variables, while hardware embedding and decomposition can further reduce quality or increase solution time.Naive programmable coupling requires N^2 weights, and limited connectivity can add embedding overhead and exponential slowdown.Source: Challenges of mapping to hardware · p. 62, Scaling challenges · p. 62, Figure 21 · p. 62

Precision challenges

• Emerging devices must provide enough weight precision and sufficiently accurate couplings and node updates to avoid distorting global energy minima.Training neural networks offers a limited analogy: many deep-learning models require at least 4-bit weight and dot-product precision for highest accuracy.Source: Precision challenges · pp. 62–63

7.5.3. Potential Solutions

• Potential improvements span QUBO mappings, device implementations, and flexible architectures, while benchmarks should compare solution quality against hardware time under fixed power and resource budgets.Analog memory, optical interconnects, and quantum annealing are identified as attractive device directions; the schematic tradeoff spans fast lower-quality solvers and slow complete approaches.Source: §7.5.3 · pp. 63–64, Figure 22 · p. 64

7.5.4. Conclusions

• Physics- and brain-inspired optimization approaches have potential, but practical large-scale solvers require progress across materials, circuits, systems, and algorithms, with input from non-hardware users.The conclusion emphasizes continuous feedback among users, developers, material scientists, and engineers.Source: §7.5.4 · p. 64

8.1.1. Status

• SRAM in-memory accelerators have demonstrated >100 TOPS/W for 4-bit matrix-vector multiplication, while a nor-Flash accelerator reported 3.3 TOPS/W at 8-bit precision.PCM and RRAM have reached multi-core chips and neural-network inference demonstrations; several other emerging technologies remain at single devices or small arrays.Source: §8.1.1 · p. 65

8.1.2.Challenges

• Inference and training impose different device requirements, and simultaneously meeting array-scale specifications for endurance, retention, variability, and resistance remains difficult.Inference prioritizes retention and low drift, whereas training requires high endurance and symmetric conductance updates.Source: 8.1.2.Challenges · pp. 65–66
• Power-hungry output conversion, peripheral area, digital workloads, communication, and software integration can constrain system-level performance.High-efficiency analog cores also need nearby efficient digital blocks, with spatial mapping and communication co-designed.Source: 8.1.2.Challenges · p. 66, 8.1.3.Potential Solutions · p. 66

8.1.3.Potential Solutions

• Proposed improvements include stabilizing conductance for 4-to-5-bit precision, integrating dense arrays, reducing ADC area, and coordinating analog and digital core placement.Fully analog peripherals may save power but impose stricter precision and activation-function limits.Source: 8.1.3.Potential Solutions · p. 66

8.1.4.Conclusion

• Product-level in-memory computing aims for 4-to-5-bit precision and 100/200 TOPS/W, requiring uniform, low-noise devices, compact peripherals, and careful spatial mapping.The roadmap presents these as specifications and development needs, not demonstrated product-level results.Source: 8.1.4.Conclusion · p. 67

• Memristive behavior depends on material choice, dimensions, and interacting physical processes, while nanoscale operating conditions can make device behavior depart from macroscopic expectations.The roadmap identifies phase change, redox reactions, ionic transport, electronic effects, van der Waals forces, and magnetic effects among reported mechanisms.Source: §9 · p. 67
• The roadmap aims for a broad perspective on materials, devices, and system design, but does not elaborate on several promising neuromorphic approaches.Examples listed include adaptive matter, computation based on disorder, organic perovskites, ionic-liquid devices, and molecular devices.Source: §9 · p. 68
• The most suitable material system depends on application requirements, and recommendations must account for the gap between academic proof-of-concept work and industrial economic feasibility.The passage contrasts embedded-system integration needs with endurance needs for computing applications.Source: §9 · p. 68
• Neuromorphic technologies may use digital, analog, or different computing and signal-processing paradigms.The passage describes these technologies as contenders for future computing.Source: §9 · p. 68