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Hardware-efficient quantum error correction via concatenated bosonic qubits

Harald Putterman, Kyungjoo Noh, Connor T. Hann, Gregory S. MacCabe, Shahriar Aghaeimeibodi, Rishi N. Patel, Menyoung Lee, William M. Jones, Hesam Moradinejad, Roberto Rodriguez, Neha Mahuli, Jefferson Rose, John Clai Owens, Harry Levine, Emma Rosenfeld, Philip Reinhold, Lorenzo Moncelsi, Joshua Ari Alcid, Nasser Alidoust, Patricio Arrangoiz-Arriola, James Barnett, Przemyslaw Bienias, Hugh A. Carson, Cliff Chen, Li Chen, Harutiun Chinkezian, Eric M. Chisholm, Ming-Han Chou, Aashish Clerk, Andrew Clifford, R. Cosmic, Ana Valdes Curiel, Erik Davis, Laura DeLorenzo, J. Mitchell D'Ewart, Art Diky, Nathan D'Souza, Philipp T. Dumitrescu, Shmuel Eisenmann, Essam Elkhouly, Glen Evenbly, Michael T. Fang, Yawen Fang, Matthew J. Fling, Warren Fon, Gabriel Garcia, Alexey V. Gorshkov, Julia A. Grant, Mason J. Gray, Sebastian Grimberg, Arne L. Grimsmo, Arbel Haim, Justin Hand, Yuan He, Mike Hernandez, David Hover, Jimmy S. C. Hung, Matthew Hunt, Joe Iverson, Ignace Jarrige, Jean-Christophe Jaskula, Liang Jiang, Mahmoud Kalaee, Rassul Karabalin, Peter J. Karalekas, Andrew J. Keller, Amirhossein Khalajhedayati, Aleksander Kubica, Hanho Lee, Catherine Leroux, Simon Lieu, Victor Ly, Keven Villegas Madrigal, Guillaume Marcaud, Gavin McCabe, Cody Miles, Ashley Milsted, Joaquin Minguzzi, Anurag Mishra, Biswaroop Mukherjee, Mahdi Naghiloo, Eric Oblepias, Gerson Ortuno, Jason Pagdilao, Nicola Pancotti, Ashley Panduro, JP Paquette, Minje Park, Gregory A. Peairs, David Perello, Eric C. Peterson, Sophia Ponte, John Preskill, Johnson Qiao, Gil Refael, Rachel Resnick, Alex Retzker, Omar A. Reyna, Marc Runyan, Colm A. Ryan, Abdulrahman Sahmoud, Ernesto Sanchez, Rohan Sanil, Krishanu Sankar, Yuki Sato, Thomas Scaffidi, Salome Siavoshi, Prasahnt Sivarajah, Trenton Skogland, Chun-Ju Su, Loren J. Swenson, Stephanie M. Teo, Astrid Tomada, Giacomo Torlai, E. Alex Wollack, Yufeng Ye, Jessica A. Zerrudo, Kailing Zhang, Fernando G. S. L. Brandão, Matthew H. Matheny, Oskar Painter

arXiv:2409.13025v2quant-ph

TL;DR

Quantum error correction is needed for algorithms requiring trillions of error-free gate operations, but current hardware remains about nine orders of magnitude away. This work demonstrates a concatenated bosonic-cat and repetition-code memory; its current logical error is dominated by intrinsic cat errors, with the authors projecting improvement to about 0.5% per cycle under proposed changes.

  • Problem

    Currently proposed algorithms require trillions of error-free gate operations, while state-of-the-art qubit error rates remain about nine orders of magnitude from that requirement.

    Source: §I · p. 2

  • Method

    The memory suppresses cat-qubit bit flips with bosonic encoding and corrects residual phase flips using an outer repetition code.

    Source: §I · p. 2, §VII · p. 9

  • Results

    The current device’s logical error is dominated by intrinsic cat bit-flip and phase-flip errors, and the authors project distance-5 logical error per cycle approaching 0.5% after proposed improvements.

    Source: §VII · p. 9

  • Takeaways & Limitations

    The experiment is a first step toward hardware-efficient QEC and highlights the scalability potential of planar-microfabricated concatenated bosonic qubits.

    Source: §VII · p. 9

    Ancilla-transmon double decay and heating do not currently limit performance but would ultimately impose a lower bound on the repetition-cat-code logical error probability.

    Source: §VII · p. 9

Abstract

from arXiv · show

In order to solve problems of practical importance, quantum computers will likely need to incorporate quantum error correction, where a logical qubit is redundantly encoded in many noisy physical qubits. The large physical-qubit overhead typically associated with error correction motivates the search for more hardware-efficient approaches. Here, using a microfabricated superconducting quantum circuit, we realize a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance $d=5$. The bosonic cat qubits are passively protected against bit flips using a stabilizing circuit. Cat-qubit phase-flip errors are corrected by the repetition code which uses ancilla transmons for syndrome measurement. We realize a noise-biased CX gate which ensures bit-flip error suppression is maintained during error correction. We study the performance and scaling of the logical qubit memory, finding that the phase-flip correcting repetition code operates below threshold, with logical phase-flip error decreasing with code distance from $d=3$ to $d=5$. Concurrently, the logical bit-flip error is suppressed with increasing cat-qubit mean photon number. The minimum measured logical error per cycle is on average $1.75(2)\%$ for the distance-3 code sections, and $1.65(3)\%$ for the longer distance-5 code, demonstrating the effectiveness of bit-flip error suppression throughout the error correction cycle. These results, where the intrinsic error suppression of the bosonic encodings allows us to use a hardware-efficient outer error correcting code, indicate that concatenated bosonic codes are a compelling paradigm for reaching fault-tolerant quantum computation.

I. INTRODUCTION

Practical quantum algorithms require error-free computation across trillions of gate operations, while current hardware remains far from that regime. This work combines bosonic cat-qubit protection with an outer repetition code to build a hardware-efficient logical memory.

I. INTRODUCTION

  • Trillions of error-free gate operations are required by currently proposed algorithms, while state-of-the-art qubit error rates remain about nine orders of magnitude from that requirement.Quantum error correction can reduce errors by redundantly encoding information across noisy physical qubits.Source: §I · p. 2
  • Bosonic encodings use a mode’s extra dimensionality for native error protection, and concatenating them with an outer code can reduce overall QEC resource overhead.Prior bosonic-mode experiments have used cat, binomial, and GKP codes.Source: §I · p. 2
  • The demonstrated memory stabilizes cat qubits so bit flips are suppressed physically, while an outer repetition code corrects residual phase flips across bosonic modes.The work realizes a distance-5 code and uses a noise-biased CX gate for syndrome measurements with ancilla transmons.Source: §I · p. 2

II. QUANTUM DEVICE REALIZING A DISTANCE-5 REPETITION CODE OF CAT QUBITS

The device concatenates cat qubits hosted in five bosonic storage modes with a distance-5 repetition code measured by four transmon ancillas. Two-photon dissipation stabilizes the cat states and maintains their noise bias.

II. QUANTUM DEVICE REALIZING A DISTANCE-5 REPETITION CODE OF CAT QUBITS

  • The distance-5 device uses five bosonic storage modes as data qubits and four transmon ancillas to measure repetition-code stabilizers.The storage resonators couple to ancillas through tunable couplers; two bump-bonded chips carry the device’s linear and nonlinear elements.Source: §II · p. 2, Figure 1 · p. 3
  • Cat-qubit bit flips are phase-space rotations between |α⟩ and |−α⟩, while phase flips exchange even and odd cat-state parity.Bit-flip rates can be exponentially suppressed as cat size increases, whereas phase flips arise from single-photon loss and heating.Source: §II · p. 2
  • Two-photon dissipation stabilizes each cat amplitude by coupling the storage mode to a lossy buffer that dissipates photon pairs.A driven buffer supplies the complementary two-photon drive, and a four-pole filter protects storage lifetime from the strong buffer loss channel.Source: §II · p. 3
  • At |α|2 = 2, stabilized cat qubits have greater than 1 ms bit-flip times and 27–33 µs phase-flip times, yielding noise bias greater than 30.Bit-flip times increase exponentially with mean photon number, while phase-flip times decrease as 1/|α|2.Source: §II · p. 4

III. NOISE-BIASED CX GATES IN THE REPETITION CAT CODE

The CX gate must preserve cat-qubit bit-flip suppression despite ancilla errors that can propagate to the data qubits. The authors use a χ-matched transmon-storage interaction and pulsed cat stabilization to make the gate noise-biased.

III. NOISE-BIASED CX GATES IN THE REPETITION CAT CODE

  • A CX gate can propagate ancilla errors into data-cat bit flips, so the gate must minimize unwanted target flips to preserve the cat qubits’ noise bias.Ordinary |g⟩/|e⟩ transmon encoding allows |e⟩→|g⟩ decay during the gate to dephase the cat state and induce bit flips.Source: §III · pp. 4–5
  • Encoding the ancilla in |g⟩ and |f⟩ with χge ≃ χgf keeps the storage rotation similar after |f⟩→|e⟩ decay, suppressing decay-induced cat bit flips.Sequential decay events or heating can still cause bit flips.Source: §III · p. 5
  • Two-photon dissipation after the CX gate corrects many storage-state misrotations and distortions, while omitting stabilization allows errors to accumulate over repeated cycles.The measured Wigner tomograms show the storage mode rotating conditionally on the ancilla state during the gate.Source: §III · p. 5
  • The CX2 characterization sequence is first-order insensitive to ancilla-state preparation errors, as in a stabilizer measurement cycle.CX2 replaces a single CX with its two-gate equivalent for the repeated-cycle characterization.Source: §III · p. 5
  • At |α|2 ≥3, repeated CX2 cycles with the ancilla in |g⟩+|f⟩ retain bit-flip times over 1 ms, while |g⟩+|e⟩ yields times well under 1 ms.At |α|2 = 2, the measured per-cycle bit-flip and phase-flip errors are (3.5 ± 0.4) × 10−3 and (9.6 ± 0.4) × 10−2, respectively.Source: §III · p. 5

IV. CORRECTING PHASE-FLIP ERRORS WITH THE REPETITION CODE

The repetition code corrects cat-qubit phase flips below threshold across the measured photon-number range, with distance 5 outperforming distance 3. The study also characterizes logical bit flips, which are passively suppressed by the cat encoding rather than corrected by the outer code.

IV. CORRECTING PHASE-FLIP ERRORS WITH THE REPETITION CODE

  • Across the measured photon-number range, the distance-5 repetition code has lower logical phase-flip probability than the distance-3 subsections, indicating operation below threshold.Including erasure information reduces the distance-5 logical phase-flip rate by about 20% at |α|2 = 1.5.Source: Figure 3 · p. 6, §IV · p. 7
  • Stabilizer detection probabilities remain approximately constant over time, which the authors attribute to dissipative stabilization preventing leakage accumulation without active leakage-suppression protocols.Detection probabilities increase with photon number, reflecting increasing cat-qubit phase-flip rates.Source: §IV · p. 6
  • Three-state transmon readout identifies |f⟩→|e⟩ decays as erasures, and excluding erased syndromes from decoding reduces measurement error by over a factor of two at |α|2 = 1.An erased syndrome provides no data-qubit error information and is omitted when constructing detectors.Source: §IV · pp. 6–7
  • The fitted logical phase-flip scaling exponent rises from 1.63 ± 0.04 and 1.86 ± 0.03 for the two distance-3 sections to 2.31 ± 0.02 for distance 5.The increase indicates greater phase-flip resilience at increased code distance; the measured exponents are below ideal values but consistent with simulations.Source: Figure 3 · p. 6, §IV · p. 7

A REPETITION CAT CODE

  • At |α|2 = 4, logical bit-flip error per cycle falls below 0.5% for both distance-3 sections and below 1% for distance 5.At |α|2 = 1, the corresponding errors are approximately 2% for distance 3 and 4% for distance 5; distance 5 has more bit-flip error locations.Source: A REPETITION CAT CODE · p. 8, Figure 4 · p. 8
  • A phenomenological model combining photon-number-dependent idling errors and photon-number-independent CX errors agrees with measurements, indicating no significant integrated bit-flip performance degradation.The model’s component error probabilities are fit from independent cat-qubit and CX characterization experiments.Source: A REPETITION CAT CODE · p. 8

VI. OVERALL MEMORY LIFETIME AND ERROR BUDGET

The logical error per cycle is minimized at different cat photon numbers for the distance-3 and distance-5 codes, with the distance-5 minimum comparable to the best distance-3 results. At the distance-5 optimum, intrinsic cat errors dominate the error budget.

VI. OVERALL MEMORY LIFETIME AND ERROR BUDGET

  • 1.65% ± 0.03% overall logical error per cycle at |α|^2 = 1.5 for d=5, versus 1.83% ± 0.03% and 1.67% ± 0.04% at |α|^2 = 1 for the two d=3 sections.The distance-5 value is comparable to the best measured distance-3 performance.Source: §VI · p. 8, Figure 5 · p. 9
  • For each |α|^2 ≥ 1.5, the distance-5 logical error rate is lower than that of the distance-3 sections, as noise bias lets the larger code benefit from phase-flip suppression.The phase-flip contribution dominates above |α|^2 = 1.5.Source: §VI · p. 9
  • The d=5 error budget separates cat and CX bit-flip errors from cat and CX phase-flip and syndrome-measurement errors; intrinsic cat errors dominate near |α|^2 ≃ 1.5.Bit-flip mechanisms dominate at small photon number, while phase-flip mechanisms dominate at large photon number.Source: §VI · p. 9

VII. CONCLUSION AND OUTLOOK

The work demonstrates a concatenated bosonic code, using cat qubits to suppress bit flips and a repetition code to correct residual phase flips, in a planar-microfabricated logical memory. The authors report near-term improvement strategies and discuss transmon-related limits and longer-term alternatives.

VII. CONCLUSION AND OUTLOOK

  • The experiment combines cat-code bit-flip suppression with repetition-code correction of residual phase flips, and planar microfabrication highlights the architecture’s potential scalability.Source: §VII · p. 9
  • Near-term cycle-time and cat bit-flip improvements project an overall logical error per cycle approaching 0.5% with a d=5 code, even without better component coherence times.The projection is limited by transmon errors.Source: §VII · p. 9
  • Ancilla transmon double decay and heating would ultimately bound logical error, while transmon coherence improvements could lower that floor and noise-biased surface-code layouts offer a scalable alternative.Source: §VII · pp. 9–10
  • Cat-ancilla approaches could reduce overhead if gates were limited by intrinsic cat errors, but current cat-cat CX proposals are hampered by large control errors.The cited performance examples assume coherence-limited gates and are idealized hypotheticals.Source: §VII · p. 10

IX. AUTHOR CONTRIBUTIONS

The author contributions span device architecture and fabrication, experiment development and execution, data analysis, and project oversight.

IX. AUTHOR CONTRIBUTIONS

  • The transmon-ancilla architecture, CX gate, device parameters, circuit-level modeling, and device design were developed or led by the named contributors.Source: §IX · p. 10
  • Contributors led fabrication, fridge and instrumentation setup, calibration, and repetition-code experiment protocols; H.P. performed the experiment.Source: §IX · p. 10
  • H.P. led data analysis, C.H. implemented erasure-information decoding and performance simulations, and the project was managed by M.M. and overseen by F.B. and O.P.Source: §IX · p. 10

Supplemental information for ”Hardware-efficient quantum error correction via

The supplemental material describes the device fabrication and control-line and fridge setup for the repetition-code device.

Appendix A: Device fabrication

  • The device pairs separately fabricated aluminum-based qubit and tantalum-based storage dies by flip-chip bonding, with indium bumps and bond-stop spacers.Source: Appendix A · p. 14
  • Separate die processes support high-coherence tantalum storage modes, favorable ancilla-storage frequency alignment, and reduced junction-energy imperfections in smaller qubit dies.Source: Appendix A · pp. 14–15

Appendix B: Control lines and fridge setup

  • The buffer uses symmetric and antisymmetric flux controls, a driven input, a filtered output, and a Σ-line flux pump for two-photon dissipation; storage, coupler, and ancilla controls are separately routed.Source: Appendix B · p. 15
  • The fridge setup is duplicated across unit cells, with cryoswitching enabling multiple buffer readouts on one line; temperature cycling shifts problematic TLS frequencies.The authors note tunable-frequency ancillas could minimize the need for temperature cycling.Source: Appendix B · p. 15

Appendix C: Basis and error rate convention

The appendix fixes cat-qubit basis and logical-error conventions, then describes device mechanisms and models relevant to the noise-biased CX gate. It covers buffer-induced effects and a Kerr-model condition for χ-matching.

Appendix C: Basis and error rate convention

  • Even/odd cat states define the complementary basis; parity measurement reads X, while displaced-vacuum population enables single-shot Z readout.Source: Appendix C · p. 15
  • The repetition code's XiXi+1 stabilizers extract dominant cat Z-error syndromes, but any single-qubit X can act logically, making physical bit-flip suppression essential.Source: Appendix C · p. 15

Appendix D: Device Hamiltonian

  • Two-photon dissipation stabilizes cat amplitude, while χge≈χgf at coupler-on flux makes bit-flip rates first-order insensitive to ancilla |e⟩ population; dissipation and flux pulses do not overlap.Source: Appendix D · p. 17

1. Buffer mode for implementing two-photon dissipation

  • A 4-pole filter protects storage from buffer loss; parasitic Kerr and near-resonant sideband processes can degrade bit-flip performance or add parity flips.Source: §1 · p. 18

2. Simple Kerr oscillator model of the CX gate and χ-matching

  • For negative transmon anharmonicity, approximate χ-matching occurs when storage frequency exceeds ancilla frequency by |Kq|, about 200 MHz.Source: §2 · pp. 18–19

3. Full circuit-quantization-level numerical model of the CX gate and χ-matching

A circuit-quantization model captures coupler-dependent frequencies and dispersive shifts used to design χ-matching for the CX gate. At the operating point, its predicted ratio closely matches the measured ratio and differs from the perturbative prediction.

3. Full circuit-quantization-level numerical model of the CX gate and χ-matching

  • The full model includes neighboring buffer, readout, and coupler modes and uses DMRG-X because these elements affect storage and ancilla properties beyond the simple Kerr model.Source: §3 · p. 19
  • At coupler minimum, measured χge/χgf is 1.04, full-model prediction is 1.05, and perturbative prediction is 1.13.Source: Figure 7 · p. 19, §3 · p. 20
  • Asymmetric level repulsion increases storage-ancilla detuning near half flux, and χge/χgf approaches 1 as the coupler reaches its operating point.Source: Figure 7 · p. 19, §3 · p. 20
  • At the operating point, χge and χgf are each around −1 MHz, while storage self-Kerr stays below 5 kHz across relevant ancilla states.Source: §3 · p. 20
  • If flux pulses are not adiabatically ramped relative to 40–150 MHz detuning, spectral weight can drive iSWAP-like exchange, heating the ancilla and degrading cat bit-flip times.Source: §3 · p. 20

Appendix E: Frequency targeting procedure for achieving the χ-matching condition

This appendix section describes frequency and interaction tuning, gate calibration, readout, and characterization procedures for device and repetition-code operation. It also covers χ-mismatch mitigation, buffer-pump crosstalk compensation, and examples of device instability.

Appendix E: Frequency targeting procedure for achieving the χ-matching condition

  • A1 and A2 anharmonicities were tuned by 5%, lowering their frequencies by approximately 100 MHz and yielding measured 1.03 < χge/χgf < 1.12.The passage says these ancillas otherwise would not have achieved these ratios without the frequency-tuning procedure.Source: Appendix E · p. 21

1. Mode frequencies and coherences

  • Couplers idle at maximum frequencies above 8.5 GHz, with minima of 6.25–6.75 GHz; reported ancilla coherences are representative snapshots that vary over time and with coupler flux.Ancilla and storage frequencies in Fig. 9 were measured with couplers at their idle, maximum-frequency positions.Source: §1 · p. 21, Figure 9 · p. 22

2. Storage T1 and T2 measurements

  • Storage T1 and T2 degraded under pure two-photon dissipation; buffer-pump-induced resonances caused heating, which frequency arrangement can remedy.The shifted steady-state parity and decreased lifetime were attributed to buffer-pump-induced heating; the passage expects frequency arrangements that avoid the resonances to prevent these effects.Source: Figure 10 · p. 22, §2 · p. 23

3. Ancilla transmon readout and reset

  • Ancilla |g⟩/|e⟩ SPAM error was under 2% on every ancilla, averaging 1.5%, and reset pulses lasted 504 ns.The |e⟩ and |f⟩ populations reached the readout floor after reset.Source: Figure 11 · p. 23, §3 · p. 24

4. Storage-ancilla dispersive couplings

  • Across eight storage–ancilla interactions, χge/χgf ranged from 0.85 to 1.3, and seven had less than 20% χ-mismatch; the repetition-code experiment tolerated small mismatches.S4–A4 was the exception with mismatch above 20%.Source: Figure 12 · p. 24, §4 · p. 25

5. Two-photon dissipation calibration

  • Two-photon dissipation calibration yielded g2/2π of 300–450 kHz and dissipation rates of 27–65 kHz.Storage detuning was calibrated to order 1 kHz or less, while buffer detuning was calibrated to approximately 1 MHz; residual storage detuning can degrade cat-qubit bit-flip times.Source: Figure 13 · p. 25, §5 · p. 26

6. Displacement and dissipation amplitude calibrations

  • Displacement calibrations agreed within 2%; buffer-drive calibrations before and after the experiment were consistent within 1% ∼8% at |α|2 = 1 and 1% ∼3% at |α|2 = 2.The buffer-drive calibration maps drive amplitude to mean photon number using a linear model.Source: §6 · pp. 26–27, Figure 14 · p. 27

7. CX (and CX2) gate calibration procedure

  • CX and CX2 gate parameters were refined by optimizing bit-flip rates using repeated syndrome-extraction-like cycles, each lasting 3 µs.The sequence prepares the storage in |+α⟩, applies ancilla preparation, a CX or CX2 gate, unpreparation, readout and reset, and storage stabilization between coupler pulses.Source: §7 · p. 27
  • CX2 gate lengths are tuned to maximize cat-qubit bit-flip time, while CX gate lengths are tuned in the repetition-code stabilizer circuit because they are sensitive to ancilla preparation errors.For CX2, calibration uses an ancilla prepared in |f⟩ and requires ancilla reset; storage phase shifts are optimized by measuring bit-flip time across gate lengths.Source: §7 · pp. 28–29

8. Dissipative map assymmetry

  • Simulations indicate negative buffer detuning near −5 MHz can reduce A4 ↔ S4 CX2 bit-flip probabilities by almost half, while positive detuning can increase them.The measured dissipative map favors recovery from positive phase shifts at the nominal detuning, estimated as ∆b,0/(2π) ≃ −2 MHz.Source: Figure 17 · p. 30, §8 · p. 31

7. CX (and CX2) gate calibration procedure

  • CX2 bit-flip times exceed 1 ms for seven of eight interactions at sufficiently large |α|²; A4 ↔ S4 is an outlier with χge/χgf ≃ 1.3.All eight interactions have effective storage-mode lifetimes T1,eff above 50 µs. The A4 ↔ S4 mismatch can cause ancilla decay to misrotate the storage mode by over 90° and trigger bit flips.Source: Figure 16 · p. 29, §7 · p. 30

9. Examples of noise affecting repetition code performance

  • Device performance examples outside the repetition-code run include fluctuating storage-mode T2, direct ancilla |f⟩→|g⟩ decay, and TLS-related ancilla population loss during coupler flux pulses.The observed direct decay was most pronounced around |α|² = 10; TLSs can cause ancilla loss, especially at the coupler on-position.Source: Figure 18 · p. 31, §9 · p. 32

1. Single-shot Z-basis measurement of a cat qubit

  • Symmetrizing the ±α displacements makes the single-shot Z-readout POVM diagonal in the computational basis at any |α|², though assignment infidelities remain at large photon number.Infidelities saturate for |α|² ≳ 3 due to effective transmon readout and vacuum-selective ancilla π-pulse errors.Source: §1 · pp. 33–34

2. Calibrating the CX gate length for the repetition code

  • CX gate lengths were chosen by maximizing the logical bit-flip time of each corresponding d = 2 repetition code, with maxima validating the selected lengths.Ancilla state preparation errors do not affect these bit-flip-time measurements because the stabilizer acts trivially on the repetition-code states. The calibration omits ancilla readout but retains reset.Source: §2 · p. 34

3. In situ calibrations of CX gate for repetition code operation

  • Before each run, storage and ancilla phase corrections are optimized in parallel across unit cells, respectively maximizing storage bit-flip times and minimizing stabilizer detection probability.The central storage mode’s calibration depends most on whether it is at the boundary or center of the repetition-code section; ancilla phase minima are fit quadratically.Source: §3 · pp. 34–35, Figure 21 · p. 35

4. Crosstalk cancellation

  • Buffer flux-pump crosstalk can excite readout resonators, dephasing ancillas and impairing reset; readout-line compensation tones cancel the crosstalk in steady state.Pump transients are not canceled, so conservative pump turn-on padding remains important; residual effects can elevate detection fractions on the A4 stabilizer in the d = 5 experiment.Source: Figure 22 · p. 35, §4 · p. 36

5. Repetition code X basis pulse sequences

  • For logical X-lifetime characterization, storage modes are initialized in even or odd cat states, undergo repeated stabilizer-measurement rounds (five in the illustrated sequence), and are finally read out.The rounds use a conservative 2.8 µs cycle time; an additional ef π pulse enables detection of ancilla |f⟩→|e⟩ decay during readout as an erasure error.Source: §5 · pp. 36, 38

6. Repetition code Z basis pulse sequences

  • The logical Z-lifetime sequence prepares storage modes in coherent states and uses the same central-cycle device pulses as the X-basis sequence, but does not digitize central-round outcomes.The authors report a Z-basis experiment with digitization to confirm that detection probabilities are commensurate with the X-basis experiment despite the different initialization.Source: §6 · p. 38, Figure 24 · p. 39

7. Repetition code characterization procedure

  • Characterization interleaves measurements and calibrations for the d = 3 and d = 5 sections, applies identical calibrations across sections, and combines the runs for analysis.The procedure includes logical X- and Z-basis data collection and takes roughly 6 hours; storage lifetimes are characterized only for d = 5 and do not update calibration.Source: §7 · pp. 38–40

Appendix H: Repetition Code Data Analysis

This appendix describes fitting logical lifetimes and decoding repetition-code syndromes, including erased measurements. Erasure-aware decoding changes detector construction and edge weights; the observed detector correlations support a Pauli error model.

1. Fitting procedure for the logical lifetimes

  • Shot disagreements are estimated with a uniform-prior beta-binomial model, converted to logical correlations, and fit with uncertainty-weighted exponential decays.The Z fits have no offset, while the X fits allow a small constant offset.Source: §1 · p. 40

2. Decoding without erasure information

  • Without erasure handling, binary syndrome changes form detection events, and correlation-derived edge weights feed minimum-weight perfect matching on a Pauli-error graph.Source: §2 · p. 40

3. Decoding with erasure information

  • Erasure-aware decoding replaces clusters of erased-syndrome detectors with detectors built from non-erased syndromes, then updates edge probabilities for the longer intervals.Source: §3 · pp. 41–42
  • The erasure-aware decoder yields slightly longer logical lifetimes than zero-weighting erased edges, chiefly for shots with multiple consecutive erasures.Source: §3 · p. 42

4. Correlations in detection events

  • Spatial, temporal, and diagonal detector correlations are explained by a Pauli error model, motivating the decoder’s restricted edge set.Source: §4 · p. 43

5. Syndrome measurement error rate versus |α|2

The appendix examines how syndrome-edge probabilities, detection rates, and storage lifetimes behave across photon number, code distance, and initialization basis. It also reports logical bit-flip probabilities for different initial states and an ancilla control condition.

5. Syndrome measurement error rate versus |α|2

  • Spacelike edge probabilities rise with |α|^2, while timelike probabilities also increase, especially for A4, because fixed gate lengths do not track photon-number-dependent nonlinear shifts.A3 shows barely any timelike-edge increase; tuning gate length separately for each photon number could mitigate the measurement-error degradation.Source: §5 · p. 43

6. Comparison of detection probabilities between distance-3 and distance-5 experiments

  • Detection probabilities are consistent across distances on A1–A3; A4 is 1–2% higher and fluctuates in distance 5, attributed to S1 flux-pump crosstalk.Increasing flux-pump padding removed the fluctuations in another dataset.Source: §6 · p. 44, Figure 28 · p. 44

7. Comparison of detection probabilities between X and Z basis initialization

  • Bulk detection probabilities are consistent between X- and Z-basis initialization; first and final rounds differ because the initial stabilizer state is nondeterministic for Z-basis preparation.The comparison uses twice-interleaved repetition-code experiments.Source: §7 · p. 44, Figure 29 · p. 44

8. Effective storage T1 during repetition code experiments

  • Storage-mode T1,eff values are consistent within 5% across repetition-code segments and all exceed 50 µs; phase-flip rates increase linearly with |α|^2.The rates are fit to γphase-flip = κ1,eff|α|^2, with κ1,eff = 1/T1,eff.Source: §8 · p. 45, Figure 30 · p. 45

9. Comparison of logical Z lifetime for the two different initial states and with ancilla in g

  • At |α|^2 = 4, logical bit-flip error probability is measured at ∼3×10^-3 for the distance-5 section, while distance-3 sections show probabilities under 2×10^-3.Source: §9 · p. 45

10. Distribution of initial states in logical X lifetime experiments

At low photon number, asymmetric cat phase-flip rates bias initial repetition-code states toward even cats and make logical decay depend on the initial state. The measured phase-flip scaling falls below ideal expectations, while simulations identify the error-rate regime as relevant to that scaling.

10. Distribution of initial states in logical X lifetime experiments

  • At |α|² = 1, initial repetition-code states are heavily biased toward higher numbers of |+⟩ states and grouped decay curves vary significantly; at |α|² = 1.5, the distribution is more symmetric and curves almost identical.The study compares analytical predictions with experimentally measured steady parities.Source: §10 · p. 47
  • Low-error initial states are overrepresented, biasing fitted bit-flip times upward at low photon number, especially for distance 3; this dispersion collapses by |α|^2 = 1.5.For grouped initial states at low photon number, the decay need not be purely exponential, while the overall decay rate is fit from steady-state samples.Source: §10 · p. 47

11. Explanation of distance-3 and distance-5 TX scaling with |α|2

  • Measured scaling exponents are γ = 1.63(4) and 1.86(3) for the two distance-3 codes and γ = 2.31(2) for distance 5, below ideal values 2 and 3.Simulations likewise predict lower-than-ideal scaling.Source: §11 · p. 47
  • With syndrome measurement errors set to zero, simulations find ideal scaling emerges as pZ decreases; the experimental pZ range of about 5%–17% is too high for leading-order scaling agreement.Photon-number-dependent syndrome measurement errors can also increase the measured γ relative to constant syndrome error.Source: §11 · pp. 47–48, Figure 33 · p. 48

Appendix I: Simulated logical performance and error budgets

The appendix describes simplified simulations and error-budget methods for estimating logical phase- and bit-flip performance, then gives idealized logical-error projections. Simulated and measured phase-flip data agree reasonably, and the d = 5 budget separates several physical error contributions.

1. Simulated logical phase-flip performance

  • Simulated and measured phase-flip times agree reasonably, and both show scaling exponents below the ideal γ = 3 for a distance-5 repetition code.The Monte Carlo model uses cat phase-flip, syndrome measurement, and optional ancilla-erasure probabilities, inferred from measured lifetimes and matching-graph edge weights.Source: §1 · p. 48

2. Simulated logical bit-flip performance

  • The logical bit-flip model sums per-cycle cat-idling and CX bit-flip probabilities, with idling errors assumed to decrease exponentially with |α|^2.The CX contributions are inferred from CX2 measurements after accounting for cat-idling probability; the model averages over ancilla |g⟩ and |f⟩ states.Source: §2 · p. 49

3. Logical error budget

  • The d = 5 error budget apportions phase- and bit-flip contributions by component, but aggregates syndrome measurement because it contributes least to the overall budget.The budget includes idling cat phase flips, idling cat bit flips, CX bit flips, and syndrome measurement errors; its approximate additivity reflects the experiment’s non-ideal scaling at relatively high physical error rates.Source: §3 · pp. 49–50

4. Logical performance estimates assuming idealized coherence-limited, bias-preserving gates

  • For coherence-limited gates, both examples use d = 11 and Tcycle = 1 µs, estimating overall logical errors per cycle of 3.8 × 10^-6 and 3.3 × 10^-8, respectively.The first assumes T1 = 300 µs and TZ = 1 s at |α|^2 = 5; the second assumes T1 = 1 ms and TZ = 100 s at |α|^2 = 7.Source: §4 · p. 50

Appendix J: Simulated CX performance and error budgets

The appendix uses CX simulations to examine physical mechanisms behind gate-induced cat bit flips, including an effective enhancement of ancilla decay during gate operation. It tunes selected parameters against measured data and reports general qualitative agreement between simulated and measured bit-flip probabilities.

Appendix J: Simulated CX performance and error budgets

  • CX simulations examine mechanisms behind gate-induced cat bit flips, with particular attention to effective enhancement of ancilla decay during gate operation.The simulations assess tolerance to χ mismatch and construct error budgets for individual gates.Source: Appendix J · p. 50

1. CX simulations and parameters

  • Simulated CX2 bit-flip probabilities generally agree qualitatively with measurements, and agree quantitatively at some photon numbers, although parameters were tuned for agreement at |α|^2 = 4.The simulations combine measured Hamiltonian parameters with fitted storage-dephasing, coupler-heating, and ancilla-decay rates; they assume a 1% ancilla |f⟩ preparation error into |e⟩.Source: §1 · pp. 50–51

2. Ancilla T1

The appendix investigates ancilla decay and χ mismatch as contributors to CX bit-flip errors. It finds that ancilla decay dominates the illustrated gate error budgets, while engineered dissipation makes the gates tolerant to modest χ mismatch.

2. Ancilla T1

  • Post-selecting shots where an initially |f⟩ ancilla decayed to |g⟩ makes its CX2 bit-flip probability comparable to the |g⟩-initialized case, implicating effective ancilla decay.Without post-selection, the probability is significantly higher for initial |f⟩.Source: §2 · p. 52
  • Applying the readout drive does not significantly change measured CX2 bit-flip probabilities, so it is not the cause of the enhanced ancilla decay investigated here.The ancilla was in a superposition of |g⟩ and |f⟩ during readout.Source: §2 · p. 52
  • At |α|2 = 4, simulations require an ancilla T1 reduction of β ≈2.5, versus a measured pulsed reduction of β ≈1.5; temporal fluctuations and TLS effects complicate interpretation.Pulsed T1 measurements show degradation, but combine coupler-on and -off periods and transients.Source: §2 · p. 52

3. CX χ-matching tolerance

  • Repetition-code cycles tolerate χ mismatches up to |χge/χgf − 1| ≲0.2 without significant additional logical bit-flip error, versus ≲0.1 for CX2 gates.Engineered dissipation corrects small mismatch-induced storage rotations; the greater tolerance reflects the shorter CX gate.Source: §3 · pp. 53–54

4. CX bit-flip error budgets

  • Ancilla transmon decay dominates both illustrated CX error budgets, and removing χ mismatch in simulation significantly reduces the expected bit-flip error for the poorly matched A4, S4 gate.The A4, S5 gate is well χ matched, unlike A4, S4.Source: §4 · p. 54

Appendix K: Additional error correction experiment data

Additional experiment runs use varied pulse parameters and include calibration and logical-state fit data. Across the datasets, the repetition code operates below threshold, with distance 5 outperforming distance 3 above the reported photon-number range.

Appendix K: Additional error correction experiment data

  • Supplementary data report ancilla and storage phase calibrations across three runs, plus logical X and Z fit data, including X fits grouped by initial |+⟩ count.The calibrations cover phase optimization for ancilla detection and storage bit-flip times.Source: Appendix K · p. 54, Figure 40 · p. 56, Figure 41 · p. 57
  • Across the additional datasets, the repetition code operates below threshold and distance 5 outperforms distance 3 for |α|2 ≳1.5; distance-5 logical bit-flip probabilities reach ~1% or less.Minimum measured logical errors per cycle for the distance-3 and distance-5 sections are comparable.Source: Appendix K · p. 55
  • Three other runs used different pulse parameters, including omission of an ef π pulse before readout; one |α|2 = 2 phase-flip lifetime fit excludes transient points.The excluded points would yield an artificially high lifetime.Source: Appendix K · p. 54, Figure 44 · p. 60
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