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Compiling the surface code to crossbar spin qubit architectures

Dávid Pataki, András Pályi

arXiv:2412.05425v1cond-mat.mes-hall

TL;DR

The paper addresses how to realize surface-code error correction in crossbar spin-qubit architectures despite shared-control constraints and many required control lines. It compiles stabilizer measurements into native gates, routing and scheduling protocols, and physical pulse sequences, finding a realistic parameter regime with below-threshold crosstalk and surface-code operation.

  • Problem

    Controlling thousands of spin qubits requires many control lines, motivating crossbar architectures and a compilation procedure for surface-code operations.

    Source: §I · p. 1

  • Method

    The authors decompose stabilizer circuits into native gates, update routing and scheduling, construct pulse sequences, and verify qubit shuttling.

    Source: §I · pp. 2–3

  • Results

    The study identifies an experimentally relevant parameter regime where crosstalk errors are below the surface-code threshold and enables below-threshold surface-code operation.

    Source: §I · p. 3, §VI · p. 15

  • Takeaways & Limitations

    Crossbar spin-qubit architectures can support compiled surface-code cycles with pulse-level design and verification addressing their shared-control constraints.

    Source: §I · p. 2, §VI · p. 15

Abstract

from arXiv · show

Spin qubits in quantum dots provide a promising platform for realizing large-scale quantum processors since they have a small characteristic size of a few tens of nanometers. One difficulty of controlling e.g., a few thousand qubits on a single chip is the large number of control lines. The crossbar control architecture has been proposed to reduce the number of control lines exploiting shared control among the qubits. Here, we compile the surface code cycle to a pulse sequence that can be executed in the crossbar architecture. We decompose the quantum circuits of the stabilizer measurements in terms of native gates of the spin-qubit architecture. We provide a routing and scheduling protocol, and construct a gate voltage pulse sequence for the stabilizer measurement cycle. During this protocol, coherent phase errors can occur on idle qubits, due to the operational constraints of the crossbar architecture. We characterize these crosstalk errors during the stabilizer measurement cycle, and identify an experimentally relevant parameter regime where the crosstalk errors are below the surface code threshold. Our results provide design guidelines for near-term qubit experiments with crossbar architectures.

I. INTRODUCTION

The paper compiles surface-code stabilizer measurements for crossbar spin-qubit architectures, addressing control-line scaling through shared control while translating circuits into executable pulse sequences. It updates routing and scheduling, constructs abstract and physical pulses, and characterizes crosstalk and logical-error behavior.

Motivation

  • Spin qubits offer small device dimensions, while crossbar control reduces control-line scaling from linear in qubit count to square-root scaling.The crossbar uses shared control in a two-dimensional quantum-dot array.Source: §I · pp. 1–2

Compilation framework

  • The compilation stack translates circuits into native gates, qubit routing and scheduling, abstract gate-voltage settings, and physical voltage and microwave pulses.The abstract sequence encodes gate-voltage structure, while the physical sequence specifies amplitudes, timings, and pulse shapes.Source: §I · p. 2, Figure 2 · p. 2

Surface-code compilation

  • The authors correct the native-gate decomposition of surface-code stabilizer circuits and update the routing and scheduling protocol for parallel operation.These changes correct quantitative errors in Ref. without altering its qualitative conclusions.Source: §I · p. 3

Logical-error scaling

  • For line-by-line operation, the authors determine an optimal code distance as a function of coherence and measurement times and identify a regime with logical error below physical error.This is described as break-even performance of the surface-code quantum memory.Source: §I · p. 3

Pulse construction and verification

  • The work constructs an abstract pulse sequence for parallel stabilizer measurement and develops a verification algorithm for adiabatic qubit shuttling.The algorithm checks whether specified gate-voltage changes generate the desired electron movements.Source: §I · p. 3

Crosstalk characterization

  • Crossbar constraints can cause coherent phase errors on idle qubits, but an experimentally relevant regime has estimated crosstalk below the surface-code threshold.The authors suggest these errors can be mitigated by surface-code error correction.Source: §I · p. 3

II. THE CROSSBAR SPIN QUBIT ARCHITECTURE

The crossbar architecture uses shared electrostatic control, alternating qubit frequencies, shuttling, native SWAP gates, and PSB readout to support surface-code stabilizer measurements.

II. THE CROSSBAR SPIN QUBIT ARCHITECTURE

  • The architecture is a two-dimensional quantum-dot array whose barrier gates control tunneling and diagonal plunger gates tune dot potentials under shared-control constraints.Source: §II · p. 3
  • Alternating column-by-column Larmor frequencies enable semi-global ESR addressing of even- and odd-column qubits.Source: §II · p. 3
  • Coherent shuttling moves qubits between sites and can induce z-axis rotations when traversing sites with different Larmor frequencies.Source: §II · p. 3
  • The architecture uses exchange-based SWAP gates between neighboring qubits and supports PSB or charge-sensor readout.Source: §II · p. 4
  • The study assumes perfect array uniformity while noting that shared control can induce unwanted rotations and spurious shuttlings.Source: §II · p. 4

A. Z-cycle circuit, X-cycle circuit with CNOT gates

B. Z-cycle circuit, X-cycle circuit using

The stabilizer circuits are compiled from CNOTs into native SWAP and single-qubit operations, then mapped to a parallel crossbar protocol using global ESR rotations and shuttling-based rotations.

B. Z-cycle circuit, X-cycle circuit using

C. Routing and scheduling protocol for parallel operation

B. Z-cycle circuit, X-cycle circuit using

C. Routing and scheduling protocol for parallel operation

D. Line-by-line implementation

The line-by-line implementation executes operations sequentially across columns or rows, with global rotations remaining parallel and most composite-step counts scaling with code distance.

D. Line-by-line implementation

E. Dependence of the logical error on the code distance

The paper estimates logical-error scaling by combining decoherence and operation errors with surface-code threshold formulas. Parallel operation maintains strong suppression, whereas line-by-line operation has an optimal code distance and becomes highly sensitive to coherence and measurement times.

Error model

  • The estimate models decoherence through qubit dephasing while assigning operation-induced error probability 10^-3 to each operation.Relaxation is neglected because dephasing is treated as the dominant spin-qubit decoherence mechanism.Source: E. Dependence of the logical error on… · pp. 7–8
  • The average per-cycle error estimate is an upper bound because boundary qubits may have lower gate counts.The analysis also notes that Gaussian rather than exponential decay could yield more favorable logical-error estimates at short times.Source: E. Dependence of the logical error on… · p. 8

Parallel operation

  • For parallel operation, the logical error probability falls below 10^-20 at code distance d ≈85 for both T*2 = 1 s and 10 ms.The reported precision is described as suitable for a fully functioning computer.Source: E. Dependence of the logical error on… · p. 8
  • The parallel-operation error-suppression factors are Λ ≈2.7 for T*2 = 1 s and Λ ≈2.6 for T*2 = 10 ms, largely independent of measurement time.These values are extracted from the estimated logical-error scaling.Source: E. Dependence of the logical error on… · pp. 8–9

Line-by-line operation

  • For line-by-line operation, logical error has a global minimum because cycle time scales linearly with code distance.The total cycle time is proportional to d for line-by-line operation but independent of d for parallel operation.Source: E. Dependence of the logical error on… · p. 8
  • At T*2 = 10 ms and τm = 100 ns, the line-by-line minimum is pL ≈10^-12 at d*=117, worsening to pL ≈10^-7 at d*=63 when τm = 1000 ns.The longer measurement time therefore produces a substantially higher minimum logical-error probability.Source: E. Dependence of the logical error on… · p. 8

IV. PULSE SEQUENCE FOR THE STABILIZER MEASUREMENT CYCLES

The paper constructs a practical physical pulse sequence for the surface-code stabilizer measurement cycle in the crossbar architecture. It also verifies shuttling steps, maps abstract controls to physical pulses, and estimates idle-qubit crosstalk errors.

IV. PULSE SEQUENCE FOR THE STABILIZER MEASUREMENT CYCLES

  • A complete implementation is built from abstract gate-voltage and ESR sequences, shuttling verification, physical pulse assignments, and crosstalk-error estimation.These stages establish the final control-stack layer for implementing the surface code with the crossbar architecture.Source: §IV · p. 9

A. Abstract pulse sequence

The abstract pulse sequence combines shared-control operations, qubit motion, native gates, and measurements while respecting crossbar constraints. A formal verification procedure checks that each shuttling step is compatible and produces the intended intermediate configuration.

A. Abstract pulse sequence

  • The protocol uses global single-qubit gates, qubit shuttling, shuttling-based phase gates, SWAP gates, and measurements.Parallel shuttling is non-trivial because the crossbar provides limited control over simultaneous movements.Source: A. Abstract pulse sequence · p. 9
  • Parallel operation can be represented with four repeating plunger-gate voltage values, plus a fifth value for spin-to-charge conversion.The pulse sequence only needs voltages on four consecutive diagonal plunger gates before applying the periodic pattern.Source: A. Abstract pulse sequence · p. 9
  • The abstract Z-cycle is expanded into elementary time steps specifying plunger values, barrier states, and ESR pulses, with the full 111-step sequence supplied separately.The first steps include ancilla Hadamards, shuttling, plunger resets, SWAPs, and shuttling-based Z gates.Source: A. Abstract pulse sequence · pp. 9–10, Table II · p. 11

B. Verification of the shuttling protocol

  • Verification models configurations, plunger resets, and shifts so that electron motion follows barrier activation and changes in relative on-site energies.A shift moves only electrons adjacent to activated barriers whose post-shift on-site energy becomes higher.Source: B. Verification of the shuttling… · pp. 10–11
  • The shuttling protocol is valid when every shift is compatible with its preceding configuration and produces the desired next configuration.The verification algorithm checks these conditions for all intermediate steps as well.Source: B. Verification of the shuttling… · pp. 11–12
  • Testing the 4 × 4 periodic unit cell found all shuttling steps in the protocol compatible and correctly mapped to subsequent configurations.The Python verification code is also described as usable for brute-force searches between arbitrary configurations.Source: B. Verification of the shuttling… · p. 12

C. Physical pulse sequence

The physical pulse sequence maps abstract controls to smooth gate-voltage, barrier, ESR, exchange, and readout operations. The construction implements native single- and two-qubit operations together with spin-to-charge measurement.

C. Physical pulse sequence

  • The physical implementation uses four on-site-energy levels and smooth time-dependent pulses for plunger resets and barrier activation.The barrier pulse interpolates between Off and On states, while the plunger pulse changes one on-site energy level into another.Source: C. Physical pulse sequence · p. 12
  • A shuttling-based Z rotation tunes the target qubit to the neighboring site's energy while activating the separating barrier, then reverses the tuning.The two tuning steps together define the Z-rotation time window.Source: C. Physical pulse sequence · p. 12
  • Hadamard and S gates are decomposed into elementary single-qubit rotations driven by ESR pulses whose frequency matches the relevant Larmor frequency.The ESR pulse is controlled by amplitude, frequency, and phase; X and Y rotations use specified phases and durations.Source: C. Physical pulse sequence · p. 12
  • SWAP gates use an exchange pulse that lowers the separating barrier while keeping the two dots at equal on-site energy.The involved qubits occupy the same column and therefore have the same Zeeman splitting.Source: C. Physical pulse sequence · p. 12
  • Readout uses Pauli-spin blockade: antiparallel spins form a singlet on one site, whereas parallel spins remain separated and are distinguished by charge sensing.The reference qubit is placed in an even column and the measured qubit in a neighboring odd column.Source: C. Physical pulse sequence · pp. 12–13

D. Idle-qubit errors due to limited control

The crossbar’s shared controls induce coherent idle-qubit rotations during shuttling, readout, and off-resonant ESR operations. Including these errors still yields feasible logical-error suppression for parallel and moderate-distance line-by-line operation.

Idle-qubit crosstalk mechanism

  • Idle qubits undergo coherent phase rotations because shared control fields affect qubits not targeted by shuttling, gates, or readout.The protocol avoids opening barriers between neighboring idle qubits, so two-qubit crosstalk errors are absent.Source: D. Idle-qubit errors due to limited… · p. 13

Shuttling-induced rotations

  • The effective model attributes shuttling-induced z rotations to leakage toward a neighboring dot with a different Larmor frequency.The Hamiltonian is block diagonal in spin sectors, and the analysis assumes adiabatic idle-qubit evolution.Source: D. Idle-qubit errors due to limited… · p. 13

ESR-induced errors

  • Off-resonant ESR pulses cause unwanted partial Rabi oscillations, with large-detuning errors scaling as αΩ^2/(ω′)^2 and approximately doubling for a Hadamard gate.For an off-resonant X gate, α = (64 + π2)/384; a Hadamard composed of two rotations has error approximately 2αΩ2/(ω′)2.Source: D. Idle-qubit errors due to limited… · p. 14

Threshold relevance

  • The estimated idle-qubit errors remain below the surface-code per-step threshold pth = 0.57%, supporting continued logical-error suppression.The errors have a spatially periodic coherent structure, but cited work indicates coherent single-qubit rotations do not significantly change the surface-code threshold.Source: D. Idle-qubit errors due to limited… · p. 14

Error estimates

  • 6.4 · 10−4 is the estimated average idle-qubit error for the Z cycle, with 8.5 imperfect idle operations per qubit per full cycle.The idle-operation count is obtained by summing stepwise errors and dividing by the number of qubits in the unit cell.Source: D. Idle-qubit errors due to limited… · p. 14

Logical-error scaling

  • Parallel operation retains exponential logical-error suppression with Λ ≈1.6, while line-by-line operation remains feasible up to dopt = 63 with pL ≈2.3 · 10−5.These refined estimates include idle-qubit errors and use a shorter shuttling-based Z-rotation time.Source: D. Idle-qubit errors due to limited… · p. 14, Figure 12 · p. 14

V. DISCUSSION

The discussion identifies non-uniform hardware as an unmodeled source of error-scaling variation and notes possible real-time correction of crosstalk-induced Z errors.

Scope and limitations

  • The analysis assumes a uniform crossbar, whereas real hardware has imperfections whose effects on logical-error scaling remain to be incorporated.The proposed extension is to include inhomogeneities in the logical-error estimate.Source: §V · pp. 14–15

Decoding and correction

  • Crosstalk-induced Z errors could be corrected with shuttling-based z rotations, which are significantly shorter than semi-global rotations.Real-time correction would require a fast, accurate decoder and feedforward operations.Source: §V · p. 15

VI. CONCLUSIONS

The paper advances physical realization of surface-code circuits in crossbar spin-qubit architectures by connecting abstract routing to physical pulse sequences and below-threshold operation.

Conclusions

  • The work identifies abstract and physical pulse sequences for surface-code error correction and develops a verification algorithm for electron routing.The physical pulse sequence enables refined logical-error estimates and a realistic parameter set for below-threshold operation.Source: §VI · p. 15

Appendix A: Calculation details for the error scaling with line-by-line implementation

The appendices provide operation-count calculations for line-by-line and parallel implementations and estimate idle-qubit rotations and their resulting errors using experimentally relevant parameters.

Appendix A: Calculation details for the error scaling with line-by-line implementation

  • Appendix A tabulates composite time steps for protocol operations and the full stabilizer cycle, with parallel-operation counts obtained by substituting d = 1.The tables also count operations by data and ancilla qubit type for average cycle-error estimates.Source: Appendix A · p. 15, Table IV · p. 16, Table V · p. 16

Appendix B: Estimation of idle qubit errors

  • The appendix derives idle-qubit rotation angles from the effective Hamiltonian for shuttling and PSB readout under time-dependent detuning and tunneling.For readout, activating the barrier closer to the Coulomb-repulsion detuning reduces unwanted rotation angles.Source: Appendix B · pp. 15–17
  • The error estimates use maximal infidelity from the calculated rotation angles, while average infidelity gives a very similar and slightly more optimistic estimate.The appendix relates these estimates to unwanted z rotations affecting idle qubits.Source: Appendix B · p. 17
  • All summarized idle-qubit errors are below the surface-code per-step threshold pth = 0.57%, and lowering the maximum tunnel amplitude could further suppress them.The numerical estimates use the model parameters listed in Table VIII.Source: Appendix B · p. 17

Appendix C: Short guide to Supplementary Material files

The supplementary files provide abstract pulse sequences, shuttling configurations and shifts, visualizations, simulation parameters, and idle-error estimates for the surface-code cycles.

Pulse sequences

  • The Z- and X-cycle spreadsheets contain the abstract gate-voltage and ESR pulse sequences used to implement the surface-code cycles.The Z-cycle sequence is outlined in Table II, while both sequences are described in Sec. IV A.Source: Appendix C · p. 17

Shuttling data

  • Configuration and shift text files encode the Z- and X-cycle shuttling protocols and serve as inputs to the shuttling verification algorithm.The Z-cycle files list configurations and electron movements, while the X-cycle files provide corresponding configurations and shifts.Source: Appendix C · pp. 17–18

Idle-error estimates

  • The Z-cycle idle-error estimates give an average weighted idle error of pidle ≈6.4 · 10−4 and 17 imperfect idle operations per qubit per full cycle.The estimates are approximate upper bounds; ancilla qubits B1 and B2 are unaffected during specified intervals because successive Hadamard gates ideally return them to computational-basis states.Source: Table VII · p. 18

Physical-pulse simulation

  • Simulation parameters are chosen for adiabatic target-qubit transfer, with shuttling, Z, and S† durations numerically optimized for target fidelity.Other parameters are held fixed during these optimizations.Source: Table VIII · p. 18

Visualizations

  • The ZcycleMovie.pdf and XcycleMovie.pdf files visually represent the corresponding abstract pulse sequences.Source: Appendix C · p. 18

Notation

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