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Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit Zuchongzhi 3.0 Processor
Dongxin Gao, Daojin Fan, Chen Zha, Jiahao Bei, Guoqing Cai, Jianbin Cai, Sirui Cao, Xiangdong Zeng, Fusheng Chen, Jiang Chen, Kefu Chen, Xiawei Chen, Xiqing Chen, Zhe Chen, Zhiyuan Chen, Zihua Chen, Wenhao Chu, Hui Deng, Zhibin Deng, Pei Ding, Xun Ding, Zhuzhengqi Ding, Shuai Dong, Yupeng Dong, Bo Fan, Yuanhao Fu, Song Gao, Lei Ge, Ming Gong, Jiacheng Gui, Cheng Guo, Shaojun Guo, Xiaoyang Guo, Tan He, Linyin Hong, Yisen Hu, He-Liang Huang, Yong-Heng Huo, Tao Jiang, Zuokai Jiang, Honghong Jin, Yunxiang Leng, Dayu Li, Dongdong Li, Fangyu Li, Jiaqi Li, Jinjin Li, Junyan Li, Junyun Li, Na Li, Shaowei Li, Wei Li, Yuhuai Li, Yuan Li, Futian Liang, Xuelian Liang, Nanxing Liao, Jin Lin, Weiping Lin, Dailin Liu, Hongxiu Liu, Maliang Liu, Xinyu Liu, Xuemeng Liu, Yancheng Liu, Haoxin Lou, Yuwei Ma, Lingxin Meng, Hao Mou, Kailiang Nan, Binghan Nie, Meijuan Nie, Jie Ning, Le Niu, Wenyi Peng, Haoran Qian, Hao Rong, Tao Rong, Huiyan Shen, Qiong Shen, Hong Su, Feifan Su, Chenyin Sun, Liangchao Sun, Tianzuo Sun, Yingxiu Sun, Yimeng Tan, Jun Tan, Longyue Tang, Wenbing Tu, Cai Wan, Jiafei Wang, Biao Wang, Chang Wang, Chen Wang, Chu Wang, Jian Wang, Liangyuan Wang, Rui Wang, Shengtao Wang, Xinzhe Wang, Zuolin Wei, Jiazhou Wei, Dachao Wu, Gang Wu, Jin Wu, Shengjie Wu, Yulin Wu, Shiyong Xie, Lianjie Xin, Yu Xu, Chun Xue, Kai Yan, Weifeng Yang, Xinpeng Yang, Yang Yang, Yangsen Ye, Zhenping Ye, Chong Ying, Jiale Yu, Qinjing Yu, Wenhu Yu, Shaoyu Zhan, Feifei Zhang, Haibin Zhang, Kaili Zhang, Pan Zhang, Wen Zhang, Yiming Zhang, Yongzhuo Zhang, Lixiang Zhang, Guming Zhao, Peng Zhao, Xianhe Zhao, Xintao Zhao, Youwei Zhao, Zhong Zhao, Luyuan Zheng, Fei Zhou, Liang Zhou, Na Zhou, Naibin Zhou, Shifeng Zhou, Shuang Zhou, Zhengxiao Zhou, Chengjun Zhu, Qingling Zhu, Guihong Zou, Haonan Zou, Qiang Zhang, Chao-Yang Lu, Cheng-Zhi Peng, XiaoBo Zhu, Jian-Wei Pan
TL;DR
Quantum computational advantage requires quantum processors to perform sampling tasks beyond practical classical simulation. This work develops Zuchongzhi 3.0 and evaluates it with large-scale random circuit sampling, establishing a larger benchmark than earlier Google experiments. The 83-qubit, 32-cycle task is completed in a few hundred seconds, while Frontier is estimated to require approximately 6.4 × 10^9 years.
Problem
The work addresses the challenge of extending quantum computational advantage to larger random circuit sampling experiments beyond prior 67- and 70-qubit Google benchmarks.
Method
The authors develop a 105-qubit superconducting processor and evaluate it using patch-circuit verification and large-scale random circuit sampling.
Results
The 83-qubit, 32-cycle experiment produces one million samples in a few hundred seconds, whereas Frontier would require approximately 6.4 × 10^9 years to replicate the task.
Takeaways & Limitations
Zuchongzhi 3.0 establishes a new benchmark in quantum computational advantage by executing a larger random circuit sampling experiment than previously achieved by Google.
Takeaways & Limitations
The Frontier cost estimate assumes a memory cap of 9.2 PB, corresponding to Frontier’s current memory size.
Abstract
from arXiv · showhide
In the relentless pursuit of quantum computational advantage, we present a significant advancement with the development of Zuchongzhi 3.0. This superconducting quantum computer prototype, comprising 105 qubits, achieves high operational fidelities, with single-qubit gates, two-qubit gates, and readout fidelity at 99.90%, 99.62% and 99.18%, respectively. Our experiments with an 83-qubit, 32-cycle random circuit sampling on Zuchongzhi 3.0 highlight its superior performance, achieving one million samples in just a few hundred seconds. This task is estimated to be infeasible on the most powerful classical supercomputers, Frontier, which would require approximately $6.4\times 10^9$ years to replicate the task. This leap in processing power places the classical simulation cost six orders of magnitude beyond Google's SYC-67 and SYC-70 experiments [Nature 634, 328(2024)], firmly establishing a new benchmark in quantum computational advantage. Our work not only advances the frontiers of quantum computing but also lays the groundwork for a new era where quantum processors play an essential role in tackling sophisticated real-world challenges.
INTRODUCTION
Quantum computational advantage is pursued through random circuit sampling designed to challenge classical simulation, with Zuchongzhi competing to extend prior scale records. Zuchongzhi 3.0 advances this effort with 105 qubits and an 83-qubit, 32-cycle experiment that greatly exceeds earlier benchmarks.
- Random circuit sampling applies random quantum gates to create quantum states and then measures them, providing a focal test of quantum computational superiority.
- The 83-qubit, 32-cycle experiment raises the classical simulation cost six orders of magnitude beyond Google’s SYC-67 and SYC-70 experiments.
- Zuchongzhi 3.0 contains 105 qubits and achieves single-qubit gate, two-qubit gate, and readout fidelities of 99.90%, 99.62%, and 99.18%, respectively.
- The processor obtains one million samples from the 83-qubit, 32-cycle circuit in a few hundred seconds.
- Frontier would require approximately 6.4 × 10^9 years to replicate the sampling task.
ZUCHONGZHI 3.0 QUANTUM PROCESSOR
Zuchongzhi 3.0 improves qubit coherence, gate performance, and readout through circuit, hardware, fabrication, and measurement optimizations. These changes support high-fidelity operation across the processor.
- The processor houses 105 Transmon qubits in a 15-by-7 rectangular lattice, with experiments using up to 83 selected qubits.
- Relaxation time reaches 72 µs and dephasing time reaches 58 µs after fabrication and interface improvements.
- Average Pauli errors fall to 0.10% for single-qubit gates and 0.38% for iSWAP-like gates when gates operate simultaneously.
- Readout is accelerated through stronger qubit–resonator coupling and wider resonator linewidths, while bandpass filtering protects qubits from the Purcell effect.
- Three measurement rounds and reset gates reduce thermal-noise effects and suppress average readout error across 83 qubits to 0.82%.
LARGE-SCALE RANDOM CIRCUIT SAMPLING
Zuchongzhi 3.0 applies patterned random quantum circuits to selected 83-qubit subsets, using patch circuits to verify large-scale sampling fidelity. It completes 83-qubit, 32-cycle sampling and estimates the full-circuit fidelity from experimentally verified patch results.
- Circuit construction: The random circuit uses iSWAP-like gates arranged in four patterns and executed in the sequence ABCD-CDAB within each cycle.The selected 83-qubit configuration and pattern layout are illustrated in Fig. 3.
- Verification method: Patch circuits divide the circuit by selectively removing inter-patch two-qubit gates, making large-scale verification more feasible while slightly increasing expected fidelity.The study implements 2-patch, 4-patch, and full circuits and computes linear XEB fidelities.
- Hardware and operating subset: The processor contains 105 qubits and 182 couplers, while the experiment selects 83 qubits for the large-scale sampling task.Gate and readout performance in Fig. 2 is reported for the selected 83 qubits.
- 83-qubit random circuit sampling: 4.1 × 10^8 bitstrings were collected from the largest full 83-qubit, 32-cycle circuit, whose estimated fidelity was 0.025%.The corresponding 4-patch circuit had experimental fidelity 0.030% and estimated fidelity 0.033%.
COMPUTATIONAL COST ESTIMATION
The paper estimates classical simulation costs for its hardest random circuits using tensor-network algorithms under realistic and impractical memory scenarios. Both estimates remain extremely large, with the realistic Frontier scenario requiring billions of years.
- Computational cost: 8.4 × 10^33 floating-point operations are estimated to generate one million uncorrelated bitstrings at 0.025% fidelity from the 83-qubit, 32-cycle circuit.The corresponding SYC-67 estimate is 4.7 × 10^27 operations, making the reported cost six orders of magnitude higher.
- Frontier-based estimate: 6.4 × 10^9 years is the estimated time for Frontier to simulate the most challenging random quantum circuit.The estimate uses the current most powerful supercomputer and corresponds to the paper’s primary memory-constrained scenario.
- Unlimited-memory lower bound: Even with over 762.2 PB of memory, the estimated simulation time remains 5.7 × 10^7 years for the comparable 80-qubit, 32-cycle circuit.This virtually unlimited-memory scenario is described as an unrealistic lower bound for sampling cost.
- Progress comparison: Random-circuit-sampling time complexity is presented as progressing with a doubly-exponential growth pattern across Sycamore and Zuchongzhi experiments.Figure 4 labels the processors as SYC and ZCZ.
CONCLUSION
Zuchongzhi 3.0 combines increased qubit count with improved manipulation precision and executes larger random circuit sampling experiments than previously achieved by Google. The authors present this progress as evidence supporting future quantum applications.
- Zuchongzhi 3.0 combines 105 qubits with improved quantum-manipulation precision, enabling larger random circuit sampling than previously achieved by Google.The paper frames this scaling in both hardware size and operational precision.
- The authors state that scaling qubits and circuit complexity enhances the capacity to address sophisticated challenges in optimization, machine learning, and drug discovery.
- The work is presented as empirical evidence of quantum technology’s potential and as a foundation for practical applications.
Supplemental Material for “Establishing a New Benchmark in Quantum Computational Advantage with 105-qubit
The supplemental material describes Zuchongzhi 3.0’s processor architecture, wiring and control electronics, and calibration procedures. It also documents the hardware and experimental setup supporting the 83-qubit sampling experiment.
- A. Quantum processor: Zuchongzhi 3.0 comprises 105 Transmon qubits and 182 tunable couplers arranged in a 15-by-7 lattice.Each qubit has dedicated control and readout infrastructure, while couplers tune interactions between neighboring qubits.
- B. Control electronics and Cryogenic wiring: The cryogenic system uses modular high-density cables, filters, attenuators, and combined XY/Z control lines to reduce noise and cable count.The refrigerator contains 504 cables, of which 332 were used in the experiment.
- B. Control electronics and Cryogenic wiring: Readout control was upgraded with traveling-wave parametric amplification, optimized circulators, and bandpass filtering to suppress unwanted pump-signal leakage.
- C. Calibration: Basic calibration characterized readout frequencies, flux responses, XY crosstalk, and coherence times before the random circuit sampling experiment.The calibration procedures otherwise followed those used for Zuchongzhi 2.0, with the sampling experiment receiving distinct treatment.
A. Idle Frequency Configuration for 83 qubits
The experiment selected and optimized an 83-qubit subset by accounting for coherence, unwanted couplings, crosstalk, and frequency-dependent defects. Additional calibration procedures addressed single-qubit, readout, and two-qubit-gate performance.
- The 83-qubit subset was selected after evaluating sampling fidelity, circuit complexity, and defects in qubits and couplers.Inactive qubits were frequency-biased and decoupled from active qubits to mitigate unwanted interactions.
- Idle frequencies were optimized using coherence, TLS effects, residual coupling, XY crosstalk, and Z-pulse distortion, with affected qubits retuned when T1 varied.
- Crosstalk cancellation calibrated the compensation amplitude and phase for neighboring qubits, while dynamic coupling-off calibration targeted unintended recoupling during iSWAP-like gates.These procedures were evaluated with error-distribution comparisons with and without the corrections.
- Active reset reduced readout error from 2.21% to 0.93% at a 400 µs sampling interval.The reset procedure used measured qubit states to select subsequent gates.
- The selected 83-qubit subset’s calibration results are presented in Fig. S4 with detailed statistics in the supplement.
C. Fine Calibration for Random Circuit Sampling Experiment
Random circuit sampling circuits differ from XEB calibration circuits, so the experiment calibrates additional effects that influence the actual sampling sequence. The 4-patch method adjusts iSWAP-like-gate parameters toward their experimental values.
- XEB fidelities can deviate from random-circuit performance because the two experiments use different gate sequences and expose different error sources.Idle-gate fidelity, coupler pulse distortion, and state-preparation errors appear in random circuits but are not captured by the XEB circuits.
- Calibration applies the same waveform pattern used in random circuit sampling to align crosstalk, dynamic coupling-off, and residual-coupling effects with experiment conditions.
- Residual Z-pulse crosstalk distorts the applied pulses and creates discrepancies between calibrated and experimentally observed iSWAP-like-gate unitaries.
- The 4-patch calibration method brings iSWAP-like-gate parameters closer to their actual values and aligns experimental fidelities more closely with the sampling experiment.It optimizes parameters starting from values obtained through two-qubit XEB calibration.
2. Idle Gate Benchmarking and Calibration
The experiment benchmarks idle-gate errors under alternating iSWAP-like gate patterns and applies targeted corrections for crosstalk, dynamic coupling-off, residual coupling, and coupler pulse distortion. These calibrations address fidelity mismatches between random-circuit experiments and predictions.
- Idle Gate Benchmarking and Calibration: 45 ns idle gates experience decoherence, Z-crosstalk, dynamic coupling-off, and residual coupling with neighboring qubits across the ABCDCDAB pattern sequence.Because not all 83 qubits participate in every pattern, idle-gate errors must be calibrated separately for each pattern.
- Idle Gate Benchmarking and Calibration: Idle-gate fidelity significantly deviates from SPB estimates because of Z-crosstalk, dynamic coupling-off, and residual neighboring-qubit coupling.The deviation is measured with an RCS-based benchmarking circuit analogous to single-qubit XEB.
- Idle Gate Benchmarking and Calibration: Z-gate compensation corrects qubit-frequency shifts after rescanning dynamic coupling-off and interaction frequencies.The compensation amplitude is selected by scanning for an XBE value below 100 cycles while balancing calibration time and precision.
- Idle Gate Benchmarking and Calibration: Coupler pulse-distortion correction is introduced because alternating shallow circuit patterns make two-qubit gates at different cycles correspond to distinct unitary matrices.The distortion is inferred indirectly from detection-qubit frequency shifts after coupler Z pulses.
4. Calibration of State Preparation Errors
After idle-gate calibration and coupler-distortion correction, a cycle-independent fidelity discrepancy remains and is attributed to state-preparation errors. The experiment calibrates a correction factor using an RCS-specific circuit, after which experimental and predicted fidelities match well.
- Calibration of State Preparation Errors: After idle-gate and coupler-distortion corrections, the remaining cycle-independent fidelity discrepancy is attributed to state-preparation errors.The relevant errors differ from standard readout-fidelity calibration because the 0-2 reset scheme depends on the qubit state before reset.
- Calibration of State Preparation Errors: The RCS-specific calibration circuit estimates a state-preparation correction factor for fidelity calculations.The circuit accounts for the fact that the random-circuit process does not begin from uniformly comparable reset conditions.
- Calibration of State Preparation Errors: After all stated correction methods, experimental and predicted fidelities match well.
III. RANDOM CIRCUIT SAMPLING OF 31-QUBIT 2-PATCH CIRCUIT
The 31-qubit 2-patch experiment scales circuits from 12 to 32 cycles and compares estimated with experimental linear XEB fidelities. Their close correspondence supports the discrete error model when using 4-patch calibration.
- RANDOM CIRCUIT SAMPLING OF 31-QUBIT 2-PATCH CIRCUIT: The 2-patch circuits scale from 12 to 32 cycles with 31 qubits, and linear XEB fidelities are computed for their output bitstrings.
- RANDOM CIRCUIT SAMPLING OF 31-QUBIT 2-PATCH CIRCUIT: Figure S5 compares five iSWAP-like gate parameters before and after 4-patch calibration in the 83-qubit experiment context.The parameter definitions are referred to an earlier reference.
- RANDOM CIRCUIT SAMPLING OF 31-QUBIT 2-PATCH CIRCUIT: Estimated and experimental fidelities closely correspond for both 2-patch and full circuits using 4-patch calibration.The comparison covers 31-qubit 2-patch circuits and the full circuits shown in Fig. S7.
IV. RANDOM CIRCUIT SAMPLING OF 83-QUBIT FULL CIRCUIT
The 83-qubit, 32-cycle full-circuit experiment samples hundreds of millions of bitstrings over an extended run and monitors fidelity stability. RCS-specific error benchmarks track idle-gate and readout errors during the experiment.
- RANDOM CIRCUIT SAMPLING OF 83-QUBIT FULL CIRCUIT: 410 million bitstrings are sampled from the 83-qubit, 32-cycle full circuit over 91 hours.Random sampling experiments are inserted before and after every 10 million bitstrings to monitor stability.
- RANDOM CIRCUIT SAMPLING OF 83-QUBIT FULL CIRCUIT: Figure S6 benchmarks idle-gate and readout errors in RCS circuits, while its CDF plots compare corrected and uncorrected errors across 4-patch and full circuits.The readout comparison covers P0 error in 31-qubit and 83-qubit settings.
- RANDOM CIRCUIT SAMPLING OF 83-QUBIT FULL CIRCUIT: Fidelity variation is monitored with repeated 83-qubit, 4-patch, 32-cycle samples, whose XEB fidelity stays within ±25% of the estimated value.