PaperlayerView exact revision on arXiv

Source-linked AI summary

Demonstrating dynamic surface codes

Alec Eickbusch, Matt McEwen, Volodymyr Sivak, Alexandre Bourassa, Juan Atalaya, Jahan Claes, Dvir Kafri, Craig Gidney, Christopher W. Warren, Jonathan Gross, Alex Opremcak, Nicholas Zobrist, Kevin C. Miao, Gabrielle Roberts, Kevin J. Satzinger, Andreas Bengtsson, Matthew Neeley, William P. Livingston, Alex Greene, Rajeev Acharya, Laleh Aghababaie Beni, Georg Aigeldinger, Ross Alcaraz, Trond I. Andersen, Markus Ansmann, Frank Arute, Kunal Arya, Abraham Asfaw, Ryan Babbush, Brian Ballard, Joseph C. Bardin, Alexander Bilmes, Jenna Bovaird, Dylan Bowers, Leon Brill, Michael Broughton, David A. Browne, Brett Buchea, Bob B. Buckley, Tim Burger, Brian Burkett, Nicholas Bushnell, Anthony Cabrera, Juan Campero, Hung-Shen Chang, Ben Chiaro, Liang-Ying Chih, Agnetta Y. Cleland, Josh Cogan, Roberto Collins, Paul Conner, William Courtney, Alexander L. Crook, Ben Curtin, Sayan Das, Alexander Del Toro Barba, Sean Demura, Laura De Lorenzo, Agustin Di Paolo, Paul Donohoe, Ilya K. Drozdov, Andrew Dunsworth, Aviv Moshe Elbag, Mahmoud Elzouka, Catherine Erickson, Vinicius S. Ferreira, Leslie Flores Burgos, Ebrahim Forati, Austin G. Fowler, Brooks Foxen, Suhas Ganjam, Gonzalo Garcia, Robert Gasca, Élie Genois, William Giang, Dar Gilboa, Raja Gosula, Alejandro Grajales Dau, Dietrich Graumann, Tan Ha, Steve Habegger, Michael C. Hamilton, Monica Hansen, Matthew P. Harrigan, Sean D. Harrington, Stephen Heslin, Paula Heu, Oscar Higgott, Reno Hiltermann, Jeremy Hilton, Hsin-Yuan Huang, Ashley Huff, William J. Huggins, Evan Jeffrey, Zhang Jiang, Xiaoxuan Jin, Cody Jones, Chaitali Joshi, Pavol Juhas, Andreas Kabel, Hui Kang, Amir H. Karamlou, Kostyantyn Kechedzhi, Trupti Khaire, Tanuj Khattar, Mostafa Khezri, Seon Kim, Bryce Kobrin, Alexander N. Korotkov, Fedor Kostritsa, John Mark Kreikebaum, Vladislav D. Kurilovich, David Landhuis, Tiano Lange-Dei, Brandon W. Langley, Kim-Ming Lau, Justin Ledford, Kenny Lee, Brian J. Lester, Loïck Le Guevel, Wing Yan Li, Alexander T. Lill, Aditya Locharla, Erik Lucero, Daniel Lundahl, Aaron Lunt, Sid Madhuk, Ashley Maloney, Salvatore Mandrà, Leigh S. Martin, Orion Martin, Cameron Maxfield, Jarrod R. McClean, Seneca Meeks, Anthony Megrant, Reza Molavi, Sebastian Molina, Shirin Montazeri, Ramis Movassagh, Michael Newman, Anthony Nguyen, Murray Nguyen, Chia-Hung Ni, Logan Oas, Raymond Orosco, Kristoffer Ottosson, Alex Pizzuto, Rebecca Potter, Orion Pritchard, Chris Quintana, Ganesh Ramachandran, Matthew J. Reagor, David M. Rhodes, Eliott Rosenberg, Elizabeth Rossi, Kannan Sankaragomathi, Henry F. Schurkus, Michael J. Shearn, Aaron Shorter, Noah Shutty, Vladimir Shvarts, Spencer Small, W. Clarke Smith, Sofia Springer, George Sterling, Jordan Suchard, Aaron Szasz, Alex Sztein, Douglas Thor, Eifu Tomita, Alfredo Torres, M. Mert Torunbalci, Abeer Vaishnav, Justin Vargas, Sergey Vdovichev, Guifre Vidal, Catherine Vollgraff Heidweiller, Steven Waltman, Jonathan Waltz, Shannon X. Wang, Brayden Ware, Travis Weidel, Theodore White, Kristi Wong, Bryan W. K. Woo, Maddy Woodson, Cheng Xing, Z. Jamie Yao, Ping Yeh, Bicheng Ying, Juhwan Yoo, Noureldin Yosri, Grayson Young, Adam Zalcman, Yaxing Zhang, Ningfeng Zhu, Sergio Boixo, Julian Kelly, Vadim Smelyanskiy, Hartmut Neven, Dave Bacon, Zijun Chen, Paul V. Klimov, Pedram Roushan, Charles Neill, Yu Chen, Alexis Morvan

arXiv:2412.14360v2quant-ph

TL;DR

Quantum error correction needs implementations that can suppress errors despite faulty qubits, but static surface-code layouts impose hardware constraints and can permit non-computational errors to accumulate. This work experimentally tests three time-dynamic surface-code implementations and measures error suppression from distance 3 to distance 5. Each suppresses errors, while their differing error budgets and leakage behavior reveal hardware-design trade-offs.

Abstract

from arXiv · show

A remarkable characteristic of quantum computing is the potential for reliable computation despite faulty qubits. This can be achieved through quantum error correction, which is typically implemented by repeatedly applying static syndrome checks, permitting correction of logical information. Recently, the development of time-dynamic approaches to error correction has uncovered new codes and new code implementations. In this work, we experimentally demonstrate three time-dynamic implementations of the surface code, each offering a unique solution to hardware design challenges and introducing flexibility in surface code realization. First, we embed the surface code on a hexagonal lattice, reducing the necessary couplings per qubit from four to three. Second, we walk a surface code, swapping the role of data and measure qubits each round, achieving error correction with built-in removal of accumulated non-computational errors. Finally, we realize the surface code using iSWAP gates instead of the traditional CNOT, extending the set of viable gates for error correction without additional overhead. We measure the error suppression factor when scaling from distance-3 to distance-5 codes of $\Lambda_{35,\text{hex}} = 2.15(2)$, $\Lambda_{35,\text{walk}} = 1.69(6)$, and $\Lambda_{35,\text{iSWAP}} = 1.56(2)$, achieving state-of-the-art error suppression for each. With detailed error budgeting, we explore their performance trade-offs and implications for hardware design. This work demonstrates that dynamic circuit approaches satisfy the demands for fault-tolerance and opens new alternative avenues for scalable hardware design.

HEXAGONAL LATTICE SURFACE CODE

The paper experimentally demonstrates three time-dynamic surface-code implementations, each addressing different hardware or error-management constraints. All suppress errors from distance 3 to distance 5, while their error budgets and leakage behavior expose distinct design trade-offs.

SCALING AND OUTLOOK

HEXAGONAL LATTICE SURFACE CODE

  • The hexagonal implementation uses 20% fewer couplers than the standard implementation while matching its error suppression factor, 2.15(2) versus 2.14(2).A distance-5 hexagonal circuit used 49 computational qubits and 64 couplers, compared with 80 couplers in the standard implementation.Source: HEXAGONAL LATTICE SURFACE CODE · p. 3

WALKING SURFACE CODE

  • The walking circuit alternates each qubit between data and measurement roles, providing reset opportunities every two cycles that limit leakage buildup.The distance-5 walking circuit used 58 qubits and achieved Λ35,walk = 1.69(6) without explicit leakage removal beyond multi-level reset.Source: WALKING SURFACE CODE · pp. 3–4

ISWAP SURFACE CODE

  • The iSWAP implementation preserves surface-code structure through complementary, time-reversed stabilizer distortions and achieves Λ35,iSWAP = 1.56(2).It relies on multi-level reset rather than DQLR; iSWAP also transports leakage toward measure qubits, where reset is applied.Source: ISWAP SURFACE CODE · pp. 5–6

SCALING AND OUTLOOK

  • The error budgets identify two-qubit gates, dynamical decoupling, and readout as larger contributors than leakage and crosstalk across implementations.The iSWAP c-phase accounts for 16% of its simulated inverse-scaling-factor budget and makes its simulated 1/Λ35 larger than the other implementations.Source: SCALING AND OUTLOOK · p. 6
  • Tailoring hardware to a hexagonal layout is predicted to improve Λ by 15% while reducing coupler count and control-line demands.The simulations account for realistic hardware inhomogeneities and TLS density.Source: SCALING AND OUTLOOK · p. 7
  • The experiments support dynamic circuits as a viable fault-tolerant approach and show opportunities to co-design error correction and hardware.The reported budgeting and leakage results illuminate trade-offs in realizing quantum error correction.Source: SCALING AND OUTLOOK · p. 7

Appendix A: Statistical analysis of QEC experiments

Appendix A describes how detection events and logical outcomes are sampled and analyzed, then connects stochastic Pauli errors to detector probabilities, covariances, and error budgets. Its linear budget groups error channels and estimates their first-order contributions.

1. Detector probability

  • Repeated memory experiments average detector events and logical observables across repetitions and randomized initial data states, then pass them to a decoder for correction.The dataset contains detector bits and a final logical-observable bit.Source: §1 · p. 13
  • A detector fires when an odd number of stochastic Pauli errors that anticommute with its detecting region occur; their probabilities combine by probabilistic XOR.The first-order approximation treats the combined probability as a linear sum when error probabilities are small.Source: §1 · pp. 13–14

2. Detector probability sampling noise

  • Detector-probability uncertainty is estimated from binomial sampling variance, with shot noise expressed as the standard deviation of detector outcomes.The variance scales with the number of samples.Source: §2 · p. 14

3. Covariance of two detectors

  • Detector covariance serves as a proxy for shared error channels, providing more localized information about circuit errors than individual detector probabilities.The joint-trigger probability includes an XOR over channels that trigger both detectors.Source: §3 · p. 14

a. Linear error budget

  • The linear error budget partitions anticommuting errors into non-overlapping channel groups and estimates each group’s first-order contribution to detector probability.Subtracting near the operating point cancels many nonlinear terms; the remaining nonlinear contribution is the model expectation minus the sum of linear contributions.Source: §4 · p. 15, a. Linear error budget · p. 15

b. Exact error budget

The appendix presents an exact detector error budget alongside device benchmarking and simulation procedures. It describes how measured operation errors and modeled mechanisms inform budgets for the dynamic surface-code experiments.

b. Exact error budget

  • The exact budget disentangles error-set contributions and removes nonlinear cross terms; its contributions sum to zero as a consistency check.The authors use the linear budget in main-text figures for readability and verify that the exact-budget sum rule holds for all detector budgets in the work.Source: b. Exact error budget · pp. 15–16

5. Experimental benchmarking and error model construction

  • Device benchmarking measures single-qubit gates with randomized benchmarking, two-qubit gates with cross-entropy benchmarking, and reset and measurement errors in parallel circuit-matched layers.The measured errors are translated into Pauli-model rates for detector budgeting and verification.Source: §5 · p. 16

1. Simulation details

  • The error model includes decoherence, readout and reset errors, leakage, crosstalk, and excess depolarizing errors; iSWAP simulations additionally model unwanted controlled-phase error as a Pauli ZZ error.The iSWAP controlled-phase is measured in parallel with the circuit’s two-qubit gate layers.Source: §1 · p. 18
  • The error-budget sensitivity for each channel is obtained by uniformly increasing its component error probabilities in simulations and fitting the resulting change in 1/Λ35.The analysis uses each channel’s measured operating-point error probabilities.Source: §1 · p. 18

2. Error budget for hexagonal lattice surface code

The hexagonal-code error budget attributes most of the modeled 1/Λ35 contribution to CZ-related errors, followed by data-qubit idle errors. The simulation comparison also indicates that some experimental error mechanisms are not included in the models.

2. Error budget for hexagonal lattice surface code

  • 46% of the hexagonal-code 1/Λ35 budget comes from CZ-related errors, versus 23% from data-qubit idle errors, 17% from readout/reset, and 13% from single-qubit errors.The calculation assumes 95% DQLR fidelity for leakage to |2> and 15% for leakage to |3>.Source: §2 · pp. 18–19
  • The measured Λ35 value was 2.14, obtained using sparse blossom and harmony decoders, indicating that the experiment has additional error mechanisms not included in the simulations.Source: §2 · p. 19

3. Error budget for walking surface code

The walking-code error budget assigns a 7% contribution to leakage, comparable to the hexagonal and conventional codes. Its linear prediction exceeds the measured error-suppression factor, indicating an unaccounted error source.

3. Error budget for walking surface code

  • Leakage contributes 7% to Λ^-1_35 in the walking code, similar to 6% for the hexagonal and conventional surface codes.The authors interpret this similarity as evidence that the walking code successfully removes leakage.Source: §3 · p. 19
  • Λ_linear35 = 2.27 exceeds the measured Λ_expt,harmony35 = 1.67, pointing to a significant unmodeled error source.The passage identifies the measured value as given in the main text.Source: §3 · p. 19
  • The walking-code budget is calculated with a linear approximation using the operating-point data in Table B.3.The prediction is notably higher than the experiment, suggesting that the budget misses a significant error source.Source: §3 · p. 19

4. Error budget for iSWAP surface code

The iSWAP error budget finds small leakage contributions but identifies parasitic c-phase error as a substantial source. Its linear prediction exceeds the measured scaling factor, with the authors suspecting uncaptured error mechanisms, including leakage propagation.

4. Error budget for iSWAP surface code

  • iSWAP leakage contributes roughly 1% to Λ^-1_35, versus 5% for hexagonal and 6% for walking codes.The simulations omit DQLR as in the experiment; without DQLR, leakage heating is more detrimental and leakage lifetime is roughly four QEC cycles.Source: §4 · p. 19
  • Parasitic c-phase error contributes a Pauli error of 1.5 × 10^-3 per iSWAP gate and accounts for 16% of the simulated total budget.The simulations include this error alongside the usual sources.Source: §4 · p. 19
  • Λ_linear35 = 1.77 exceeds the measured Λ_expt,harmony35 = 1.54, indicating error mechanisms are not fully captured by the model.The authors suspect some missing mechanisms relate to complex leakage propagation without periodic leakage removal such as DQLR.Source: §4 · p. 19

Appendix C: Hexagonal circuit implementation of the surface code

The appendix describes a hexagonal surface-code implementation whose moving detecting regions permit reduced connectivity. Its circuit alternates expansion and contraction and accommodates a distinct boundary structure.

1. Circuit construction and detail

  • The hexagonal circuit reuses the first entangling layer as its last layer with inverted CNOT orientation, enabling hexagonal connectivity.In experiments, CZ gates and inserted single-qubit rotations implement the circuit presented in CNOT form.Source: §1 · p. 21
  • Each bulk detecting region touches 22 CNOTs, as in the standard code, but spans six qubits rather than nine.The region expands and contracts, and its measurements move across different qubits; its contraction cycle is the time inverse of expansion.Source: §1 · p. 21, Figure C.2 · p. 21
  • At the reset slice, a north-west boundary stabilizer spans two measure qubits, changing the code edge and its noise sensitivity.The full detector slices depict Pauli terms by vertex color and include reset/DQLR and dynamical-decoupling actions.Source: §1 · p. 21, Figure C.3 · p. 22

2. Component Benchmarks

The component benchmarks characterize gate, readout, dynamical-decoupling, reset, and leakage-removal errors for the hexagonal implementation. The supplied benchmark descriptions specify the measured quantities and, for coherence, report T1 and T2 statistics.

2. Component Benchmarks

  • T1 has mean and median 76 µs, while T2 has mean 80 µs and median 87 µs.The reported standard deviations are 12 µs for T1 and 22 µs for T2.Source: Figure C.4 · p. 23
  • Gate benchmarks report single-qubit Pauli error and two-qubit XEB Pauli error, with inferred CZ error subtracting single-qubit error from total XEB error.The cumulative histogram summarizes Pauli error rates across the chip.Source: Figure C.5 · p. 23
  • Readout, dynamical-decoupling, and reset/DQLR benchmarks summarize mid-cycle versus final readout, measurement/reset decay, residual reset error, and data-qubit excess depolarization.Their figures also show cumulative histograms of the corresponding measured error rates.Source: Figure C.6 · p. 24, Figure C.7 · p. 24, Figure C.8 · p. 24

3. Detection analysis

The section tests whether benchmark-derived Pauli models reproduce measured detection statistics for the hexagonal implementation. It finds that the model captures detection probabilities for embedded distance-3 codes and agrees well with measured detector covariances.

3. Detection analysis

  • Boundary weight-2 and bulk weight-4 detectors show clearly separated detection fractions, which are compared with simulations.Averages use 20 initial bitstrings and 10,000 repetitions per experiment.Source: §3 · p. 25, Figure C.9 · p. 26
  • The benchmark-derived Pauli model captures detection probabilities for embedded distance-3 codes, although benchmarks were taken in the distance-5 memory context.The analysis focuses on the distance-5 hexagonal circuit over 54 cycles.Source: §3 · p. 25
  • Measured detector covariances for decoding-graph edges agree very well with the benchmark-derived Pauli model.The analysis reports two-point covariance for space-like, time-like, and spacetime-like edges.Source: §3 · p. 25, Figure C.10 · p. 27

Appendix D: Walking circuit implementation of the surface code

The walking implementation uses alternating, space-inverted cycles to reset all qubits, including boundaries, and analyzes component benchmarks and detection events. Its benchmark-derived Pauli model captures distance-3 detection probabilities, but agrees less closely with measurements than models for the hexagonal and iSWAP implementations.

1. Circuit construction and detail

  • Space-inverting alternate cycles make every other cycle spatially symmetric, allowing all qubits, including boundaries, to be reset each cycle and leakage errors to be eliminated.A time-reversal alternative does not reset every boundary qubit and can allow leakage to accumulate.Source: §1 · p. 28, Figure D.11 · p. 29

2. Component benchmarks

  • The low-fidelity multi-level reset at qubit (7, 8) was replaced with a higher-fidelity single-level reset for the |1⟩ state.The authors describe the implementation's high performance after this change as an indication of walking's leakage benefits.Source: §2 · p. 28, Figure D.16 · p. 31
  • Walking-grid coherence benchmarks report a T1 mean of 67 µs and a T2 mean of 88 µs.The reported medians are 70 µs for T1 and 94 µs for T2.Source: Figure D.12 · p. 30

3. Detection analysis

  • The walking Pauli model captures distance-3 detection probabilities despite distance-5 benchmarking, but agrees less closely with measurements than the hexagonal and iSWAP models.Detection analysis focuses on distance-3 and distance-5 circuits with 54 cycles.Source: §3 · p. 32

Appendix E: iSWAP circuit implementation of the surface code

The iSWAP implementation uses time-reversal to refocus spread-out detecting regions and balances an unwanted c-phase with virtual Z rotations. Its benchmark-derived Pauli model captures distance-3 detection probabilities; the appendix also details its gate and reset benchmarks.

1. Circuit construction and detail

  • Time-reversal in the second cycle refocuses the iSWAP circuit's more spread-out detecting regions.The code boundary required trial and error to produce a functioning circuit.Source: §1 · p. 35, Figure E.19 · p. 35

2. Experimental implementation details

  • Virtual Z rotations balance the unwanted c-phase from the 01-10 interaction, which introduces a new error channel for codes requiring strict Cliffords.The implemented gate uses γ = −φ/2.Source: §2 · pp. 35–36

3. Component Benchmarks

  • The iSWAP-grid coherence benchmarks report a T1 mean of 80 µs and a T2 mean of 68 µs.The reported medians are 81 µs for T1 and 27 µs for T2.Source: Figure E.20 · p. 37

4. Detection analysis

  • The benchmark-derived iSWAP Pauli model captures detection probabilities for embedded distance-3 codes, using benchmarks taken in the distance-5 memory context.The analysis focuses on distance-3 and distance-5 circuits with 54 cycles.Source: §4 · pp. 36–37

3. Component Benchmarks

  • The iSWAP benchmarking includes c-phase measurements and an inferred iSWAP XEB Pauli error calculated by adding φ^2/16 to the inferred Sycamore-gate Pauli error.The c-phase is measured using MEADD.Source: Figure E.22 · p. 38
  • The iSWAP reset benchmark used fewer statistics, so unmeasured zero-error qubits were assigned the median reset error in simulations.The authors report that this substitution makes little difference, as reset is a small contributor to the 1/Λ budget.Source: Figure E.24 · p. 39

Appendix F: Decoding results

The decoding appendix compares decoder algorithms and prior-setting methods, and identifies Harmony with a reinforcement-learning-optimized prior as the combination used for the best logical performance reported in the main text.

Appendix F: Decoding results

  • The main text quotes error-suppression factors for Harmony with a reinforcement-learning-optimized decoder prior because that combination achieves the best logical performance.The appendix lists decoding results for the hexagonal, walking, and iSWAP implementations.Source: Appendix F · p. 42, Table F.9 · p. 42, Table F.10 · p. 42
  • The decoding comparison uses sparse blossom and Harmony, with priors from either the SI1000 error model or reinforcement learning.The learned prior is trained separately by code distance, patch location, and basis, then extrapolated to datasets up to 56 cycles under a time-invariance assumption.Source: Appendix F · p. 42

Appendix G: Simulation of the gate frequency optimization

The appendix simulates gate-frequency optimization for standard and hexagonal surface-code circuits to test whether removing one coupler relaxes frequency-selection constraints. In the simulations, the hexagonal circuit has a higher error suppression factor than the standard circuit.

Simulation setup

  • The simulation used 20 Bayesian-network-generated fake processors per distance, then created matched hexagonal counterparts by removing one coupler per qubit and scaling its coupling by 10−3.This kept each hexagonal processor otherwise identical to its square-connectivity twin.Source: Appendix G · pp. 42–43
  • Circuit-aware Snake optimization used 20 initial seeds per processor and selected the frequency configuration with the lowest expected QEC detection rate for each circuit.The optimization used local scope 3 with no additional healing.Source: Appendix G · p. 43

Gate-error results

  • Three neighbors reduced spurious frequency collisions, allowing frequencies to cluster near the tuning-range maximum and reducing flux-noise dephasing; stray-interaction contributions also fell by nearly the 4/3 neighbor-count ratio.Some other error contributions remained similar between circuits.Source: Appendix G · p. 43
  • Hexagonal connectivity suppressed mean single-qubit gate errors by 3.4% and two-qubit gate errors by 21.0%; twice-per-cycle CZ gates improved by 30.0%, versus 10.5% for once-per-cycle CZ gates.The optimization did not account for readout errors; the simulation instead used a uniform readout error probability of 8 × 10−3.Source: Appendix G · p. 43, Figure G.27 · p. 45

Detection rates

  • Bulk average detection rates rose with code distance for both circuits and appeared to saturate at a lower level for hexagonal connectivity; whether better optimization can mitigate the distance trend remains open.The averaging excluded boundary detectors, so boundary dilution does not explain the increase.Source: Appendix G · pp. 43–44

Results

  • Λ was 1.55 ± 0.03 for standard and 1.80 ± 0.02 for hexagonal circuits, equivalent to 16% improved scaling for hexagonal connectivity.The estimates fit mean logical error rate against code distance using the typical scaling law.Source: Appendix G · p. 44, Figure G.27 · p. 45

Coupling sweep

  • Reducing the removed-coupler interaction to the stray-diagonal-coupling level was sufficient for the simulated Λ improvement, though fits through distance 7 gave higher estimates than fits through distance 15.The standard-circuit estimate was 1.68 through distance 7 and 1.55 through distance 15.Source: Appendix G · p. 44, Figure G.27 · p. 45
Loading 2412.14360v2…