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Bias-preserving and error-detectable entangling operations in a superconducting dual-rail system

Nitish Mehta, James D. Teoh, Taewan Noh, Ankur Agrawal, Amos Anderson, Beau Birdsall, Avadh Brahmbhatt, Winfred Byrd, Marc Cacioppo, Anthony Cabrera, Leo Carroll, Jonathan Chen, Tzu-Chiao Chien, Richard Chamberlain, Jacob C. Curtis, Doreen Danso, Sanjana Renganatha Desigan, Francesco D'Acounto, Bassel Heiba Elfeky, S. M. Farzaneh, Chase Foley, Benjamin Gudlewski, Hannah Hastings, Robert Johnson, Nishaad Khedkar, Trevor Keen, Anup Kumar, Cihan Kurter, Kamila Krawczuk, Eric Langstengel, Richard D. Li, Gangqiang Liu, Hanyi Lu, Pinlei Lu, Luke Mastalli-Kelly, Adam Maines, Michael Maxwell, Heather McCarrick, Mona Mirzaei, Anirudh Narla, Omar Rashad, Erik Reikes, Mizanur Rahman, Rurik Primiani, Michael Schwaller, Ali Sabbah, Tali Shemma, Ruby A. Shi, Sitakanta Satapathy, Dean Stolpe, Jonathan Strenczewilk, Doug Szperka, Iu-Wei Sze, David Sweeney, Preetham Tikkireddi, Chin-Lun Tsung, Daren Vet Sam, Daniel K. Weiss, Zhibo Yang, Liuqi Yu, Teng Zhang, Olivier Boireau, Stephen Horton, Sean Weinberg, Jose Aumentado, Bryan Cord, Chan U Lei, Joseph O. Yuan, Shantanu O. Mundhada, Kevin S. Chou, S. Harvey Moseleley, Jr., Robert J. Schoelkopf

arXiv:2503.10935v2quant-ph

TL;DR

Dual-rail cavity qubits offer a favorable idle error hierarchy, but lacked an entangling operation that preserves it. This work experimentally demonstrates an excitation-preserving CZ gate whose dominant errors remain detectable erasures, with low residual errors and asymmetric target/control rates.

  • Problem

    Dual-rail cavity qubits have a favorable idle error hierarchy, but an entangling operation that preserves it was an important missing ingredient.

    Source: §I · p. 1
  • Method

    The authors experimentally demonstrate an excitation-preserving controlled-Z SWS gate that swaps the control photon into a coupler, accumulates an entangling phase, then swaps it back.

    Source: §I · pp. 1–2, §II · p. 3
  • Results

    Postselected fidelity is 99.97-99.90%; dominant errors remain erasures (~0.5%), and target erasure and dephasing rates are 3-4 times lower than control rates.

    Source: §I · p. 2, §III · p. 7
  • Takeaways & Limitations

    The gate completes the dual-rail cavity qubit’s universal-operation gate set; estimating QEC performance with both error types still requires detailed numerical simulations.

    Source: §III · p. 7

Abstract

from arXiv · show

For useful quantum computation, error-corrected machines are required that can dramatically reduce the inevitable errors experienced by physical qubits. While significant progress has been made in approaching and exceeding the surface-code threshold in superconducting platforms, large gains in the logical error rate with increasing system size remain out of reach. This is due both to the large number of required physical qubits and the need to operate far below threshold. Importantly, by exploiting the biases and structure of the physical errors, this threshold can be raised. Erasure qubits achieve this by detecting certain errors at the hardware level. Dual-rail qubits encoded in superconducting cavities are a promising erasure qubit wherein the dominant error, photon loss, can be detected and converted to an erasure. In these approaches, the complete set of operations, including two qubit gates, must be high performance and preserve as much of the desirable hierarchy or bias in the errors as possible. Here, we design and realize a novel two-qubit gate for dual-rail erasure qubits based on superconducting microwave cavities. The gate is high-speed ($\sim$500 ns duration), and yields a residual gate infidelity after error detection below 0.1%. Moreover, we experimentally demonstrate that this gate largely preserves the favorable error structure of idling dual-rail qubits, making it ideal for error correction. We measure low erasure rates of $\sim$0.5% per gate, as well as low and asymmetric dephasing errors that occur at least three times more frequently on control qubits compared to target qubits. Bit-flip errors are practically nonexistent, bounded at the few parts per million level. This error asymmetry has not been well explored but is extremely useful in quantum error correction and flag-qubit contexts, where it can create a faster path to effective error-corrected systems.

I. INTRODUCTION

Dual-rail cavity qubits make photon loss detectable while idling errors favor erasures over dephasing and strongly suppress bit flips; this work introduces an entangling gate designed to preserve that hierarchy.

I. INTRODUCTION

  • Bias-aware encodings can raise surface-code gate-error thresholds from 1% to more than 5%, while erasures can be corrected more readily than Pauli errors.The cited surface-code erasure threshold is almost 25% per round, and a given code distance can correct twice as many erasures as Pauli errors.Source: §I · p. 1
  • Dual-rail cavity qubits have an idle-error hierarchy dominated by erasures, with dephasing 5–10 times lower and bit flips several orders of magnitude rarer.Source: §I · p. 1
  • An entangling gate that preserves this favorable hierarchy was a missing ingredient for superconducting dual-rail cavity qubits.Source: §I · p. 1
  • The SWAP-Wait-SWAP gate temporarily swaps a control-cavity excitation into a transmon coupler, uses its dispersive shift with the target, then swaps the excitation back for a roughly 500 ns CZ.Source: §I · p. 2
  • Below 1% erasure, 0.1% or lower post-detection dephasing, and fewer than a few parts per million bit flips accompany the gate; target erasure and dephasing rates are 3–4 times lower.The asymmetry is between target and control qubits.Source: §I · p. 2

II. RESULTS

The SWAP-Wait-SWAP (SWS) gate temporarily stores the control excitation in a coupler so its dispersive interaction with the target produces a CZ phase. Benchmarking and error characterization show low residual errors, strong control-target asymmetry, and benign propagation of vacuum leakage.

Gate construction

  • The SWS gate swaps the control excitation into a coupler, accumulates a dispersive phase with the target, then swaps the excitation back.The gate takes about 500 ns and preserves total excitation number, keeping both dual-rails in the single-excitation manifold with the coupler included in the control rail during the gate.Source: §II · pp. 2–3, Figure 1 · p. 2

Gate benchmarking

  • 0.53(2)% total erasure probability per CZ gate is extracted from the repeated-gate postselected fraction.A separate interleaved-RB estimate reports a 0.69% erasure probability per gate, which limits usable sequence depth to a few hundred gates.Source: §II · p. 4
  • 0.1% error per CZ gate is estimated by interleaved randomized benchmarking, in reasonable agreement with repeated Bell-state tomography.The tomography estimate is 0.03% postselected infidelity per gate through 15 repeats; at larger depths, fidelity and purity decrease quadratically, possibly due to calibration drift or coupler-frequency fluctuations.Source: §II · p. 4, Figure 2 · p. 4

Error structure

  • 0.400(4)% control and 0.096(4)% target erasures per CZ gate yield an erasure asymmetry of about four.The measured asymmetry is consistent with the relative T1 of the coupler and the target cavities.Source: §II · pp. 4–5
  • 0.039(1)% control and 0.0112(9)% target Z errors per gate give a dephasing ratio of about 3.5.The proposed model attributes control dephasing to coupler Tϕ during the swap and target dephasing to dual-rail Tϕ while idling.Source: §II · pp. 4–5
  • Bit-flip errors are bounded at a few parts per million per gate, while leakage to vacuum either leaves the target near identity or induces correlated target dephasing.For control preparations |00⟩ and |10⟩, the target process remains close to identity; loss from |01⟩ during the gate instead gives an incomplete, randomly timed CPHASE and a dephasing-like target channel.Source: §II · pp. 5–6

III. DISCUSSION AND CONCLUSION

The SWS gate provides a fast entangling operation while preserving the dual-rail qubit’s favorable error hierarchy. Its errors remain mainly detectable erasures, and the gate has simple leakage behavior.

  • Leakage before the CZ interaction switches the gate off, while leakage during it can produce either an identity process or a CZ error.The conditioned target process is close to identity for control preparations |00⟩ and |10⟩, and resembles a CZ error for |01⟩.Source: Figure 4 · p. 7
  • The excitation-preserving SWS gate retains erasure-dominated errors, sub-microsecond timing, and strong suppression of bit flips.The dominant errors are erasures at approximately 0.5%, while bit flips are bounded below a few parts per million per gate.Source: §III · pp. 6–7
  • The added entangling operation completes the universal gate set for dual-rail cavity qubits.The paper states this can enable high-performance short-depth circuits and new error-mitigation approaches.Source: §III · p. 7
  • Erasure and dephasing rates are each reported at tenfold below their separate surface-code thresholds, though combined-error performance requires detailed numerical simulation.The authors describe the results as a realistic route to gains of 10 or more with increasing code distance.Source: §III · p. 7

VIII. COMPETING INTERESTS STATEMENT

The statement reports a financial interest involving R.J.S. and Quantum Circuits, Inc.

  • R.J.S. is a founder and shareholder of Quantum Circuits, Inc., and QCI-affiliated authors have a financial interest in the company.Source: §VIII · p. 8

Supplemental information for “Bias-preserving and error-detectable entangling

The excerpt identifies itself as supplemental information for the paper.

1. 1Q gate characterization

This section characterizes the single-qubit gates and dual-rail SPAM, then describes calibration of the SWS two-qubit gate.

1. 1Q gate characterization

  • Single-qubit gates use parametric beamsplitter interactions, and randomized benchmarking samples 20 sequences per Clifford length.The benchmarking gateset generates the 24 single-qubit Cliffords.Source: §1 · p. 11
  • Individual gate fidelity exceeds 99.98%; simultaneous operation decreases control and target fidelities by 0.001% and 0.002%, respectively.Source: §1 · p. 11, Figure 5 · p. 11

2. SPAM

  • Repeated dual-rail measurements can exponentially suppress misassignments, at the cost of a first-order decrease in postselected fraction.The measurement detects photon loss and can flag errors arising during measurement.Source: §2 · pp. 11–12
  • SPAM misassignment is 0.023% for target and 0.020% for control; SPAM erasure is 6.79% for target and 6.43% for control.These are the reported logical misassignment and overall SPAM erasure errors.Source: §2 · p. 12

Appendix B: Two-qubit gate calibration

  • Swap amplitude is optimized for g_ac/κϕ, then pulse duration is set by minimizing cavity population after odd-numbered swaps.The calibration also selects the swap-back phase that minimizes erasure for the |01g10⟩ initial state.Source: Appendix B · p. 13
  • The wait time is calibrated for entangling phase π, while Ramsey-like sequences measure the accumulated local Z phases.The swap-back phase is recalibrated as delay time changes.Source: Appendix B · p. 13

Appendix C: CZ gate on-off ratio

These appendices quantify the CZ gate’s interaction strength, explain fidelity estimation with postselection, and analyze leakage propagation and process-tomography results.

Appendix C: CZ gate on-off ratio

  • χbc/2π is ∼1.51 MHz, χab/2π is ∼6.64 kHz, and the resulting CZ-gate on-off ratio is ∼230.The two interactions are inferred from target-cavity spectroscopy and Ramsey measurements, respectively.Source: Appendix C · pp. 13–14, Figure 7 · p. 15

Appendix D: Inferring gate fidelities

  • The short-depth interleaved-RB analysis extracts the depolarizing parameter from a linear fit to survival-probability decay, with the estimate depending on fit amplitude and offset.The gate-error estimate is based on interleaved and reference RB slopes.Source: Appendix D · pp. 14–15

Appendix E: Evaluating the accuracy of IRB with postselection

  • The postselected-fidelity model includes leakage and dephasing channels and renormalizes each input-state fidelity contribution by its postselected fraction.The model accounts for leakage-detection misassignments and compares simulated IRB with the modeled postselected fidelity.Source: Appendix E · pp. 15–16
  • IRB systematically underestimates infidelity in the simulations, by 25% at the measured value, changing it from 0.1% to 0.13%.The underestimate persists with perfect simulated leakage detection and varies with the random gate sequence.Source: Figure 8 · p. 15, Appendix E · p. 16

1. Leakage before a CZ gate

  • Leakage before the gate leaves the other qubit unchanged because the coupler-target interaction is not activated with only one excitation between the qubits.The leakage-propagation analysis considers leakage before and during the CZ gate.Source: Appendix F · p. 16, §1 · p. 17

2. Leakage during a CZ gate

  • Leakage during the gate is modeled as a random partial entangling phase followed by leakage; after stabilizer measurement, preserving correlated error terms avoids bad hook errors.The effective channel corresponds to a 50-50 mixture of leakage before and after the gate.Source: §2 · p. 17

3. Analysis of experimental results

  • The process-tomography analysis uses the χ-error matrix to quantify deviations from a reference process, with the ideal error process having only χI,I = 1 nonzero.The error process is represented in the Pauli basis.Source: §3 · p. 18

Appendix G: No-jump backaction in the SWS gate

The appendix analyzes no-jump backaction in the SWS gate and describes a measurement of residual coupler excitation after repeated gates.

Appendix G: No-jump backaction in the SWS gate

  • A single mid-sequence X pulse on the control cancels no-jump polarization, while interleaved rotations and measurements keep its effective error below 10^-5.No-jump backaction acts like a gradual Z-basis measurement favoring the less lossy |10⟩ state.Source: Appendix G · pp. 18–19

Appendix H: CZ induced coupler heating

  • Unpostselected measurements find residual coupler population rising by 0.014% per CZ gate, whereas postselection on the control codespace finds no measurable increase after 64 gates.The excitation-preserving gate makes residual coupler excitation detectable through the control qubit’s vacuum outcome.Source: Appendix H · p. 19

Appendix I: Correlated leakage and coupler excitation in the SWS gate

The appendix analyzes correlated leakage and coupler excitation arising during the SWS gate.

Appendix I: Correlated leakage and coupler excitation in the SWS gate

  • Target-photon loss midway through an SWS gate can leave both qubits in vacuum and an excitation in the coupler, producing a correlated double erasure.The mechanism is most pertinent when gac ∼ χbc, where the control photon may not fully swap into or back from the coupler.Source: Appendix I · p. 19
  • The predicted double-erasure probability is 1.3 × 10^-5 per gate, while coupler dephasing is predicted to leak to detectable states with probability 6.5 × 10^-5 per gate.Both effects are suppressed quadratically with |χbc|/gac; the predicted total probability of ending with an excited coupler is 8.0 × 10^-5 per gate.Source: Appendix I · p. 20

Appendix J: Measuring bit-flip errors

The appendix reports additional measurements of bit-flip rates for varied initial logical states and compares their trends with idling rates.

Appendix J: Measuring bit-flip errors

  • With the exception of the state that swaps an excitation into the coupler, measured bit-flip rates are indistinguishable from idling rates.The extracted rates may be apparent rates because finite leakage-discrimination fidelity combines with increasing erasures over time.Source: Appendix J · p. 20, Figure 10 · p. 20

Appendix K: Derivation of gate parameters

The appendix derives SWS pulse parameters for a CZ-equivalent dual-rail operation, then explains how the wait and SWAP phases accumulate. Its analytic derivation assumes square, instantaneous pulses; experimental values require calibration because real pulses have finite ramps and additional Hamiltonian terms.

Appendix K: Derivation of gate parameters

  • The derived parameters make the gate locally equivalent to CZ on the dual-rail subspace, up to local Z rotations, under square, instantaneous-pulse assumptions.In the experiment, finite pulse ramps and terms such as cavity-cavity cross-Kerr make the calibrated values differ from theory.Source: Appendix K · pp. 20–21
  • Fixing tSWAP = π/gac leaves twait and the second-SWAP phase ϕ as the parameters to derive and calibrate.For a given hardware parameter set, multiple pulse-parameter sets can enact CZ; this choice makes the experimental sweep involve a delay and a phase.Source: Appendix K · pp. 20–21

1. Deriving twait

  • The wait time follows by summing the entangling phase from the wait and both SWAP segments, with the total phase set to π for CZ.The wait contributes ϕwait = χtwait; each SWAP segment also contributes phase because the detuned-Rabi trajectory is only partially completed.Source: §1 · p. 21

2. Deriving ϕSWAP

  • The second-SWAP phase is derived geometrically from the XY-plane trajectory, relating ϕ3 to ϕSWAP and using ϕ1 + 2ϕ2 + ϕ3 = 2π.The trajectory angles are illustrated in Fig. 11.Source: §2 · pp. 21–22, Figure 11 · p. 22

Appendix L: QuTiP Master equation simulations and CZ gate error budget

The appendix uses QuTiP master-equation simulations to model the SWS gate and its error budget. The simulations verify the derived gate parameters and show how dual-rail basis states evolve through the operation.

Appendix L: QuTiP Master equation simulations and CZ gate error budget

  • The simulations evolve all five modes under the three piecewise Hamiltonians, including measured-coherence collapse operators, white-noise dephasing, and excitation loss.They also capture no-jump backaction, expected Z-frame updates, and correlated errors.Source: Appendix L · p. 22
  • The derived gate-parameter expressions are exact, and the simulated |0L1L⟩ state returns to its initial population with an entangling phase of π and a deterministic control Z-phase.The |1L0L⟩ and |1L1L⟩ states undergo identity evolution in the simulation; Fig. 12 depicts the basis-state trajectories.Source: Figure 12 · p. 22, Appendix L · p. 23
  • The simulated error budget estimates probabilities for CZ error channels that are too small to measure directly, using measured hardware coherence times.The comparison uses the longer echo times as dephasing times; Table V gives the estimated single-gate budget and compares it with short-sequence measurements.Source: Appendix L · p. 23, Table V · p. 23

Appendix M: Fundamental limits to SWS gate performance

The appendix estimates fundamental SWS gate limits under a hypothetical model in which coupler decoherence accounts for cavity decoherence. It reports a potentially large advantage for target-qubit Z errors over the transmon decoherence limit, with the bias bounded by hardware hybridization.

Appendix M: Fundamental limits to SWS gate performance

  • The limit analysis assumes only the coupler has intrinsic loss and dephasing, with cavity modes otherwise taken to have infinite T1 and Tϕ.In this scenario, dispersively coupled cavities inherit coupler loss and dephasing through the inverse Purcell effect.Source: Appendix M · p. 23
  • The estimated SWS error limits use gate duration τ = π/|χbc| and assume white-noise dephasing with hybridization G typically between 0.01 and 0.05.The analysis also assumes G is approximately equal to Ga and Gb and omits order-unity prefactors.Source: Appendix M · pp. 23–24
  • Target-qubit Z errors may be several orders of magnitude below the transmon decoherence limit, while the maximum bias is set by 1/G^2.The passage describes this regime as promising for flag-qubit or stabilizer-measurement circuits.Source: Appendix M · p. 24
  • Reducing extrinsic cavity dephasing, including dephasing inherited from ancilla transmons, is expected to further improve target-qubit Z errors.The analysis identifies these errors as a potential improvement target rather than a fixed limit.Source: Appendix M · p. 24
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