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CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie

arXiv:2505.02168v1cs.AR

TL;DR

AI-assisted IC design methods are often task-specific or focus on circuit structure, despite circuits carrying complementary functional information across modalities. CircuitFusion learns general representations by combining hardware code, structural graphs, and functionality summaries with circuit-specific strategies, and it consistently achieves state-of-the-art performance across five design-quality tasks while enabling zero-shot inference.

  • Problem

    Many AI-assisted IC design methods are task-specific or focus on graph structure, overlooking other circuit modalities with functional information.

    Source: §1 · p. 1

  • Method

    CircuitFusion combines HDL code, structural graphs, and functionality summaries in a general circuit encoder, with circuit-specific preprocessing, pre-training, and retrieval-augmented inference strategies.

    Source: §1 · p. 2

  • Results

    Across five design-quality prediction tasks, CircuitFusion consistently achieves state-of-the-art performance after fine-tuning and enables zero-shot inference.

    Source: §5 · p. 10

  • Takeaways & Limitations

    CircuitFusion’s representations support multiple circuit-design tasks, and retrieving similar known circuits enables zero-shot inference.

    Source: §1 · p. 2

    The training data remains limited compared with what the authors consider ideal for a robust circuit foundation model.

    Source: §5 · p. 10

Abstract

from arXiv · show

The rapid advancements of AI rely on the support of ICs. However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent years, AI-assisted IC design methods have demonstrated great potential, but most methods are task-specific or focus solely on the circuit structure in graph format, overlooking other circuit modalities with rich functional information. In this paper, we introduce CircuitFusion, the first multimodal and implementation-aware circuit encoder. It encodes circuits into general representations that support different downstream circuit design tasks. To learn from circuits, we propose to fuse three circuit modalities: hardware code, structural graph, and functionality summary. More importantly, we identify four unique properties of circuits: parallel execution, functional equivalent transformation, multiple design stages, and circuit reusability. Based on these properties, we propose new strategies for both the development and application of CircuitFusion: 1) During circuit preprocessing, utilizing the parallel nature of circuits, we split each circuit into multiple sub-circuits based on sequential-element boundaries, each sub-circuit in three modalities. 2) During CircuitFusion pre-training, we introduce three self-supervised tasks that utilize equivalent transformations both within and across modalities. 3) When applying CircuitFusion to downstream tasks, we propose a new retrieval-augmented inference method, which retrieves similar known circuits as a reference for predictions. It improves fine-tuning performance and even enables zero-shot inference. Evaluated on five different circuit design tasks, CircuitFusion consistently outperforms the SOTA supervised method specifically developed for every single task, demonstrating its generalizability and ability to learn circuits' inherent properties.

1 INTRODUCTION

CircuitFusion targets general circuit representations because existing AI-assisted design methods are largely task-specific and often overlook circuit modalities beyond structure. It combines multimodal encoding with circuit-specific strategies for preprocessing, pre-training, and downstream inference.

1 INTRODUCTION

  • CircuitFusion separately encodes HDL code, structural graphs, and functionality summaries, then fuses them through cross-attention.An auxiliary netlist encoder adds downstream implementation information.Source: §1 · p. 2
  • Parallel circuit execution motivates splitting circuits into sub-circuits at sequential-element boundaries for scalable learning.The circuit is represented in three modalities for each sub-circuit.Source: §1 · p. 2
  • Equivalent circuit transformations support pre-training tasks that jointly capture structural and semantic representations within and across modalities.The tasks include masked graph modeling, masked summary modeling, and functional contrastive learning.Source: §1 · p. 2
  • Retrieval-augmented inference uses similar known circuits as references to calibrate predictions, improving fine-tuning results and enabling zero-shot inference.Circuit reusability motivates retrieving similar circuits for new designs.Source: §1 · p. 2
  • Across varied tasks, CircuitFusion consistently outperforms state-of-the-art task-specific models.Figure 1 previews the effects of removing modalities and proposed strategies.Source: §1 · p. 3
  • Using a single modality or removing a proposed strategy increases prediction error, as previewed in Figure 1.The introduction reports these ablation effects without giving numerical values.Source: §1 · p. 3, Figure 1 · p. 3

2 RELATED WORKS

Prior circuit representation methods largely use graphs and often target late-stage netlist verification, while CircuitFusion targets early RTL-stage representations. Multimodal software encoders offer a related approach, but the paper identifies differences in circuit mechanisms and input length.

2 RELATED WORKS

  • Prior hardware representation work focuses on graph-format circuits, often for netlist functional verification at a late design stage.CircuitFusion instead targets early RTL-stage representations, where designers have more flexibility for design-quality optimization.Source: §2 · p. 3
  • Software encoders commonly combine summary and code modalities, with some also using syntactic graphs, but their mechanisms differ from hardware circuits.The paper notes that circuit-specific properties do not apply to software code.Source: §2 · p. 3
  • Most existing software encoders are validated on snippets within 1024 tokens, shorter than HDL for a simple circuit.Source: §2 · p. 3

3 PROPOSED METHOD: CIRCUITFUSION

CircuitFusion preprocesses circuits into register-aligned multimodal subcircuits, encodes code, graph, and summaries with a fusion architecture, and trains using within- and across-modality plus netlist-stage objectives. For downstream tasks, retrieval uses similar known circuits as references for fine-tuning or zero-shot prediction.

3.1 PREPROCESSING: MULTIMODAL AND MULTI-STAGE CIRCUIT DATA

  • Register-based subcircuits backtrace each register’s combinational inputs and align RTL and netlist representations across code, graph, and functionality-summary modalities.Each subcircuit captures a register’s single-clock-cycle state transition, including timing paths and logic computations.Source: §3.1 · p. 4

3.2 CIRCUITFUSION MODEL ARCHITECTURE

  • Three unimodal encoders represent graph, summary, and code; a summary-centric cross-attention encoder fuses them, while an auxiliary netlist encoder is used during pretraining.Graph and code embeddings are mixed as keys and values, with summary tokens as queries; the netlist encoder is discarded at inference.Source: §3.2 · pp. 4–5

3.3 PRE-TRAINING WITHIN CIRCUITFUSION: MULTIMODAL FUSION

  • Within CircuitFusion pretraining, masked graph modeling, functionally equivalent contrastive samples, cross-modal alignment, and summary–mixup objectives train structural and semantic representations.Masked summary modeling predicts hidden summary tokens from fusion embeddings, while summary–mixup matching distinguishes matched from unmatched pairs.Source: §3.3 · pp. 5–6

3.4 PRE-TRAINING BEYOND CIRCUITFUSION: IMPLEMENTATION-AWARE ALIGNMENT

  • Implementation-aware contrastive learning aligns whole-subcircuit RTL and netlist embeddings in a shared latent space.The auxiliary netlist encoder is pretrained with masked graph modeling and graph contrastive objectives to capture netlist structure.Source: §3.4 · pp. 6–7

3.5 APPLICATION: RETRIEVAL-AUGMENTED INFERENCE FOR DOWNSTREAM TASKS

  • Retrieval-augmented inference indexes known-circuit embeddings and retrieves top-k similar subcircuits by cosine similarity for downstream prediction.Retrieved quality metrics can be combined with target embeddings during fine-tuning or used directly for zero-shot inference.Source: §3.5 · p. 7

4 EXPERIMENTS

Experiments show that CircuitFusion performs strongly across five design-quality prediction tasks, supports zero-shot prediction through similar-circuit retrieval, and improves as model and pretraining data sizes increase.

4 EXPERIMENTS

  • CircuitFusion’s dataset contains 41 RTL designs and 7,166 aligned RTL–netlist sub-circuit pairs; sub-circuits are approximately 1000× smaller than full circuits in nodes and code tokens.The smaller units support scalable, fine-grained representation learning.Source: §4 · pp. 7–8, Table 1 · p. 8

4.1 VISUALIZATION OF CIRCUIT MULTIMODAL FUSION

  • Figure 5 visualizes cross-attention between functionality summaries and code or graph elements, highlighting relevant signal names and operations for signal and conditional-logic examples.Grad-CAM highlights the code tokens and graph nodes with the highest cross-attention scores.Source: §4.1 · p. 8, Figure 5 · p. 8

4.2 DESIGN QUALITY PREDICTION TASKS AND BASELINE METHODS

  • The five RTL-stage prediction tasks cover register slack, WNS, TNS, total power, and total area; comparisons include hardware-specific models, text encoders, and software-code encoders.Evaluation uses correlation coefficient and MAPE; register slack is evaluated at sub-circuit level, while the other tasks are evaluated on whole designs.Source: §4.2 · pp. 8–9

4.3 SUPERVISED FINE-TUNING FOR DESIGN QUALITY TASKS

  • CircuitFusion consistently outperforms hardware, text, and software-code baselines across all five design-quality tasks, with MAPE improvements of 5% for slack, WNS, and area, 10% for TNS, and 13% for power.The authors also describe it as a flexible foundation that can be fine-tuned across tasks without significant task-specific adjustments.Source: Table 2 · p. 9, §4.3 · p. 9

4.4 ZERO-SHOT RETRIEVAL AND REGRESSION

  • At top-1 retrieval, CircuitFusion achieves the lowest MAPE across all tasks, enabling zero-shot circuit-quality prediction; the authors set the retrieval number to 1 to minimize error.The authors report that its embeddings can identify functionally similar circuits, unlike general text and software-code encoders.Source: §4.4 · p. 10, Table 3 · p. 10

4.5 DOWNSTREAM PERFORMANCE SCALING WITH MODEL SIZE AND DATA SIZE

  • 19% to 12% error accompanies scaling from 270M to 500M parameters; increasing pretraining data from 25% to 100% (7k RTL sub-circuits) reduces error from around 24% to 12%.Figure 6 reports average performance across all five fine-tuned design-quality prediction tasks.Source: §4.5 · p. 10, Figure 6 · p. 10

5 CONCLUSION AND FUTURE WORK

CircuitFusion combines multimodal circuit encoding with strategies informed by circuit properties, and achieves state-of-the-art fine-tuned performance across five design-quality tasks while enabling zero-shot inference.

5 CONCLUSION AND FUTURE WORK

  • Across five design-quality prediction tasks, CircuitFusion achieves state-of-the-art fine-tuned performance and enables zero-shot inference.The authors identify limited training data, relative to what would be ideal for a robust circuit foundation model, as a limitation.Source: §5 · p. 10

REPRODUCIBILITY STATEMENT

The statement points readers to materials intended to support replication of the reported results.

REPRODUCIBILITY STATEMENT

  • The paper identifies its datasets as open-source benchmarks and directs readers to appendices for dataset summaries and preprocessing details.The preprocessing information covers circuit modalities, sub-circuit generation, and downstream-task label collection.Source: REPRODUCIBILITY STATEMENT · p. 11
  • The publicly available source repository includes step-by-step scripts for replicating the paper’s primary results.The statement also points readers to the repository for implementation materials.Source: REPRODUCIBILITY STATEMENT · p. 11

A MORE ON CIRCUIT HDL DATASET

The appendix describes four circuit datasets spanning logic-synthesis benchmarks, open-source designs, CPU cores, and system-on-chip designs.

A.0.1 ITC’99

  • ITC’99 is a widely used circuit benchmark suite primarily designed for logic synthesis and verification.Its designs range from simple combinational logic to more complex sequential circuits.Source: §A.0.1 · p. 15

A.0.2 OPENCORES

  • OpenCores offers open-source hardware designs spanning systems such as CPUs, memory controllers, and communication protocols.The collection ranges from small, simple circuits to large, complex designs.Source: §A.0.2 · p. 15

A.0.3 VEXRISCV

  • VexRiscv is an open-source, RISC-V-compliant CPU core designed using SpinalHDL, with configurable pipeline stages, instruction sets, and optimizations.The dataset supports evaluation on CPU-level design tasks.Source: §A.0.3 · p. 15

A.0.4 CHIPYARD

  • Chipyard is a framework for RISC-V-based system-on-chip designs, including CPU cores, accelerators, memory systems, and I/O components.Its dataset supports testing at the SoC level across varied circuit complexities and design objectives.Source: §A.0.4 · p. 15

B MORE ON CIRCUIT DATA PREPROCESSING

The preprocessing pipeline prepares circuit data at sub-circuit granularity and represents it through code, graph, and functionality-summary modalities. It also generates synthesis-based quality labels and includes an auxiliary netlist encoder.

B.1 DATASET AND FINE-TUNING LABEL COLLECTION

  • Fine-tuning labels are post-synthesis PPA metrics measured after RTL designs are synthesized with Design Compiler using the NanGate 45nm library.PrimeTime provides register slack and circuit-level WNS, TNS, power, and area.Source: §B.1 · p. 15

B.2 MULTIMODAL AND MULTI-STAGE CIRCUIT: A CASE STUDY

B.2.1 HDL CODE

  • HDL snippets preserve each sub-circuit’s functional description, with clock-triggered always blocks defining sequential-register behavior.Inputs and outputs specify primary signals, while wires and assign statements express internal connections and combinational logic.Source: §B.2.1 · p. 16

B.2.2 STRUCTURAL GRAPH

  • The RTL structural graph is built from an abstract syntax tree, with registers and combinational operators as nodes and HDL wires as edges.The graph construction follows a process similar to Fang et al. (2023).Source: §B.2.2 · p. 16

B.2.3 FUNCTIONALITY SUMMARY

  • GPT-4o generates functionality and implementation summaries from HDL, with single-register, single-cycle sub-circuits simplifying the summarization task.Source: §B.2.3 · p. 17

B.2.4 NETLIST GRAPH

  • The auxiliary netlist graph treats flip-flops and logic gates as nodes and connecting wires as edges.Source: §B.2.4 · p. 17

B.3 SUB-CIRCUIT GENERATION ALGORITHM

  • For each register, breadth-first search traces connected combinational logic to related input or output registers, producing aligned HDL snippets and graph subgraphs.The search is parallelized within each design to reduce runtime.Source: §B.3 · p. 17

C.1 MODEL HYPERPARAMETERS

  • The RTL graph encoder uses a 7-layer Graphormer, code uses frozen NV-Embed-V1, summaries use BERTbase, and fusion uses cross-attention.The auxiliary netlist encoder uses a 3-layer GraphSAGE because graph transformers struggle with large, bit-blasted netlist graphs.Source: §C.1 · pp. 17–18

C.2 SELF-SUPERVISED PRE-TRAINING TASKS IMPLEMENTATION

The implementation combines graph reconstruction and contrastive objectives for pre-training, alongside an auxiliary netlist encoder. Downstream inference retrieves similar circuits, and lightweight task models operate on the shared pre-trained representation.

C.2 SELF-SUPERVISED PRE-TRAINING TASKS IMPLEMENTATION

  • Masked graph modeling randomly masks 30% of RTL and netlist graph nodes and reconstructs their one-hot node types using an MSE-trained MLP.Source: §C.2 · p. 18
  • InfoNCE supports all contrastive schemes, with intra-modal weight 1.0, cross-modal and implementation-aware weights 0.2, and temperature 0.3.The temperature controls the sharpness of similarity scores for circuit embeddings and their positive and negative samples.Source: §C.2 · p. 18
  • Multimodal fusion pre-training includes masked summary modeling and mixup embedding-summary matching.Source: §C.2 · p. 18

C.3 NETLIST ENCODER IMPLEMENTATION

  • The netlist encoder uses masked graph modeling and graph contrastive learning, with positive samples created through Boolean-equivalent transformations.It reconstructs gate-level nodes because flattened netlists contain limited semantics compared with RTL.Source: §C.3 · p. 18

C.4 TRAINING HYPERPARAMETERS

  • Four self-supervised tasks train simultaneously for 50 epochs; the frozen pre-trained model is adapted with lightweight models, with XGBoost performing best among those explored.XGBoost handles concatenated sub-circuit embeddings and design-level features as tabular data.Source: §C.4 · p. 19
  • Pre-training takes about 10 hours on four Nvidia A4000 GPUs, while fine-tuning takes about five minutes per task.The authors contrast this fine-tuning runtime with task-specific baselines that require time-consuming feature engineering or model changes.Source: §C.4 · p. 19

C.5 RETRIEVAL-BASED INFERENCE IMPLEMENTATION

  • At sub-circuit level, retrieved functionally similar circuits’ quality metrics are concatenated with the embedding before regression predicts sub-circuit quality.Source: §C.5 · p. 19
  • Circuit-level inference combines each sub-circuit embedding and retrieved metrics with design-level features before regression predicts circuit quality.Baseline comparisons use the same pre-trained CircuitFusion model and fine-tune different downstream models for each task.Source: §C.5 · p. 19, §C.6 · p. 19

D EXPERIMENTAL SETTINGS

CircuitFusion is evaluated in zero-shot and few-shot settings across five design-quality prediction tasks. The reported comparisons show reasonable zero-shot predictions without training data and consistent baseline outperformance as training data increases.

D EXPERIMENTAL SETTINGS

  • The experiments were conducted on a server with four NVIDIA A4000 GPUs, a 2.9 GHz Intel Xeon Platinum 8375C CPU, and 512 GB RAM.Source: D EXPERIMENTAL SETTINGS · p. 19

E.1 BASELINE MODELS (EXTENDED)

E.2 ZERO-SHOT AND FEW-SHOT INFERENCE (EXTENDED)

  • Across five design-quality prediction tasks, CircuitFusion is evaluated from zero-shot to full-shot data fractions, with MAPE as the reported metric.The extended results are shown in Tables 5–9.Source: §E.2 · p. 20, Table 5 · p. 20, Table 6 · p. 20
  • CircuitFusion produces reasonable predictions without training data, while the baselines provide no zero-shot predictions.Source: §E.2 · p. 20
  • From 1/8 to full-shot, CircuitFusion consistently outperforms baselines across tasks and has lower MAPE in nearly all cases.Source: §E.2 · p. 20

E.3 ABLATION STUDY

Ablations, transfer tests, and fusion variants examine CircuitFusion’s strategies and modalities. The results also discuss prospective uses in agile chip design and RTL generation.

E.3 ABLATION STUDY

  • Removing sub-circuit generation causes the largest error increases across tasks, while removing any pre-training objective or retrieval raises MAPE.Sub-circuit splitting is especially relevant to slack prediction, which requires sub-circuit-level embeddings; retrieval uses functionally similar circuits as references.Source: §E.3 · p. 21, Figure 9 · p. 21
  • Removing hardware code or graph raises prediction error across tasks, and the graph contributes more; the study also assesses summary removal.The graph’s structural information and code’s circuit details support the authors’ case for modality fusion.Source: §E.3 · p. 21, Figure 10 · p. 22

E.4 APPLYING PROPOSED STRATEGIES TO BASELINE ENCODERS

  • Applying sub-circuit generation and retrieval to other pre-trained encoders improves performance across tasks and enables fine-grained slack prediction.Table 10 reports the evaluation of these strategies on other encoders.Source: §E.4 · p. 22, Table 10 · p. 22
  • With sub-circuit generation and retrieval, NV-Embed-v1 MAPE falls from 26% to 17% for WNS, 55% to 27% for TNS, 44% to 20% for power, and 24% to 17% for area.CircuitFusion still outperforms all baselines.Source: §E.4 · p. 22

E.5 DISCUSSION ON DIFFERENT MULTIMODAL FUSION IMPLEMENTATIONS

  • CircuitFusion’s summary-centric fusion outperforms modality-centric, partial-fusion, alignment, and single-modality variants across all metrics.The strategy first mixes graph and code embeddings, then combines them with summary embeddings; Table 11 summarizes the variants.Source: §E.5 · p. 22, Table 11 · p. 23

F APPLING CIRCUITFUSION FOR MORE AGILE CHIP DESIGN PROCESSES

  • Predictions are proposed as inputs to early timing optimization, and combining CircuitFusion embeddings with code-generation decoders is presented as future research.The paper says the predictions can support the optimization method in [4].Source: F APPLING CIRCUITFUSION FOR MORE AGILE… · p. 23

G APPLING CIRCUITFUSION FOR MULTI-CLOCK CIRCUIT DESIGNS.

CircuitFusion predicts timing within individual clock groups after fine-tuning with group-specific labels. Its accuracy is similar to that in single-clock scenarios, but asynchronous clock-domain crossings remain outside its scope.

G APPLING CIRCUITFUSION FOR MULTI-CLOCK CIRCUIT DESIGNS.

  • For multi-clock designs, timing predictions can be made within individual clock groups by fine-tuning with timing labels specific to each group.The sub-circuit strategy backtraces logic to driving registers, capturing state transitions and timing paths within each register cone.Source: G APPLING CIRCUITFUSION FOR… · p. 23
  • CircuitFusion achieves timing prediction accuracy similar to single-clock scenarios on a design combining circuits from separate timing groups.The combined design is synthesized before predictions are made within each timing group.Source: G APPLING CIRCUITFUSION FOR… · p. 23
  • Signal transfers across asynchronous clock domains remain beyond the method's scope and are identified as future work.Source: G APPLING CIRCUITFUSION FOR… · p. 23
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