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Tour de gross: A modular quantum computer based on bivariate bicycle codes

Theodore J. Yoder, Eddie Schoute, Patrick Rall, Emily Pritchett, Jay M. Gambetta, Andrew W. Cross, Malcolm Carroll, Michael E. Beverland

arXiv:2506.03094v1quant-ph

TL;DR

The paper addresses how to realize scalable, efficient fault-tolerant quantum computing without the unfavorable physical-to-logical qubit ratio of surface-code architectures. It proposes a modular bicycle architecture using bivariate bicycle codes, explicit logical instructions, and adapted compilation. Resource estimates show that roughly an order of magnitude more logical qubits can be supported with comparable physical resources, although compilation increases runtime and the architecture remains a foundational baseline requiring further advances.

  • Problem

    Surface-code architectures have an unfavorable physical-to-logical qubit ratio, motivating architectures that preserve fault tolerance while improving efficiency.

  • Method

    The paper builds a modular architecture from gross and two-gross bivariate bicycle-code modules, LPUs, T factories, long-range connections, universal instructions, and an adapted compilation strategy.

  • Results

    Approximately an order of magnitude more logical qubits can be executed with the same physical resources as conventional surface-code architectures.

  • Takeaways & Limitations

    The bicycle architecture supports significantly larger logical circuits within fixed physical-qubit budgets, though compilation into bicycle instructions increases runtime.

  • Takeaways & Limitations

    The architecture is presented as a foundational baseline expected to evolve, and its implementation requires challenging long-range physical couplers.

Abstract

from arXiv · show

We present the bicycle architecture, a modular quantum computing framework based on high-rate, low-overhead quantum LDPC codes identified in prior work. For two specific bivariate bicycle codes with distances 12 and 18, we construct explicit fault-tolerant logical instruction sets and estimate the logical error rate of the instructions under circuit noise. We develop a compilation strategy adapted to the constraints of the bicycle architecture, enabling large-scale universal quantum circuit execution. Integrating these components, we perform end-to-end resource estimates demonstrating that an order of magnitude larger logical circuits can be implemented with a given number of physical qubits on the bicycle architecture than on surface code architectures. We anticipate further improvements through advances in code constructions, circuit designs, and compilation techniques.

1 Introduction

The bicycle architecture combines modular long-range-connected hardware with bivariate bicycle quantum LDPC codes to pursue scalable fault-tolerant quantum computing. Its resource estimates indicate roughly an order-of-magnitude advantage in logical circuit capacity over surface-code architectures, while retaining a universal, modular execution model.

  • 1 Introduction: Long-range connectivity enables modular hardware and supports low-overhead quantum LDPC codes that are impractical with short-range connections alone.Modules can be optimized, interconnected, or replaced, while long-range couplers support the code constructions used here.
  • 1 Introduction: Approximately an order of magnitude more logical qubits can be executed with the same physical resources as conventional surface-code architectures.The comparison covers physical qubit counts of 5k, 50k, and 500k and physical error rates of 10^-3 and 10^-4, with similar logical T-gate counts.
  • 1.1 Fault-tolerant architecture criteria: The bicycle architecture targets scalable fault tolerance through fault-tolerant, addressable, universal, adaptive, modular, and efficient operation criteria.These criteria cover logical error suppression, qubit access, universal instructions, real-time measurement response, replaceable modules, and practical resource use.
  • 1.1 Fault-tolerant architecture criteria: The architecture uses gross and two-gross bivariate bicycle codes, each encoding 12 logical qubits; two-gross improves error suppression but requires twice as many physical qubits.Logical addressing uses auxiliary logical processing units, while T factories and generalized lattice surgery provide universal and inter-module operations.
  • 1.2 The bicycle architecture: The bicycle architecture comprises connected code and T factory modules, with long-range entangling components supporting different module connectivities and a defined instruction set.Its instructions include shift automorphisms, in-module and inter-module measurements, and T injection; each code module stores 12 logical qubits.

Appendix A.2. Any element of the group of 36 automorphism unitaries, A :=

The bicycle instruction set combines in-module and inter-module Pauli measurements, T injection, and code automorphism operations. The paper specifies these instructions and models their durations and logical failure probabilities under circuit noise.

  • Appendix A.2. Any element of the group of 36 automorphism unitaries, A :=: The instruction set includes 15 in-module measurement instructions and 36 inter-module measurement instructions for connected code modules.The inter-module operations measure Pauli products acting nontrivially on logical qubits in different connected modules.
  • Appendix A.2. Any element of the group of 36 automorphism unitaries, A :=: Six T-injection instructions prepare a factory T state, perform a code-factory measurement, and destructively measure the factory.The six cases target X, Y, or Z on logical qubit 1 or 7.
  • Appendix A.2. Any element of the group of 36 automorphism unitaries, A :=: The bicycle codes support fault-tolerant preparation of all logical qubits in |0⟩^12 or |+⟩^12 and destructive all-qubit readout in either the X or Z basis.The analysis assumes these CSS preparation and measurement operations add no time or noise.
  • Appendix A.2. Any element of the group of 36 automorphism unitaries, A :=: Table 2 characterizes each instruction by duration τ_i and logical error rate P_i under physical circuit noise with error rate p.Execution failure is defined as any logical error, with independent logical errors and bootstrap-based Monte Carlo error bars.

2 Fault-tolerant implementation of the bicycle architecture

The paper gives explicit fault-tolerant constructions for two bivariate bicycle codes, covering in-module and inter-module measurements, and evaluates their error suppression. It also identifies architectural limitations and future improvements involving connectivity, realistic noise, inter-module operations, and low-error-rate extrapolations.

  • Overview: The implementation targets the [[144, 12, 12]] gross code and [[288, 12, 18]] two-gross code with concrete surgery-based fault-tolerant components.The constructions include a smaller surgery scheme for the gross code and a new construction for the two-gross code.
  • In-module measurements: In-module logical measurements use quantum LDPC surgery, deforming the code so the target Pauli becomes a stabilizer product for C syndrome cycles.The LPU supplies the ancillary qubits and connectivity needed to switch among measurements on selected logical qubits.
  • In-module measurements: The LPU and shift automorphisms can implement the full Clifford group on 11 of the 12 logical qubits in a module.The construction uses logical measurements enabled by the LPU together with code shifts.
  • Inter-module measurements: 36 inter-module Pauli products are fault-tolerantly measurable, while bridges of size d −1 retain phenomenological requirements of 6 errors for gross and 9 for two-gross.The adapter's deformed code distance is d −1 rather than the full code distance d, but the stated minimum decoder-failure error count remains unchanged.
  • Performance analysis: The two-gross idle instruction is extrapolated at about 10^-20 logical error rate for p = 0.001, versus about 10^-10 for a rotated d = 17 surface code.The authors caution against interpreting this extrapolation in isolation.
  • Future directions: Future work prioritizes higher-distance schedules, realistic nonuniform noise simulations, improved inter-module operations, and validation of the two-gross low-error-rate extrapolation.The authors specifically note limiting inter-module logical error rates and uncertainty about how accurately the very low two-gross extrapolation reflects performance.

3 Compiling to the bicycle architecture

The paper compiles universal quantum circuits into measurement-based bicycle instructions by distributing Pauli operations across connected code modules. The scheme uses pivot ancillas, inter-module measurements, in-module operations, and GHZ states while supporting arbitrary-angle rotations without additional global entanglement overhead.

  • Architecture adaptation: The compilation strategy targets linear connectivity and can be adapted to any module connectivity with minor adaptations.Its stated goal is to balance simplicity and efficiency while providing a starting point for later optimizations.
  • Input and preprocessing: The compiler accepts Clifford+P(φ) circuits initialized in |0^n⟩ with final computational-basis measurements and translates them into Pauli-generated rotations and measurements.The compilation pipeline first removes Clifford gates and rewrites the circuit into Pauli-based computation form.
  • Module distribution: Pauli-generated rotations and measurements are distributed across M = ⌈n/11⌉ modules, each containing 11 data qubits and one pivot ancilla.The pivot supports inter-module coordination and in-module operations.
  • Module distribution: Controlled-P operations are decomposed using pivot ancillas, GHZ-state preparation, adjacent-module ZZ measurements, and controlled-P_i unitaries within modules.Factoring P into module-local components enables the original global operations to be reduced to bicycle measurements plus in-module operations.
  • Native instruction sets: Both gross and two-gross codes support 540 native measurements and 510 native rotations, with native rotations generating the Clifford group.Each code encodes 12 logical qubits, although their parameter A differs.
  • Entanglement and rotations: Connected modules can prepare the required GHZ states by measuring along a spanning tree, while Hamiltonian-path architectures need only two rounds of inter-module measurements.Arbitrary-angle rotations require no additional global entanglement overhead, allowing faster T-state consumption and reducing noise from idling.
  • Open challenges: The general compilation scheme may limit parallelism because removing Clifford gates can produce large-support Pauli-generated rotations that entangle the entire architecture.This is identified as an opportunity for improving compilation efficiency.

4 End-to-end resource estimates

The paper extends resource estimation to the modular bicycle architecture, evaluating random circuits and transverse-field Ising simulation under circuit-noise constraints. Across these examples, bicycle architectures require substantially fewer physical qubits than comparable surface-code architectures, while having longer runtime per T and demanding compilation overhead.

  • Estimation workflow: The resource-estimation workflow compiles Pauli-generated-rotation circuits into bicycle instructions, optimizes repeated in-module measurements, and estimates failure probability from instruction counts, logical error rates, and durations.Idle instructions account for module waiting time, rounded to integer idle operations.
  • Random circuits: The capability study fixes physical qubits and physical error rate, then finds the largest random circuit whose failure probability is at most 1/3.The study considers physical noise rates from p = 10^-3 to p = 10^-4 and systems up to q = 500k.
  • Runtime trade-offs: The bicycle architecture has longer runtime per T than the surface code, with compilation overhead identified as its main limitation.Increasing LPU size and improving synthesis are proposed ways to reduce this overhead; surface-code runtime is mainly limited by one T factory’s distillation rate.
  • TFIM simulation: q = 4817 physical qubits suffice for TFIM simulation with gross codes and one 10^-4 gross factory, compared with 17 010 for a d = 9 surface code.The gross-code estimate requires p ≤ 2.1 × 10^-5, while the d = 9 surface code requires p ≤ 5.4 × 10^-5.
  • TFIM simulation: q = 8138 physical qubits suffice for TFIM simulation with two-gross codes at p ≤ 7.3 × 10^-4, compared with 58 263 at d = 17 or 72 663 at d = 19 for surface codes.The two-gross estimate uses 1.9 × 10^7 T injections and requires T-injection logical error around 10^-10.
  • Resource comparison: The bicycle architecture provides about an order of magnitude more logical data qubits than surface-code architectures at fixed T count.The authors expect further research to increase logical T-count and qubit capabilities, while algorithmic improvements reduce required capabilities.

5 Conclusions and opportunities

The paper presents the bicycle architecture as a modular, fault-tolerant platform based on bivariate bicycle codes, with custom instructions and compilation for universal execution. Its resource estimates support larger logical circuits at fixed physical-qubit budgets, while fabrication and connectivity remain important engineering constraints.

  • Architecture: The bicycle architecture combines quantum LDPC codes, selective Pauli measurements, T injection, real-time decoding, feedforward, modular code blocks, and lower qubit overhead.The architecture is described as satisfying six criteria for a scalable fault-tolerant architecture.
  • Instructions and compilation: Custom instructions exploit bivariate bicycle codes through shift automorphisms, in-module and inter-module Pauli measurements, T injection, and small-angle Pauli-rotation synthesis.High-level algorithms are compiled to these instructions without directly implementing Clifford gates.
  • End-to-end evaluation: The compilation algorithm and bicycle instructions support end-to-end resource estimates for random circuits and a 10 × 10 transverse-field Ising model.The reported comparison finds about an order of magnitude larger logical circuits within fixed physical-qubit budgets than conventional surface-code architectures.
  • Engineering opportunities: A practical boundary is the need for long-range intramodule and intermodule couplers, although the paper notes superconducting demonstrations and argues the engineering challenge is not insurmountable.Modules contain fewer than 1000 physical qubits, with intramodule couplers tens of lattice sites long.
  • Fabrication: At an optimistic 99.98% junction yield, gross and two-gross bicycle modules have fabrication success probabilities of about 2/5 and 1/5, versus about 1/3000 for a 5000-qubit monolithic surface-code chip.Defect-tolerant surface-code fabrication can reduce effective code distance and computational capacity.
  • Modularity comparison: Matching a two-gross module’s random-circuit capability requires distance-17 surface-code modules, expected from only 1 in 66 000 samples under the paper’s comparison.The surface-code module is optimistically idealized; strictly 2D-local connectivity would require more ancilla logical qubits for Clifford computation.

Opportunities

The bicycle architecture has several avenues for improvement, including reducing runtime overhead, improving decoding, enlarging codes, simplifying instructions, and redesigning the T factory.

  • Reducing time overhead: More than 10× longer runtime accompanies the bicycle architecture’s roughly 10× physical-qubit reduction relative to surface codes.Compilation changes, lower-overhead Pauli synthesis, and alternative measurement strategies are proposed to reduce this time overhead.
  • Decoding with speed and accuracy: Real-time decoding is expected for some single-code instructions but remains unclear for large inter-module measurements.Decoder-parameter choices or decomposing the decoding problem may help address these larger cases.
  • Increasing code and circuit distances: The bivariate bicycle code family offers larger-distance constructions whose conjectured kd^2/n ratio approaches 24, versus 1 for the surface code.The gross and two-gross codes already have ratios 12 and 13.5, respectively.
  • Modifying the bicycle instructions: Simpler instruction circuits, faster surgery, parallel logical measurements, and a larger logical-operation set could reduce time overhead, but some options increase qubit overhead.Inter-module measurements are identified as especially complex and error-prone targets for simplification.
  • Utilizing long-range connectivity for the T factory: The current T factory uses a surface-code design, leaving open whether higher bicycle connectivity can support more efficient distillation or cultivation.Practical small LDPC constructions for mass magic-state production remain an important open problem.

A.1 Logical code bases

The gross and two-gross codes use polynomially described logical operators and carefully selected logical bases to support measurements, Clifford computation, and efficient surgery-based processing.

  • Computational capability: qLDPC surgery enables arbitrary X- or Z-basis measurement and the full 11-qubit Clifford group on any 11 of 12 logical qubits.One logical qubit is sacrificed for gate synthesis in the Pauli-based computation approach.
  • Code construction: The gross and two-gross codes have parameters [[144, 12, 12]] and [[288, 12, 18]], respectively, with the latter using a 12 × 12 cell grid.Both use the same long-range-connection translations but differ in torus size.
  • Polynomial formalism: Polynomial operators satisfy logicality conditions pB + qA = 0 for X operators and rA^⊤ + sB^⊤ = 0 for Z operators.The polynomial formalism uses arithmetic over F2[x, y]/⟨x^ℓ−1, y^m−1⟩.
  • Logical-operator structure: Shift-related logical operators reflect translational symmetry, while X/Z duality maps logical operators between the two Pauli types.These relationships support the construction of compatible logical bases.
  • Logical-basis requirements: The selected logical bases generate the full 12-qubit logical Pauli group and satisfy overlap and commutation properties needed for bounded LPU connectivity.These properties support Clifford computation and prevent the LPU from increasing original qubit and check degrees by more than one.
  • Basis selection: For the two-gross code, the chosen basis operators have weight 20, exceeding its distance 18 because weight-18-only choices fail the required generation property.Mixed weight-18 and weight-20 choices satisfy only zero to three of the four desired properties.

A.2 Shift automorphisms

Shift automorphisms provide fault-tolerant logical permutations generated by a small set of physical qubit movements, though the full automorphism group is harder to implement.

  • Definition and logical action: A shift automorphism applies a monomial-labelled global permutation to all L and R qubits.For both codes, shifts in ⟨x^6, y^6⟩ act as logical identity.
  • Logical shift group: Each code has 35 logically nontrivial shift automorphisms.These are the shifts not contained in the subgroup acting as logical identity.
  • Fault-tolerant implementation: Twelve fault-tolerant circuits implement six basic automorphisms and their inverses using data movement through adjacent checks.The basic shifts are x, y, x^3y^-1, xy^3, x^3y^-2, and x^2y^3.
  • Generation and logical gates: Products of at most two basic shifts generate all nontrivial shift automorphisms.The induced logical CNOT action has matrix form M = A ⊗ A over F2.
  • Scope: Additional automorphisms exist beyond shifts but are expected to be harder to implement with syndrome-measurement connectivity alone.The architecture therefore focuses on the implementable shift subgroup.

An improved logical processing unit for the gross code

The improved gross-code LPU combines two auxiliary graphs with shared connectivity and bridge edges to measure selected logical Paulis while preserving fault-distance and code connectivity.

  • Overview: The LPU measures any element of ⟨X̄1, X̄7, Z̄1, Z̄7⟩ with phenomenological fault-distance 12 using 90 ancilla qubits.LPUs from different BB-code modules can also be connected for joint logical-Pauli measurements.
  • Graph interpretation: The graph-based LPU assigns qubits to edges and opposite-type checks to vertices and cycles, encoding no logical qubits by itself.This auxiliary CSS structure is attached to the gross code to perform logical measurements.
  • Graph construction: The construction builds Gl for X̄1 and Z̄7, Gr for X̄7 and Z̄1, then joins them by vertex identification and bridge edges.This reuses the two graph constructions to support four logical operators.
  • Gl construction: Gl contains 12 vertices and 18 edges, with edges connecting pairs of logical-operator qubits that share a Z check.The edge qubits are also connected to corresponding X checks by symmetry.
  • Fault-distance improvement: For the gross-code basis, no extra expanding edges are needed because the deformed codes already have phenomenological fault-distance 12.The general construction and the two-gross code require an additional edge set for expansion and distance preservation.
  • Bridge construction: Eleven bridge edges increase relative expansion and add cycles needed for the combined logical-measurement graph.The completed graph includes ten length-4 cycles plus an additional cycle through the identified vertex and one bridge edge.

A logical processing unit for the two-gross code

The two-gross code’s LPU is constructed from graph-based components and augmented with additional edges to achieve phenomenological fault-distance 18. Its left and right subgraphs are merged into the full processing unit.

  • The two-gross code’s LPU construction follows the gross-code procedure and supports measurement of ⟨X̄1, X̄7, Z̄1, Z̄7⟩.
  • 18 is the target phenomenological fault-distance, verified for all 15 logical measurements using CPLEX.Additional edge qubits are randomly sampled, with the number of added edges increased until a satisfying set is found.
  • Left and right subgraphs: The left subgraph Gl initially has one vertex per qubit of X̄1 and 30 edges from adjacent Z checks, then receives two additional edges.Afterward, Gl contains 20 vertices, 32 edges, and an 11-cycle basis.
  • Left and right subgraphs: The right subgraph Gr is defined analogously from qubits of X̄7, with 20 vertices, 32 edges, and a nine-cycle basis after redundant cycles are removed.
  • Merged LPU: The full graph has 39 vertices, 81 edges, and a basis of 37 cycles after the left and right graphs are merged.The merge identifies a vertex from Gl with a vertex from Gr.

A.4 Logical measurement protocols

Logical measurement uses gauging measurement on graph-defined LPUs, with repeated syndrome extraction and Pauli-frame correction. The LPU supports specified in-module, inter-module, and code-factory joint measurements while controlling connectivity degree.

  • Logical measurement protocol: Gauging measurement initializes edge qubits, measures the LPU and deformed-code checks repeatedly, restores the original code, then applies a Pauli correction.The correction can be tracked in software rather than physically applied.
  • Logical measurement protocol: After correction, the procedure applies the logical projector (I + m̄L)/2 to the logical state.
  • In-module measurements: The LPU enables in-module measurement of any logical Pauli in ⟨X̄1, X̄7, Z̄1, Z̄7⟩ using appropriate graph substructures and code connections.
  • Inter-module measurements: Inter-module LPUs connected by Bell-couplers enable measurements from (⟨X̄1, Z̄7⟩ ∪ ⟨X̄7, Z̄1⟩)⊗2.The construction uses half-LPUs, bridge qubits, Bell checks, and bridge checks prepared in Bell states.
  • Connectivity design: Connecting bridge qubits between adjacent modules keeps maximum connectivity at degree 7 because bridge qubits have only 3 or 4 intra-module connections.
  • Code-factory measurements: Code-factory adapters support measurements in ⟨X̄1, X̄7, Z̄1, Z̄7⟩⊗Z̄T while maintaining maximum qubit or check degree 7 for surface-code factories.Direct vertex-check connections are limited to at most one factory module to preserve this degree bound.

A.5 Circuit scheduling for logical measurements

The scheduling methods assign timesteps to two-qubit gates while avoiding conflicts from shared qubits, Bell preparation, and anticommuting check overlaps. Graph coloring supplies reported schedules, while integer programming is left for future benchmarking.

  • Scheduling methods: Graph coloring is used for reported results, while integer-programming improvements are reserved for future work.
  • Scheduling formulation: Scheduling variables assign each check–data gate an integer timestep, with constraints preventing two gates from sharing a qubit simultaneously.
  • Scheduling constraints: Bell-check preparation is scheduled before Bell-pair interactions with data, and anticommuting check overlaps impose additional ordering constraints.For the BB and deformed codes considered, each anticommuting overlap has size 0 or 2.
  • Scheduling constraints: A timestep bound Tmax controls feasibility: sufficiently large values permit sequential schedules, whereas values below the connectivity degree can make the problem infeasible.
  • Graph-coloring schedule: Graph coloring schedules Bell initialization, LPU–BB edges, standard BB syndrome edges, LPU edges, and remaining BB–LPU edges in a fixed order.The LPU subgraph is edge-colored separately for X- and Z-check edges.
  • Graph-coloring schedule: 12Cmem timesteps are required for Cmem syndrome cycles under the graph-coloring schedule.The graph-colored LPU subcircuit dominates circuit depth and prevents later cycles from overlapping.
  • Integer-programming analysis: Integer-programming analysis models qubit lifetimes so later syndrome cycles can begin before all measurements from the previous cycle finish.
  • Integer-programming analysis: The gross code’s optimized schedules require 9C + b timesteps for C cycles, with b = 1 or 2 depending on measurement mode.The coefficient 9 is optimal because the maximum degree in the deformed codes is 7.

A.6 Cost estimates for T state cultivation

The T-state cultivation estimates combine cultivation and escape durations, discard probabilities, and qubit counts under an in-place sequential protocol. The analyzed protocols use distances 3 and 5, with total durations near ten cycles per protocol cycle count.

  • Estimation inputs: The estimates model cultivation at physical noise strength p = 10^-3 using logical error, discard probability, duration, and qubit-count inputs.
  • Estimation outputs: The end-to-end factory estimates identify mean preparation time and factory error probability with the corresponding end-to-end quantities.
  • Protocol assumption: The analysis assumes in-place sequential cultivation, reducing qubit overhead and simplifying control while potentially increasing preparation time through reduced parallelism.
  • Protocol parameters: For d1 = 3, the protocol uses r = 13, r1 = 3, r2 = 5, and d2 = 15; for d1 = 5, it uses r = 20, r1 = 5, r2 = 5, and d2 = 15.
  • Time estimates: For d1 = 3, cultivation takes 39 timesteps and escape takes 90; for d1 = 5, cultivation takes 89 and escape takes 110.In both cases, total duration is close to 10r timesteps.
  • Qubit estimates: The end-to-end protocols with r1 = 3 and r1 = 5 use 454 and 463 qubits, respectively, while the r1 = 5 inject-and-cultivate protocol uses 42 qubits.

A.7 Simulation of bicycle instructions

The simulations estimate bicycle-instruction logical error rates under circuit-level noise using decoding matrices, Monte Carlo sampling, and failure-spectrum fits. They use Relay-BP decoding and model assumptions to extrapolate performance across fault weights.

  • Circuit-level simulations assume an error-free initial codestate and a final cycle of noise-free stabilizer measurements.
  • The full syndrome and fault set are represented by binary check and logical-action matrices, H and A, with their interpretation depending on the logical operation.For unitary operations, A spans logical operators; for logical measurements, it spans the commuting subgroup.
  • Decoder correction succeeds when the inferred correction and actual fault have identical logical action, Ac = Ae; otherwise the trial fails.The decoder first computes σ = He, returns c = D(σ), and is typically guided by a probable fault consistent with the syndrome.
  • The circuit distance D is the minimum undetectable fault causing a nontrivial logical action, whereas the practical decoder’s minimum failing weight need not equal ⌈D/2⌉.The equality w0 = ⌈D/2⌉ holds for an optimal decoder, but these simulations use Relay-BP instead.
  • Relay-BP provides fast, accurate decoding through disordered memory terms and serialized ensembling that produces multiple candidate corrections.Its parameters vary with the circuit being decoded and are listed in Table 7.
  • Monte Carlo estimates count failures over repeated noisy trials, while the failure spectrum f(w) measures the fraction of weight-w faults causing logical failure.Idle and shift instruction error rates are normalized by the number of repeated cycles in their simulated circuits.
  • Failure-spectrum fits use an ansatz with w0 = 5 for gross instructions and w0 = 9 for two-gross instructions, with conservative treatment of deviations above w > 80 for ¯Y1.Fit uncertainty is estimated by bootstrap resampling and reported as shaded regions around the fits.

A.8 Distance validation of bicycle instructions

The appendix validates bicycle-instruction distances by analyzing space-like and time-like logical failures in deformed and subsystem codes. It formulates both distance calculations as minimum-weight Pauli optimization problems and uses CPLEX for the resulting integer programs.

  • A.8 Distance validation of bicycle instructions: Phenomenological validation models data-qubit depolarizing noise and measurement bit flips while abstracting away circuit-level check implementation.This provides a simplified model for validating qLDPC surgery constructions.
  • A.8 Distance validation of bicycle instructions: Space-like failures are logical errors commuting with the measured Pauli, while time-like failures arise from errors during the code deformation.The two failure classes are analyzed separately.
  • A.8 Distance validation of bicycle instructions: The space-like distance is the minimum of the original-code distance d and deformed-code distance d*_s, with the deformed code often no better than the original.The best supported case is d*_s = d.
  • A.8 Distance validation of bicycle instructions: The time-like distance is dt = min(C, d*_t), where d*_t is the minimum weight of a logical or gauge operator anticommuting with the measured operator.The deformation is represented by the subsystem-code gauge group Gdef = ⟨S, S′⟩.
  • A.8 Distance validation of bicycle instructions: For the deformed-code analysis, choosing C = d is sufficient because the relevant time-like distance is upper bounded by the original code distance.The validated results are summarized in Table 8.
  • A.8 Distance validation of bicycle instructions: Both d*_s and d*_t reduce to finding the minimum-weight Pauli commuting with selected checks while anticommuting with a target operator.The problem is expressed using symplectic bit strings and a commutation matrix.
  • A.8 Distance validation of bicycle instructions: The code distance is obtained by solving the optimization problem for each logical-basis operator and taking the minimum solution; CPLEX formulates it as an integer linear program.Pauli weight is linearized from the binary X and Z components.
  • A.10 Logical capability comparison details: Resource comparisons compute bicycle failure probabilities from instruction error rates and counts, then compare them with surface-code requirements across physical error rates.The bicycle two-gross architecture reaches failure probability 10^-3 at p ≤ 7.32 × 10^-4, while application-region boundaries are constructed from convex hulls of algorithm instances and remain approximate.
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