Tour de gross: A modular quantum computer based on bivariate bicycle codes

1 Introduction

• Long-range connectivity enables modular hardware and makes low-overhead quantum LDPC codes practical, but implementing the required couplers remains challenging.Modules contain fewer than 1000 physical qubits, with intramodule couplers tens of lattice sites long; intermodule couplers scale with code distance.Source: §1 · pp. 3–4
• Approximately an order of magnitude more logical qubits can be executed than with conventional surface-code architectures using the same physical resources and error rates.Figure 1 compares bicycle and surface-code capabilities across physical qubit counts q = 5k, 50k, 500k and error rates p = 10^-3, 10^-4; TFIM simulation is estimated at 8138 ≈8k physical qubits when p ≈7 × 10^-4.Source: Figure 1 · p. 3, §1 · p. 3

1.1 Fault-tolerant architecture criteria

• The architecture is designed to satisfy six criteria: fault-tolerant, addressable, universal, adaptive, modular, and efficient.Efficiency depends on hardware, codes, logical operations, decoding, control speed, and module fabrication success.Source: §1.1 · p. 4
• Gross and two-gross bivariate bicycle codes each encode 12 logical qubits, while two-gross provides better error suppression at twice the physical-qubit cost.Parallel syndrome measurement circuits support low logical error rates, and logical Pauli measurements, teleportation-based T operations, real-time decoding, and generalized lattice surgery provide the required capabilities.Source: §1.1 · pp. 4–5

1.2 The bicycle architecture

• The bicycle architecture uses connected code and T-factory modules with long-range entangling components, and each code module stores 12 logical qubits.Modules may use linear or triangular connectivity and include code, LPU, factory, and adapter components.Source: §1.2 · p. 5, Figure 2 · p. 5
• Bicycle instructions include shift automorphisms, multi-qubit Pauli measurements within or between modules, and T-state injection from adjacent factories.Shift automorphisms act as paired six-qubit unitaries across the 12 logical qubits, while modules designate qubit 1 as a pivot ancilla.Source: Figure 2 · p. 5, §1.2 · p. 5

• Any automorphism unitary in the 36-element group A is a product of at most two generators for both gross and two-gross codes.Source: Appendix A.2 · p. 6
• The instruction set includes 15 in-module measurements of non-trivial Paulis and 36 inter-module measurements of Pauli products across connected code modules.Source: Appendix A.2 · p. 6
• T injection uses six cases, each preparing a T state, performing an inter-module ¯Z_T⊗¯P measurement, and destructively measuring the factory in the ¯X basis.The six cases take ¯P ∈ {¯X_1, ¯Y_1, ¯Z_1, ¯X_7, ¯Y_7, ¯Z_7}.Source: Appendix A.2 · p. 6
• Because the codes are CSS, all 12 logical qubits can be prepared in |0⟩ or |+⟩ and destructively read out in the X or Z basis without added time or noise.These preparation and measurement operations are omitted from Table 2 under the surface-code-like assumption.Source: Appendix A.2 · p. 6
• Table 2 characterizes idle and bicycle instructions by duration and logical error rate under independent logical errors and physical circuit noise, with uncertainty from Monte Carlo bootstrapping.Square-bracketed values are assumed without data and left for future justification.Source: Table 2 · p. 7

2 Fault-tolerant implementation of the bicycle architecture

• The architecture combines quantum LDPC surgery with explicit constructions for [[144, 12, 12]] gross and [[288, 12, 18]] two-gross codes, including module connections and surface-code magic-state factories.The constructions use bridges and adapters, with physical interconnection implemented through Bell-pair generation.Source: §2 · p. 8

2.1 Review of bivariate bicycle codes

• The studied bivariate bicycle codes use toric layouts with long-range connections, achieving the two code instances’ specified qubit counts and distances.The toric-layout description is sufficient for this work but covers only a special case of bivariate bicycle codes.Source: §2.1 · pp. 8–9

2.2 Idles and shift automorphisms

• Idle instructions measure all checks, while shift automorphisms implement logical permutations through swaps; each shift uses 14 timesteps and 12 distinct instruction types are available.A BB module uses c = 4ℓm qubits, totaling 288 for the gross code and 576 for the two-gross code.Source: §2.2 · pp. 10–11

2.3 In-module measurements

• In-module surgery measures logical Paulis using an LPU, with C = 10 syndrome cycles for gross and C = 18 for two-gross, and combined measurements and shifts support the full Clifford group on 11 of 12 module qubits.The LPU construction advances prior work by covering both codes, using lower-weight logical operators, and simplifying the measurement construction.Source: §2.3 · p. 11

2.4 Inter-module measurements

• Inter-module adapters enable 36 code-code logical Pauli products while preserving fault-tolerance with six required errors for gross and nine for two-gross operations.Code-factory adapters add O(d) Bell-couplers and enable any logical Pauli on the four supported module operators tensored with the factory’s logical Z.Source: §2.4 · p. 13

2.5 T injections

• T injection prepares a reliable T state in a surface-code factory, then performs a joint factory-code measurement and destructive factory measurement; the study considers cultivation at p = 10^-3 and distillation at p = 10^-4.Cultivation is selected for small-size, connectivity-compatible factories, while the distillation assumptions use 15-to-1 protocols implemented in surface codes.Source: §2.5 · p. 14

2.6 Benchmarking bicycle instructions

• Instruction validation uses stochastic circuit-level noise with rate p, relay-BP decoding, circuit distance, and phenomenological fault-distance calculations for the gross and two-gross codes.The phenomenological model is used to validate LPU constructions rather than for noisy simulations, and its fault-distance is at least the circuit distance.Source: §2.6 · p. 15
• The simulations extract logical error rates for bicycle instructions from failure-spectrum fits, using circuit distances of 10 for gross and 18 for two-gross.The fitted ansatz vanishes below half the circuit distance and agrees with independently obtained logical-error data; the gross fit conservatively excludes high-weight deviations for one representative measurement.Source: §2.6 · pp. 16–17
• At p = 0.001, the two-gross idle instruction is estimated at 10^-20 logical error rate versus about 10^-10 for a rotated d = 17 surface code, though the extrapolation warrants caution.The proposed advantage may reflect fewer low-weight logical operators: 336 weight-18 X-logicals for two-gross versus 875 178 for a d = 18 rotated toric code.Source: §2.6 · p. 17

2.7 Future directions

• Future instruction-set extensions could enable parallel or broader logical measurements and additional code-code adapters, reducing the time overhead of compilation and potentially saving operations.These directions include larger LPUs and measurement capabilities without relying on code automorphisms [Cow+25], plus adapters informed by Ref. [SJY24].Source: §2.7 · pp. 17–18
• Connectivity could be improved through time-dynamics, code morphing, concatenation, or related techniques that lower qubit degree or enhance computational capacity.The architecture already considers maximum qubit degree, while these approaches are suggested by prior work [MBG23] [ST25] [PKP23] [Ber+25].Source: §2.7 · p. 18
• Future work should seek larger circuit distances and realistic noise simulations, especially because the gross circuit distance is at most 10 and measurements or Bell-couplers may fail an order of magnitude more often than gates.The two-gross circuit distance may also be below 18, and heterogeneous component noise could worsen estimates by an uncertain amount.Source: §2.7 · p. 18
• Inter-module operations currently appear particularly limiting because code-code adapters introduce many low-weight logical operators and relay-BP decoding may fail or be poorly optimized.Potential remedies include redesigned adapters, adjusted error priors, combined decoding strategies as in Ref. [Cro+24], and parameter optimization that can produce order-of-magnitude changes [Mül+25].Source: §2.7 · p. 18
• The very low two-gross logical-error extrapolations should be tested in the low-logical-error regime, alongside assumptions about immediate measurement restart and fault-tolerant module initialization.These assumptions have precedent in surface-code lattice surgery [Lit19a].Source: §2.7 · pp. 18–19

3 Compiling to the bicycle architecture

• The proposed compiler translates Clifford+P(φ) circuits into bicycle instructions through Pauli-based computation, module distribution, in-module measurement synthesis, and T-state-assisted rotations.The input assumes |0^n⟩ preparation and final computational-basis measurements; the compilation process is summarized in Figure 8.Source: §3 · pp. 20–21, Figure 8 · p. 20

3.1 Distributing operations across data modules

• The compiler distributes n-qubit operations across M = ⌈n/11⌉ modules, reserving one pivot per 12-qubit module and reducing global operations to inter-module measurements plus in-module operations.The construction uses GHZ states linking module pivots and applies to linear connectivity, with adaptations possible for other module connectivities.Source: §3 · p. 20, §3.1 · pp. 21–22

3.2 In-module Pauli measurement synthesis

• Both gross and two-gross codes support 540 native measurements and 510 native rotations, whose rotations generate the Clifford group and enable arbitrary in-module Pauli measurements.Native measurements are implemented from bicycle measurements and shift automorphisms, while arbitrary measurements are obtained by Clifford conjugation.Source: §3.2 · p. 24

3.3 Small-angle rotations

• For Clifford+T circuits, the compiler implements π/4 Pauli-generated rotations exactly, with conditional Clifford corrections absorbed into the final Pauli-basis measurement.More generally, arbitrary-angle rotations are approximated using Ross–Selinger synthesis into T, S, and H gates, followed by T-state injection and classically conditioned corrections.Source: §3.3 · pp. 25–26

3.4 Future directions

• The scheme consumes only GHZ entanglement between modules and supports arbitrary-angle rotations without additional global-entanglement overhead, but large-support rotations can serialize execution and increase noise.Future improvements include preserving parallelism for disjoint-support operations and reducing the cost of repeated arbitrary Pauli-measurement synthesis.Source: §3.4 · pp. 26–27
• Directly synthesizing CCZ |+⟩⊗3 states could reduce the T-state cost of Toffoli synthesis, while tailored non-Clifford schemes may increase T-state consumption rate [GF19] [Bev+20].Each CCZ state can synthesize a Toffoli gate instead of seven, or four in some cases, T |+⟩ states.Source: §3.4 · p. 27
• About 5.4× lower average T-state consumption is possible for small-angle rotations using probabilistic routines with ancillas, measurement, and feedforward [Kli+23].Brute-force methods can also minimize T counts for approximations up to precision about 10^-17.Source: §3.4 · p. 27

Approach

• Resource estimates assume 1D nearest-neighbor module connectivity, n = 11M logical data qubits, and runtimes derived by timing optimized compiled bicycle instructions from Table 2.Circuit failure is computed assuming identical logical errors, with idle instructions inserted whenever modules wait.Source: §4 · p. 28

Requirements for simulating the transverse-field Ising model

• q = 4817 physical qubits suffice for gross-code TFIM simulation versus 17 010 for surface code at d = 9, but require p ≤2.1 × 10^-5 versus p ≤5.4 × 10^-5.The simulation uses 1.8 × 10^5 Pauli-generated rotations and targets about 10^-3 error.Source: Figure 10 · p. 29, §4 · p. 30
• q = 8138 two-gross-code qubits suffice for TFIM simulation at p ≤7.3 × 10^-4, versus 58 263 at d = 17 or 72 663 at d = 19 for surface code.The estimate requires NT = 1.9 × 10^7 T injections and motivates a 10^-3 two-gross factory.Source: Figure 10 · p. 29, §4 · p. 30

Capability estimation: random circuits

• The bicycle architecture has longer runtime per T than surface code, mainly because compilation overhead limits performance when using one T factory.Additional T factories can move surface-code performance closer to 6d timesteps per rotation, while bicycle improvements target LPU size, synthesis, and inter-module measurements.Source: §4 · p. 29

Further remarks on resource estimates

• The bicycle architecture provides about an order of magnitude more logical data qubits than surface-code architectures at fixed T count, though 5k-qubit devices at p = 10^-3 need roughly 10× higher T-count capability.The authors consider roughly 10× better inter-module logical error rates a plausible route to that improvement.Source: §4 · p. 30

Advances in surface code architectures

• Recent surface-code proposals add concatenation or transversal gates, representing major changes to the conventional baseline compared in this section.The authors expect analogous improvements for bicycle architectures through further research.Source: §4 · p. 30

Architecture

• The bicycle architecture satisfies six scalability criteria through circuit-noise fault tolerance, logical addressability, Clifford-plus-T universality, adaptive decoding, modular Bell-pair connectivity, and lower qubit overhead.It uses gross and two-gross bivariate bicycle codes with self-contained code blocks connected by long-range Bell pairs.Source: §5 · p. 31

Instructions and compilation

• Custom bicycle instructions—shift automorphisms, intra- and inter-module Pauli measurements, and T injection—support compilation without directly implementing Clifford gates.Local T-state injection also synthesizes small-angle Pauli-generated rotations.Source: §5 · p. 31

End-to-end resource estimates

• About an order of magnitude larger logical circuits fit within fixed physical-qubit budgets than with conventional surface codes, at the cost of increased compilation runtime.This was demonstrated on random circuits and a 10 × 10 2D transverse-field Ising model.Source: §5 · p. 31

Fabrication yield

• At a 99.98% junction yield, gross and two-gross modules succeed approximately 2 in 5 and 1 in 5 times, whereas a monolithic 5,000-qubit surface-code chip succeeds about 1 in 3,000 samples.Larger perfect monolithic chips are described as astronomically unlikely; defect encoding can reduce effective code distance and computational capacity [SBD09] [Aug+17] [Lin+24] [Deb+24] [Ler+24].Source: §5 · p. 31

Surface-code comparison

• Matching a two-gross module on random circuits requires distance-17 surface-code modules, expected to function only 1 in 66 000 samples, while smaller modules need 10 times more inter-module couplers.The resulting modular bicycle system is described as 10 times smaller with looser yield and fabrication-tolerance demands.Source: §5 · p. 31

Limitations

• The surface-code comparison assumes an optimistically idealized module; with strictly 2D-local connectivity, additional ancilla logical qubits are needed for Clifford computation [Lit19a].This qualification is attached to the surface-code module used in the fabrication argument.10Source: §5 · p. 31

Reducing time overhead

• Reducing runtime overhead is a priority because the architecture uses an order of magnitude fewer physical qubits but takes more than an order of magnitude longer to run than the surface code.Potential remedies include architecture-specific compilation, alternative logical-measurement decompositions, and circuits emphasizing Pauli operations.Source: Opportunities · p. 32

Decoding with speed and accuracy

• Real-time decoding is required for adaptivity, but accurate decoding of the largest inter-module measurements remains uncertain with current techniques.Idles and automorphisms may be tractable using recent work [Mül+25], while decoder tuning or problem decomposition [Cro+24] could address larger instructions.Source: Opportunities · p. 32

Increasing code and circuit distances

• Larger code distances and new code families could improve protection and overhead, with a proposed BB family approaching k d^2/n = 24 versus 1 for the surface code.For the gross and two-gross codes, the ratio is already 12 and 13.5, respectively; long-range coupling could also support other quantum LDPC constructions.Source: Opportunities · p. 32

Modifying the bicycle instructions

• Improving bicycle instructions could reduce circuit complexity and time overhead, especially for error-prone inter-module measurements, but parallelization or faster surgery may require more qubits and connectivity.The instruction set could also be expanded with additional shift automorphisms and more logical Pauli measurements.Source: Opportunities · p. 32

Utilizing long-range connectivity for the T factory

• Long-range connectivity could enable more efficient T factories through BB-code distillation or cultivation, other LDPC codes, or cultivation without distillation, potentially producing CCZ and other non-T magic states.Small, practical LDPC constructions for mass magic production remain an open problem.Source: Opportunities · p. 33

A.1 Logical code bases

• The selected logical bases enable X- and Z-basis measurement and the full 11-qubit Clifford group on any 11 of 12 logical qubits.These capabilities arise from qLDPC surgery, shift automorphisms, and sacrificing one logical qubit for gate synthesis.Source: §A.1 · p. 43
• The appendix derives logical-operator validity using polynomial arithmetic over F2[x, y]/⟨x^ℓ−1, y^m−1⟩, with X(p, q) logical exactly when pB + qA = 0.The formalism represents toroidal translations by x and y and defines transpose-polynomial relations for Z operators.Source: §A.1 · pp. 43–44
• The gross and two-gross codes have parameters [[144, 12, 12]] and [[288, 12, 18]], respectively, with the latter assembled from a 12 × 12 unit-cell grid.Both use ℓ=12 and the same long-range connections, while the two-gross code doubles the unit-cell dimensions in the second direction.Source: §A.1 · p. 43, Figure 11 · p. 44
• ZX-duality and translational shift automorphisms relate logical operators while allowing fixed-connectivity auxiliary structures to be reused, effectively halving LPU size.The chosen operators’ adjacency graphs are isomorphic under these relations, supporting simpler connectivity in the logical processing unit.Source: §A.1 · pp. 43–45
• The logical-basis conditions ensure Clifford sufficiency while increasing the original code’s qubit and check degree by no more than one.The conditions require anticommuting designated pairs, generation of the full logical Pauli group, controlled overlap patterns, and disjoint check neighborhoods.Source: §A.1 · p. 45
• For the gross code, the selected basis operators are minimal weight 12, whereas the two-gross basis uses weight 20, two above its distance 18.For two-gross, weight-18-only choices fail the full-generation condition, and mixed weight-18/20 choices satisfy only zero through three required properties.Source: §A.1 · p. 45
• Weight-12 and weight-14 enumeration found 1884 and 19728 gross-code logical X operators, while weight-18 and weight-20 enumeration found 336 and 1728 for two-gross.The same counts hold for logical Z operators through ZX-duality; BP+OSD enumeration took less than 25 minutes on a laptop.Source: Figure 12 · p. 46

A.2 Shift automorphisms

• 35 logically nontrivial shift automorphisms remain for both the gross and two-gross codes, since shifts in ⟨x6, y6⟩ act as logical identity.A shift automorphism is defined by a monomial δ implementing the global permutation (L, α) → (L, δα) and (R, α) → (R, δα).Source: §A.2 · pp. 46–47
• Twelve fault-tolerant circuits implement shift automorphisms and inverses using existing Tanner-graph connectivity, with data routed through X or Z checks along polynomial terms.Six circuits implement automorphisms and six implement their inverses by moving data between data qubits and checks before returning it to qubit positions.Source: §A.2 · p. 47
• The basic shifts are {x, y, x3y−1, xy3, x3y−2, x2y3} and their inverses, and products of at most two suffice to generate every nontrivial shift automorphism.These operations constitute the logical gates ¯U1, . . . , ¯U6 described in Section 1.2.Source: §A.2 · p. 47
• The full automorphism group is larger than the shift subgroup, but the additional automorphisms are expected to be harder to implement using only syndrome-measurement connectivity.This limitation applies to both the gross and two-gross codes.Source: §A.2 · p. 47
• Physical-qubit permutations induce logical CNOT circuits whose matrices have the form M = A ⊗ A for A ∈ F6×6_2 in the specified 12-qubit logical basis.The logical operators split into two six-qubit groups, constraining automorphisms to act through corresponding linear transformations on each group.Source: §A.2 · p. 47

An improved logical processing unit for the gross code

• A 90-ancilla system measures any element of ⟨¯X1, ¯X7, ¯Z1, ¯Z7⟩ with phenomenological fault-distance 12.LPUs from different bivariate bicycle codes can also connect to measure joint logical Paulis.Source: An improved logical processing unit… · p. 48
• The complete auxiliary graph G combines graph Gl for ¯X1 and ¯Z7 with graph Gr for ¯X7 and ¯Z1.The two graphs are joined by vertex identification and bridge edges.Source: An improved logical processing unit… · p. 48
• For Gl, 12 monomial-labeled vertices connect to gross-code qubits supporting ¯X1 and their transposed partners supporting ¯Z7.This uses the ZX-duality relation between ¯X1 and ¯Z7.Source: An improved logical processing unit… · p. 48
• Gl adds 18 edges so gross-code checks gain support on at most one qubit during the corresponding logical measurement deformations.Each edge qubit connects to the relevant Z check and, by symmetry, an adjacent X check.Source: An improved logical processing unit… · p. 48
• The chosen gross-code basis requires no additional expanding edges because the deformed codes already have phenomenological fault-distances of 12.This applies to measurements of ¯X1 and ¯Z7 and is established in Appendix A.8.Source: An improved logical processing unit… · p. 48
• Gr follows the same construction for ¯X7 and ¯Z1 and uses a reduced cycle basis of three cycles.Like Gl, it needs no additional expanding edges.Source: An improved logical processing unit… · p. 49
• The final graph identifies vertices x4R and x9yL, then adds 11 bridge edges to increase its relative expansion.The identification reflects the single-qubit overlap of the paired logical operators, while Bell-pair implementation avoids an unnecessarily weight-8 vertex check.Source: An improved logical processing unit… · p. 49
• The bridge edges contribute 11 additional cycles: 10 length-4 cycles and one cycle through the identified vertex.Together with the cycles inherited from Gl and Gr, these complete the cycle basis of G.Source: An improved logical processing unit… · p. 49

• The logical processing unit enables measurement of any element of ⟨¯X1, ¯X7, ¯Z1, ¯Z7⟩, following the gross-code construction.Source: A logical processing unit for the… · p. 49
• Phenomenological fault-distance 18 requires additional edge qubits, selected by increasing-size random samples checked with CPLEX across all 15 logical measurements.Sampling begins with one-edge sets and increases the number of edges until a satisfying choice is found, minimizing additions.Source: A logical processing unit for the… · p. 50
• Each component graph has 20 vertices and 32 edges after adding two edges, with cycle bases of 11 cycles for Gl and 9 for Gr.Gl and Gr are built from qubits of ¯X1 and ¯X7, respectively, with edges corresponding to 30 adjacent Z checks.Source: A logical processing unit for the… · p. 50
• Merging Gl and Gr identifies one vertex and adds 17 bridge edges; the resulting full graph has 39 vertices, 81 edges, and 37 basis cycles.The full cycle basis includes 16 indicated length-4 cycles and one additional length-3 cycle.Source: A logical processing unit for the… · pp. 50–51

Logical measurement protocol

• Gauging measurement [WY24] measures LPU and deformed-code checks, repeats the deformed-code measurements C times for fault tolerance, returns to the original code, and applies a Pauli correction.Source: §A.4 · p. 51
• The protocol applies the logical projector (I + m̄L)/2, with correction and path choices equivalent because the measured state is projected into an eigenstate of L.After correction, every cycle has product of edge-measurement outcomes +1; changing the reference vertex changes the correction by at most the measured logical operator.Source: §A.4 · p. 51

In-module measurements

• Half-LPU subgraphs measure the non-trivial elements of ⟨X̄1, Z̄7⟩ or ⟨X̄7, Z̄1⟩, while the entire LPU measures the other nine non-trivial operators.Only the qubits, checks, and code connections in the selected subgraph are active for each measurement.Source: §A.4 · p. 52

Inter-module measurements

• Bell-coupled LPUs enable inter-module measurement of any element of (⟨X̄1, Z̄7⟩ ∪ ⟨X̄7, Z̄1⟩)⊗2 using half-LPUs, bridge qubits, and Bell checks.Connecting bridge qubits keeps maximum connectivity controlled: modules joined through bridge qubits can connect to three other modules without exceeding degree 7.Source: §A.4 · pp. 52–53

Code-factory measurements

• Connecting BB-code LPU vertices to a factory’s logical Z̄T supports measurement of any operator in ⟨X̄1, X̄7, Z̄1, Z̄7⟩⊗Z̄T while preserving maximum degree 7.A path through d vertices is chosen to avoid vertices and edges already at degree 7; direct vertex-check connections are limited to at most one factory module.Source: §A.4 · pp. 53–54

Scheduling formulation

• The scheduling model assigns integer timesteps to check–data gates and Bell-preparation CNOTs, then schedules check-qubit initialization and measurement around those assignments.The connectivity graph distinguishes check qubits from checks and represents Bell checks as connected check-qubit pairs.Source: §A.5 · p. 54

Scheduling constraints

• Feasible schedules enforce noncollision, Bell-preparation, anticommuting-overlap, and bounded-horizon constraints, with infeasibility for sufficiently small Tmax and feasibility for sufficiently large Tmax.For the bivariate bicycle and deformed codes, anticommuting overlaps have size 0 or 2.Source: §A.5 · pp. 54–55

Graph coloring

• 12C timesteps are required for Cmem syndrome cycles under the graph-coloring schedule, whose LPU subcircuit dominates depth and prevents overlap between subsequent cycles.The schedule initializes Bell states, processes LPU–BB edges, uses the standard BB cycle, and colors LPU X- and Z-check edges into layers.Source: §A.5 · pp. 55–56

Integer programming

• The integer-programming objective minimizes the maximum qubit lifetime across syndrome cycles, using linearization and auxiliary variables, and is solved with CPLEX.A subsequent per-check optimization reduces individual check-qubit lifetimes after the initial maximum-lifetime solution.Source: §A.5 · pp. 56–57
• 9C + b timesteps are required for C syndrome cycles in the gross code, with b = 1 or 2 by measurement mode, and both coefficients are optimal under the fixed BB schedule.The corresponding optimization problems become infeasible when Tmax is below 10 or 11, respectively; solving each gross-code case takes roughly a second.Source: §A.5 · p. 57

Cost-estimate framework

• Table 5 summarizes end-to-end T-state cultivation estimates, including logical error, discard probabilities, mean preparation time, and qubit counts based on [GSJ24].The overall factory parameters are identified as ¯τ_factory = ¯τ_e2e and P_factory = P_e2e.Source: Table 5 · p. 57, §A.6 · p. 57

Protocol assumptions

• Sequential in-place cultivation is assumed because it simplifies control and reduces qubit overhead, although it may increase preparation time by removing parallelism.States may be discarded either after cultivation or after the gap computation during escape.Source: §A.6 · p. 57

Circuit-depth estimates

• For d1 = 3, cultivation takes 39 timesteps and escape plus matchable-code idling takes 90; for d1 = 5, the corresponding times are 89 and 110.The protocols use r = 13, r1 = 3, r2 = 5 for d1 = 3, and r = 20, r1 = 5, r2 = 5 for d1 = 5, with d2 = 15 in both cases.Source: §A.6 · p. 58

Qubit resources

• 454 and 463 qubits are used by the r1 = 3 and r1 = 5 end-to-end protocols, while the r1 = 5 inject-and-cultivate protocol uses 42 qubits.These sizes are consistent with distance-15 surface-code and distance-5 hexagonal color-code sizes.Source: §A.6 · p. 58

Simulation assumptions

• Simulations assume an error-free initial codestate and a final cycle of noise-free stabilizer measurements when estimating instruction-level logical error rates.For computational convenience, faults are modeled as independent events with equal probability q = p/15.Source: §A.7 · p. 58

Decoding definitions

• Logical decoding maps fault configurations to syndromes and logical actions using binary matrices H and A, with correction succeeding when Ac = Ae.The decoder returns a correction c satisfying Hc = σ, and failure occurs otherwise.Source: §A.7 · pp. 58–59

Syndrome circuits

• Bell-pair experiments encode one qubit of each pair, run noisy syndrome circuits, and perform logical Bell measurements to expose both X and Z logical errors.Logical X measurements instead initialize the measured qubit in the |+⟩ state; this follows the method used in [Cro+24].Source: §A.7 · p. 59

Relay-BP decoder

• Relay-BP provides the simulations’ real-time decoder, using disordered memory terms and serialized ensembling to avoid trapping states while retaining a footprint similar to standard belief propagation.Its parameters vary by decoded circuit and are reported in Table 7.Source: §A.7 · p. 59

Monte Carlo and fitting

• Monte Carlo failure rates are supplemented by failure-spectrum fits, with low-weight faults dominating truncated sums and bootstrap resampling providing uncertainty bands for extrapolated estimates.Fits use w0 = 5 for gross instructions and w0 = 9 for two-gross instructions; higher-weight ¯Y1 points above w > 80 are conservatively excluded.Source: §A.7 · pp. 59–60

A.8 Distance validation of bicycle instructions

• Phenomenological fault-distance is analyzed through space-like and time-like logical failures under data-qubit depolarizing noise and check-measurement bit flips.Space-like errors alter stored logical information, whereas time-like errors corrupt the measured logical result; the two types can combine.Source: §A.8 · pp. 60–61
• The space-like distance is governed by the minimum of the original and deformed-code distances, while the time-like distance is obtained from a subsystem-code analysis.The relevant subsystem gauge group combines the original and deformed stabilizers with single-qubit Z_e operators on edge qubits.Source: §A.8 · p. 61
• CPLEX verification finds d*_t = d for all tested in-module logical measurements of the gross and two-gross codes, with nine cases covering 15 through ZX-duality.Inter-module distances are directly verified for some cases and otherwise supported by Theorem 24 in [Cro+24] under CSS and minimum-weight assumptions.Source: §A.8 · pp. 62–63

A.9 Pauli-based computation

• Pauli-based computation converts general circuits into Pauli-generated rotations and multi-qubit Pauli measurements, eliminating physical Clifford gates by absorbing them into later observables.The approach extends prior PBC compilation frameworks, including [BSS16], [BK05],, and [Lit19a].Source: §A.9 · p. 64

A.10 Logical capability comparison details

• Application regions are constructed as convex hulls of algorithm instances for cryptography, quantum chemistry, and scientific toy models, extended toward larger qubit and T-gate counts.The regions are based on data from Scholten et al. [Sch+24] and are illustrated in Figure 16.Source: §A.10 · p. 65, Figure 16 · p. 65
• The classical-simulation region is approximated as fewer than 75 qubits or fewer than 75 T gates, acknowledging that the boundary is approximate.The estimate is contextualized by reported simulations of 40 qubits and 50 T gates [BG16] and 50 qubits and 60 T gates [Bra+19].Source: §A.10 · p. 65
• The TFIM resource estimate uses 100 sites, evolution time t = 20, 80 fourth-order product-formula steps, and 184 000 Pauli-generated rotations.The compilation uses small-angle synthesis error 5 × 10^-9 ≈ 10^-3/NR and worst-case timing information.Source: §A.10 · p. 67
• p ≤ 2.09 × 10^-5 is required for the gross architecture, while two-gross reaches failure probability 10^-3 at p ≤ 7.32 × 10^-4.These thresholds come from interpolating the augmented TFIM circuit’s failure probabilities across physical error rates.Source: §A.10 · p. 67
• Table 10 estimates logical error rates for gross and two-gross codes across bicycle instructions at various physical error rates p.Worst-case instruction error rates, Pi, are extrapolated for idle and most bicycle instructions using Appendix A.7, while other values come from Table 2.Source: Table 10 · p. 68
• The TFIM circuit failure probability is obtained by multiplying instruction error rates by instruction counts Ni from Table 9.The calculation uses the resulting instruction-level error estimates to aggregate failure over the simulation circuit.Source: Table 10 · p. 68
• The comparison sets PT = PC because the T factory can be chosen to distill states of sufficient fidelity for the analysis.This assumption equates the T-state contribution with the circuit contribution in the logical-error estimate.Source: Table 10 · p. 68
• The surface-code comparison assumes two surface-code patches perform lattice surgery to inject a T state.Contributions from the T factory are neglected for surface codes, matching the treatment of the bicycle architecture.Source: §A.10 · p. 68
• Surface-code TFIM architectures comparable to gross-code error rate 2.09×10−5 use distance d = 7 at p ≤1.33×10−5 or d = 9 at p ≤5.48×10−5.These architectures are identified as having sufficient physical error rates comparable to the gross-code result.Source: §A.10 · p. 68
• Surface-code TFIM architectures comparable to two-gross error rate 7.32 × 10−4 use distance d = 17 at p ≤5.89 × 10−4 or d = 19 at p ≤7.85 × 10−4.These architectures are identified as having sufficient physical error rates comparable to the two-gross result.Source: §A.10 · p. 68