Shift-Left Techniques in Electronic Design Automation: A Survey

1 Introduction and Background

• Shift-Left emerged in software testing to find bugs sooner and avoid surprises from costly redesigns.Its general principle is to identify and mitigate risks early and iteratively.Source: §1 · p. 2
• The survey organizes EDA’s emerging Shift-Left movement and formalizes it as a research problem, identifying key metrics and challenges.It links scattered work along the design process and points to future opportunities.Source: §1 · p. 2
• EDA vendors have introduced Shift-Left updates as growing chip complexity and tighter task dependencies increase demands for design quality and engineering efficiency.EDA tools automate major design tasks to help meet performance, power, and area budgets.Source: §1 · p. 2

2 Related Survey

• Earlier work covered vendor design convergence, synthesis and macro placement, and potential in detailed routing.A recent perspective was written in Chinese and emphasized challenges more than progress.Source: §2 · p. 2
• The literature lacked a formal EDA Shift-Left definition, a progression overview, future directions, and methods to quantify effectiveness.The survey responds to dispersed research by integrating advancements along a typical design flow.Source: §2 · p. 2
• Unlike AI-for-EDA surveys centered on methods such as ML, GNNs, or LLMs, this survey classifies how Shift-Left is applied across prediction tasks and architectural studies.It covers classical and recent work and discusses open challenges and future directions.Source: §2 · p. 2

3 Shift-Left Techniques in EDA: An Overview

• Shift-Left focuses on task timing, unlike DTCO’s design–manufacturing co-optimization and HW/SW co-design or cross-layer design’s focus on integration.The survey primarily examines Shift-Left among these related design methodologies.Source: §3.1 · p. 3, Table 1 · p. 3

3.1 Formulate Shift-Left Problems in EDA

• Shift-Left asks how to detect and address issues earlier, minimizing late-correction effort and closure time without sacrificing PPA, reliability, or manufacturability.Late-correction cost includes the effort to fix violations and perform later-stage rework.Source: §3.1 · p. 3

3.2 Quantify Shift-Left in EDA

• The survey characterizes a shift by its start and end points, stages traversed, runtime overhead, and QoR gain; anchor points span early design to final signoff.Table 2 groups anchor points in the design flow, including ECO and tapeout.Source: §3.2 · pp. 3–4, Table 2 · p. 4

3.3 Shift Approaches

• The survey classifies Shift-Left approaches into Virtual Prototypes and Fused Actions.The categories derive from the authors’ survey of industry and academic practices.Source: §3.3 · p. 4

3.3.1 Virtual Prototypes (VPs)

• VPs predict downstream behavior or optimization targets for early guidance; accuracy limits their benefit, while ML, DL, and LLMs improve fidelity and RL uses prototypes as feedback.Prediction errors may lead to over- or under-optimization.Source: §3.3.1 · p. 4

3.3.2 Fused Actions (FAs)

• FAs move later stages earlier and integrate them with preceding steps, accelerating convergence and reducing runtime; shared databases support data exchange across tools.The survey identifies OpenROAD and METRICS 2.0 as examples.Source: §3.3.2 · pp. 4–5

3.3.3 Comparisons of Two Shift Approaches

• VPs offer early insight with minimal flow disruption but risk prediction error; FAs can improve runtime and integration while risking interoperability complexity and reduced modularity.The two strategies are presented as complementary alternatives to traditional divide-and-conquer design.Source: Table 3 · p. 5, §3.3.3 · p. 5

4.1 Pre-RTL Simulation Models

• Pre-RTL simulators use component-level parameters and interconnection specifications rather than RTL, gate, or transistor detail, trading modeling detail for faster, broader exploration.Processor models span cycle-accurate, event-driven, and functional granularity; specialized simulators address DRAM and accelerators.Source: §4.1 · pp. 5–6
• Performance models can be paired with trace-based power estimates, specialized memory and accelerator models, and integrated performance-and-power simulation.McPAT, CACTI, and Accelergy support early power estimation; Aladdin models both performance and power, while thermal tools and integrated toolchains extend metric coverage.Source: §4.1 · pp. 6–7

4.2 Software-defined Hardware (SDH)

• Software-defined hardware uses high-level abstractions, virtual prototypes, and parameterized architectures to support early functional verification, system prototyping, and HW/SW co-design.The approach allows software testing before hardware is available and helps hardware designers evaluate workload issues and functionality early.Source: §4.2 · p. 7

4.3 Workload Modeling

• Pre-RTL workload models range from running compiled programs to nested-loop representations that capture accelerator data mapping and parallelism.Direct program execution depends on compiler and simulator support; nested-loop abstractions are used by TimeLoop and ZigZag.Source: §4.3 · p. 7

4.4 DSE in Early Design Phase

• Early design-space exploration selects hardware components, workload mappings, or both, including choices for chiplet systems, memory hierarchies, and heterogeneous cores.Some tools automate component selection and workload mapping together.Source: §4.4 · p. 7

5.1 Shift-Left Prediction in HLS

• HLS predictors estimate area, latency, timing, power, and congestion from code, intermediate representations, reports, or execution traces using analytical and machine-learning approaches.Some methods predict post-layout timing from source code, while others trace post-route congestion hotspots back to source code.Source: §5.1 · pp. 7–8

5.2 Shift-Left Prediction in RTL

• RTL-level virtual predictors estimate PPA, timing, power, congestion, wirelength, and design-rule hotspots from RTL, circuit graphs, or netlists, with newer work using foundation models and LLMs.RTLRewriter uses multimodal analysis, retrieval-augmented generation, and cost-aware search to generate optimized RTL.Source: §5.2 · pp. 8–9

5.3 Physically-Aware Logic Synthesis

• Physically-aware synthesis fuses physical implementation with logic optimization, incorporating placement, physical constraints, or predictive timing slack into synthesis and resynthesis.Some hybrid flows use physical models to guide local synthesis; DDPAS uses an NLP-based model to predict post-routing timing slack within the synthesis search.Source: §5.3 · p. 9

5.4 Physically-Aware HLS

• Physically-aware HLS integrates floorplanning, placement, or macro placement into scheduling, allocation, and resource binding, or uses virtual models to guide those decisions.Fast placement and routing, net-delay prediction, and clock-skew estimation provide iterative physical feedback; initial placement can also inform congestion-aware HLS costs.Source: §5.4 · p. 9

6.1 Feedthrough-aware Floorplanning

• Feedthrough-aware floorplanning plans or reserves routes through hierarchical blocks to address timing and congestion risks before late-stage design changes.Methods include simulated-annealing cost models, whitespace reshaping, channel reservation, and explicit feedthrough insertion.Source: §6.1 · p. 10

6.2.1 VPs

• Virtual clock-tree models guide floorplan generation by estimating skew, latency, and power before detailed CTS.Some approaches study how clock outcomes relate to register count, aspect ratio, utilization, and CTS constraints, or estimate clock structures while planning power distribution.Source: §6.2 · p. 10, §6.2.1 · pp. 10–11

6.2.2 FAs

• Floorplanning methods that integrate CTS make clock-distribution decisions part of joint optimization of skew, latency, power, and physical placement.Reported clock-spine methods include 38% lower skew and 11% lower power than conventional CTS, and a 56% power saving versus industrial CTS.Source: §6.2.2 · p. 11

6.3 Power/Thermal-aware Floorplanning

• Power and thermal-aware floorplanning addresses rising power density and hotspots through thermal minimization, power-integrity planning, and early analysis.Work spans thermal placement and optimization for 2.5D/3D ICs, IR-drop-aware floorplanning, and industrial electrothermal co-simulation.Source: §6.3 · p. 11

6.4 EM/IR-aware Floorplanning

• EM/IR-aware floorplanning co-optimizes voltage drop, current density, and power-pad or TSV placement to address power integrity and reliability constraints.Methods include power-mesh sizing, network-flow formulations, local IR-drop fixes, decap allocation, and vertical current paths in 3D ICs.Source: §6.4 · p. 11

7 Shift-Left in Placement

• Placement quality affects downstream CTS and routing, and density can contribute to congestion and power, motivating early timing and congestion co-optimization.The placement problem is NP-hard, with state spaces that can become intractable.Source: §7 · p. 12

7.1.2 FAs

• Timing-driven placement addresses WNS and TNS while balancing wirelength, density, routability, and legality, using virtual metrics or fast STA within placement.Net-based methods fix timing weights before placement, while dynamic approaches update them iteratively; Figure 2 compares average WNS, TNS, HPWL, and runtime ratios across representative placers.Source: §7.1 · p. 12, §7.1.2 · p. 12, Figure 2 · p. 13

7.1.1 VPs

• Virtual placement methods use dataflow-aware macro placement and push-boundary operations to improve connectivity while limiting wirelength disruption.The review describes RTL connectivity and multi-hop interactions, and a KD-tree diagnosis that pushes poorly placed macros toward the boundary.Source: §7.1.1 · p. 12

7.2.1 Global Routability Driven Placement

• Global routability methods estimate and optimize congestion using overflow and edge-congestion objectives, routing-aware placement, density control, and hierarchy.Approaches include RUDY refinement, probabilistic routing models, placer-router coordination, pin-density constraints, and hierarchy-aware placement.Source: §7.2 · p. 13, §7.2.1 · p. 13

7.2.2 Detailed Routability Driven Placement

• Detailed-routability methods predict design-rule and congestion hotspots or embed detailed-routing constraints directly into placement optimization.Prediction approaches use CNNs, FCNs, and GNNs; optimization methods incorporate design rules, fence regions, blockages, and differentiable congestion functions.Source: §7.2.2 · pp. 13–14

7.3 Power-Aware Placement

• Power-aware placement co-optimizes clock-tree structure and cell placement to manage clock-network wirelength, buffers, capacitance, skew, and slew.The cited work uses multi-grid search or virtual clock-tree nodes and force-based optimization.Source: §7.3 · p. 14

7.4 Signoff-Aware Placement

• Sign-off-aware placement integrates sign-off DRC and fill checks into placement to reduce native-to-sign-off iterations and accelerate DRC convergence by 2–4×.Calibre RealTime Digital integrates Calibre sign-off DRC and SmartFill in the placement environment.Source: §7.4 · p. 14

8 Shift-Left in CTS

• Shift-Left CTS targets sub-ps skew and low slew and power under degradation while respecting congestion, reducing late timing or routing iterations.The section catalogs its seminal works in Table 8.Source: §8 · p. 14

8.1 Aging-Aware CTS

• Aging degrades transistors and interconnects, producing CTS skew, slew, and drive-strength problems; prediction models and voltage alignment address these effects.Clock-gating stress imbalance can also worsen asymmetric aging; increasing low-activity gate activity has a high power cost.Source: §8.1 · p. 15

8.2 Congestion-Aware CTS

• Clock nets consume substantial routing resources, so congestion evaluation moves into CTS; fishbone finger sharing, multi-bit flip-flops, and alternative interconnects are proposed to reduce demand.Source: §8.2 · p. 15

8.3 Power/Thermal-Aware CTS

• Power- and thermal-aware CTS addresses buffer-related IR-drop hotspots and thermal effects, with methods targeting self-heating, switching capacitance, aging, and thermal-gradient skew.Source: §8.3 · p. 15

8.4 On-Chip Variation (OCV)-Aware CTS

• OCV creates timing uncertainty from process non-uniformities; DME, path-level modifications, and cross-link insertion are studied to reduce skew or variation sensitivity.Source: §8.4 · p. 15

9 Shift-Left in Routing

• Routing trades off wirelength, congestion, crosstalk, and signal integrity; Shift-Left metrics such as wirelength, via count, and speed are embedded during routing, with AI/ML showing promise.Table 9 showcases highlighted works discussed in the section.Source: §9 · p. 15

9.1 ECO-Aware Routing

• ECO-aware routing iteratively refines paths under fixed area, layer, and utilization budgets, co-optimizing resource use, wirelength, clearance, pin access, timing, and IR-drop.Practical multi-requirement optimization often uses complex frameworks, while architecture-specific ECO routing is an emerging opportunity.Source: §9.1 · pp. 15–16

9.2 Power/Thermal-Aware Routing

• Power-aware routing lowers switching activity and buffer capacitance on fixed placements; approaches include virtual prediction, heuristics, buffer optimization, and consideration of operating scenarios or thermal effects.Source: §9.2 · p. 16

9.3 EM-Aware Routing

• EM constraints move from post-route signoff into routing, with methods operating at net, segment, or grid granularity and accounting for lifetime, parasitics, symmetry, and design rules.Source: §9.3 · p. 16

• Signoff approaches integrate learning-based prediction with ECO flows for cross-corner timing, power optimization, leakage, post-ECO IR-drop, and glitch-hotspot analysis.The section characterizes most signoff Shift-Left actions as GNN-based virtual prediction that accelerates analysis and interlocks with ECO actions.Source: §10 · p. 16

11 Shift-Left for Verification and Testing

• Verification and testing shifts DRC/LVS, DFT, and software validation from post-layout signoff to incremental checks during RTL-to-layout evolution.The stated aim is to catch SoC bugs when fixes are cheaper and avoid costly late-stage rework.Source: §11 · p. 17

11.1 Formal Verification

• Formal verification uses static mathematical analysis to prove or disprove certain design properties, whereas dynamic simulation can confirm behavior only for a finite set of test cases.Source: §11.1 · p. 17

11.2 Physical Verification

• Physical verification moves DRC, LVS, and DFM checks into incremental layout assembly, with commercial tools offering early checks and signoff-quality analysis.Examples include early block/IP LVS checks, embedded timing and power engines, and early signoff-quality DRC/LVS checks.Source: §11.2 · p. 17

12 Shift-Left Comparisons Among Different Stages

• Timing, power and routability are addressed across successive design phases through different techniques, as compared in Figure 3.The figure compares the three optimization concerns across the design flow.Source: §12 · p. 17, Figure 3 · p. 18
• Timing models become more explicit as design advances, while effective timing optimization concentrates in placement, CTS and routing.RTL delay prediction can guide floorplanning; later stages use STA, critical-path identification and RC-tree models alongside stage-specific optimization.Source: §12 · p. 19
• Power and thermal modeling progresses from analytical estimates and ML-based power prediction to hotspot and clock-tree models, followed by design-space and implementation optimizations.The described techniques include parameter selection, clock gating, simulated annealing, gradient-based optimization, buffer insertion and hybrid routing.Source: §12 · p. 19
• Routability methods span GNN-based hotspot detection and routing-demand estimates through RTL logic optimization, placement cell inflation and CTS fishbone routing.The passage also describes logic optimization between single-bit and multi-bit flip-flops.Source: §12 · p. 19
• Future Shift-Left challenges include improving model accuracy, algorithmic efficiency and generalizability, integrating AI more effectively, and adapting to sustainability requirements.These are presented as potential future challenges as technology evolves.Source: §12 · p. 19

13 Conclusions

• The survey organizes Shift-Left techniques by EDA design phase and outlines potential future directions and challenges.It presents detailed methodology for the different phases of the EDA flow.Source: §13 · p. 19
• The study offers practical guidance for future systematic investigations and maintains a GitHub repository for tracking recent Shift-Left research.The authors state that this work ultimately contributes to enhanced chip-design efficiency across the industry.Source: §13 · p. 19