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EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization

Wei-Po Hsin, Ren-Hao Deng, Yao-Ting Hsieh, En-Ming Huang, Shih-Hao Hung

arXiv:2601.18067v1cs.AIcs.NEcs.PL

TL;DR

Verilog design is labor-intensive, while LLMs lack sufficient domain data and struggle with hardware concurrency and formal logic. EvolVE applies evolutionary search with IGR, MCTS, and STG, and evaluates optimization on IC-RTL. It achieves state-of-the-art functional-generation results and reduces PPA substantially on complex benchmark problems.

  • Problem

    LLMs face limited domain-specific data and sequential reasoning that does not match Verilog’s concurrent hardware requirements, while existing benchmarks inadequately assess complex PPA optimization.

  • Method

    EvolVE uses model-agnostic evolutionary search with IGR and MCTS, STG for fine-grained verification feedback, and IC-RTL for industry-scale PPA evaluation.

  • Results

    98.1% on VerilogEval v2, 92% on RTLLM v2, and up to 66% PPA-product reduction on IC-RTL establish strong functional and optimization performance.

  • Takeaways & Limitations

    MCTS is superior for functional generation, IGR for PPA optimization, and STG accelerates convergence by replacing coarse feedback with fine-grained scores.

  • Takeaways & Limitations

    STG requires executable golden reference models, while automated synthesis flows for real-time PPA feedback and complex PPA benchmarks remain underdeveloped.

Abstract

from arXiv · show

Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation, their limited training data and intrinsic sequential reasoning fail to capture the strict formal logic and concurrency inherent in hardware systems. To overcome these barriers, we present EvolVE, the first framework to analyze multiple evolution strategies on chip design tasks, revealing that Monte Carlo Tree Search (MCTS) excels at maximizing functional correctness, while Idea-Guided Refinement (IGR) proves superior for optimization. We further leverage Structured Testbench Generation (STG) to accelerate the evolutionary process. To address the lack of complex optimization benchmarks, we introduce IC-RTL, targeting industry-scale problems derived from the National Integrated Circuit Contest. Evaluations establish EvolVE as the new state-of-the-art, achieving 98.1% on VerilogEval v2 and 92% on RTLLM v2. Furthermore, on the industry-scale IC-RTL suite, our framework surpasses reference implementations authored by contest participants, reducing the Power, Performance, Area (PPA) product by up to 66% in Huffman Coding and 17% in the geometric mean across all problems. The source code of the IC-RTL benchmark is available at https://github.com/weiber2002/ICRTL.

1 Introduction

EvolVE addresses the mismatch between sequential LLM reasoning and concurrent Verilog design through evolutionary search and structured verification. It reports strong functional-generation results and introduces IC-RTL for more rigorous PPA evaluation.

  • Manual Verilog development is labor-intensive, motivating LLM-based automation for hardware design and verification.
  • LLMs struggle with Verilog because sequential reasoning does not align with highly concurrent, clock-synchronized hardware systems.
  • Existing benchmarks have evaluation weaknesses, including inconsistent specifications, limited complexity, sparse stimulus coverage, and binary feedback.
  • EvolVE uses IGR and MCTS to explore Verilog designs and debugging without fine-tuning or massive domain-specific datasets.
  • 98.1% on VerilogEval v2 and 92% on RTLLM v2 demonstrate strong functional-generation performance with DeepSeek-R1-FP4.
  • IC-RTL evaluates complex PPA optimization, while STG accelerates evolution through automated signal categorization and high-coverage feedback.

2 Background and Motivation

Prior work addresses Verilog generation through fine-tuning and agentic search, but existing benchmarks remain small, function-focused, and insufficient for complex PPA optimization. EvolVE responds by treating HDL generation as iterative state-space exploration using test-time compute.

  • Evolutionary coding agents use closed-loop reasoning, implementation, execution feedback, and refinement rather than static prompting.
  • LLM hardware-design research has split between domain-specific fine-tuning and agentic or structural guidance.
  • Agentic frameworks include local optimization, collaborative multi-agent decomposition, and workflow-level evolutionary search.
  • Existing PPA optimization benchmarks mainly contain small modules that standard synthesis tools can optimize without deep domain knowledge.
  • Current benchmarks often have fewer than 100 samples, emphasize basic modules, omit PPA, and restrict architectural exploration through single-turn generation.
  • EvolVE shifts from learning-centric modeling to evolutionary state-space exploration, using test-time compute for iterative self-correction.

3 Methodology

EvolVE formulates Verilog development as evolutionary search, using IGR and MCTS to iteratively generate, evaluate, and refine candidate designs. Its evaluator combines functional or PPA objectives with structured feedback, while STG supplies dense correctness signals to guide search.

  • Evolutionary Search Strategies: EvolVE uses IGR and MCTS as complementary strategies for exploring and refining Verilog designs.IGR separates architectural idea generation from sequential refinement, whereas MCTS organizes candidates in a search tree.
  • Problem Formulation: Each search node stores Verilog code, a quantitative score, and diagnostic feedback generated by testbench evaluation.The framework iteratively generates nodes with an LLM and seeks an optimal design.
  • Task Objectives: Generative synthesis scores candidates by test-case pass rate, assigning Cpenalty to compilation or simulation failures.The objective for generative tasks is strictly functional correctness.
  • Task Objectives: PPA optimization scores valid designs using a normalized Area A(Vi) and Latency L(Vi) product while maintaining functional integrity.The formulation targets minimization of Power, Performance, and Area metrics through a constrained maximization objective.
  • Search Loop: The unified loop selects a parent, generates child code from code and feedback, evaluates it, and expands or backpropagates search statistics.MCTS selects nodes with a UCT-based score, prioritizing unexplored children; IGR uses independent idea-conditioned refinement chains.
  • Structured Testbench Generation: STG classifies DUT signals and produces temporally aligned test cases with a continuous pass-rate score Pstg ∈[0, 1].This fine-grained functional gradient distinguishes partially correct candidates and transfers iterative-debugging cost to EDA simulation tools.

4 Experiments

EvolVE improves functional Verilog generation through inference-time search and supports substantial PPA optimization on the industry-scale IC-RTL benchmark. MCTS scales with computational budget and STG accelerates convergence, while evolutionary search discovers both local refinements and architectural changes.

  • Verilog Code Generation: 92.0% on RTLLM v2 and 98.1% on VerilogEval v2 are achieved by DeepSeek-R1-FP4-MCTS at 300 computational nodes.At 15 nodes, the same configuration reaches 94.2% on VerilogEval v2.
  • Verilog Code Generation: MCTS performance continues improving with node count, while Siliconmind-7B-MCTS rises from 85.3% at 15 nodes to 92.9% at 300 nodes.DeepSeek-R1-FP4 resolves 84.6% of problems at the first node and averages 2.49 nodes per solution.
  • Verilog Code Generation: STG reduces DeepSeek-R1-FP4’s average nodes on Mod-VerilogEval v2 from 4.78 to 2.49 and lowers output tokens from 38,818 to 15,440.The STG-enhanced configuration maintains comparable performance at the 300-node budget while improving convergence efficiency.
  • PPA Optimization: IC-RTL evaluates EvolVE on hand-crafted and National IC Design Contest-derived tasks requiring algorithmic structures, memory optimization, and PPA optimization.The suite is designed for compatibility with commercial and open-source platforms and provides substantial design space for optimization.
  • PPA Optimization: 12% lower Latency on GEMM is obtained with neutral Area and lower Power by rescheduling systolic-array control logic.The reported mechanism is increased data reuse and fewer pipeline bubbles without hardware overhead.
  • PPA Optimization: 36% composite PPA improvement on Job Assignment Machine combines 31% lower Area and 26% lower Power without sacrificing latency.The optimization prioritizes Area efficiency while also improving energy efficiency.
  • PPA Optimization: 66% PPA improvement is achieved on Huffman Coding through simultaneous Area and Power reductions of 30% and 25%.The result is attributed to restructuring irregular decision-tree and sorting-network control flow.
  • PPA Optimization: EvolVE navigates PPA trade-offs by generating area- or latency-focused variants and by evolving a systolic design from output-stationary to weight-output-stationary hybrid architecture.The hybrid architecture reduces latency from 1280ns to 776ns, while the broader search supports distinct constraint-aware implementation trajectories.

5 Conclusion

EvolVE unifies evolutionary search strategies, structured feedback, and benchmark improvements to generate and optimize Verilog across functional and PPA objectives. Experiments report state-of-the-art results, while the authors identify dependencies on executable reference models and limited PPA benchmarks.

  • 5 Conclusion: EvolVE combines IGR and MCTS in a model-agnostic evolutionary framework for specification-to-RTL generation and PPA optimization.The framework supports functionally correct Verilog generation and targeted optimization without fine-tuning.
  • 5 Conclusion: STG replaces coarse binary feedback with fine-grained scores, accelerating convergence on complex logic problems.The engine is presented as enabling evolutionary search beyond baseline-model saturation.
  • 5 Conclusion: IC-RTL bridges academic benchmarks and industry-level complexity by providing a platform for evaluating design optimization capabilities.The benchmark complements EvolVE’s functional-generation evaluations with complex optimization tasks.
  • 5 Conclusion: 98.1% pass rate is achieved with limited evaluation budgets, while PPA product reductions reach 66% on Q5 and 17% in the IC-RTL geometric mean.The experiments span VerilogEval v2, Mod-VerilogEval v2, RTLLM v2, and IC-RTL.
  • 5 Conclusion: STG currently requires executable C or Verilog reference models, and automated synthesis flows for real-time PPA feedback remain under development.The authors also note that dedicated PPA-optimization benchmarks remain scarce.
  • 5 Conclusion: Future work targets a microarchitectural optimization playbook and broader use of MCTS for power, performance, and area optimization.The stated goal is to extend MCTS beyond functional correctness alone.

A Detailed Evolutionary Framework

EvolVE represents evolutionary search as a unified loop over candidate Verilog nodes, using either IGR or MCTS to select parents and an LLM to generate children. Each node carries code, an STG-derived score, and diagnostic feedback.

  • A Detailed Evolutionary Framework: The evolutionary process unifies IGR and MCTS under a single optimization loop.The two strategies differ in parent selection within the shared framework.
  • A Detailed Evolutionary Framework: Each search node N = (V, S, F) contains Verilog code, a quantitative STG score, and diagnostic feedback.These fields represent the candidate solution and its evaluation information.
  • A Detailed Evolutionary Framework: The algorithm takes a problem description D and testbench T as input and returns an optimized node N ∗.The evaluation function, LLM, and maximum node budget are parameters.
  • A Detailed Evolutionary Framework: The loop initializes seed code and a best-solution archive before selecting a parent node through IGR or MCTS.Search continues while the success score is below 1.0 or the task is optimization, subject to the node limit.
  • A Detailed Evolutionary Framework: Child generation constructs an LLM prompt from the problem description, parent code, score, and feedback, then produces child Verilog.This couples evolutionary selection with feedback-guided code generation.

B Benchmark Improvements

The benchmark revision addresses correctness and usability problems in VerilogEval v2, while IC-RTL-related evaluation context emphasizes more rigorous hardware-design assessment. Modifications target reference designs, specifications, interfaces, and naming consistency.

  • B Benchmark Improvements: Mod-VerilogEval v2 uses the 156-problem VerilogEval v2 benchmark’s specification-to-RTL subset.VerilogEval v2 evaluates hardware design capabilities through specification-to-RTL tasks.
  • B Benchmark Improvements: The original dataset contained inaccurate descriptions, unsynthesizable syntax, and logically inconsistent reference models that could penalize correct designs.These flaws hindered effective evolutionary optimization.
  • B Benchmark Improvements: Reference designs were revised by removing non-synthesizable initial blocks and adding explicit reset handling.The corresponding problem prompts were updated for proper register initialization.
  • B Benchmark Improvements: Several modules were rewritten to correct unsynthesizable high-impedance or undefined outputs.The revisions aimed to comply with standard synthesizable Verilog.
  • B Benchmark Improvements: FSM descriptions and complex interfaces were refined to clarify state transitions and port declarations.Extraneous information was removed from affected problems.
  • B Benchmark Improvements: Naming standardization corrected port mappings and top-module naming issues to ensure uniform testing.Examples include corrections in Problems 99 and 130.

C Siliconmind 7b Model

Siliconmind-7B is a lightweight, open-source 7-billion-parameter student model for generating functionally correct and PPA-optimized Verilog from natural-language specifications. Its training uses teacher-filtered data augmentation followed by SFT and GRPO.

  • C Siliconmind 7b Model: Siliconmind-7B is a lightweight, open-source 7-billion-parameter model at the core of an end-to-end Verilog-generation system.The system targets functionally correct and PPA-optimized modules from natural-language specifications.
  • C Siliconmind 7b Model: A larger DeepSeek-R1 teacher model filters and expands public datasets into samples containing problems, reasoning, code, and testbenches.This data augmentation supplies training examples for the student model.
  • C Siliconmind 7b Model: Siliconmind-7B is enhanced through Supervised Fine-Tuning and GRPO using the augmented data.The training objective is to learn advanced Verilog design capabilities under limited on-site computational resources.

D IC-RTL Detailed Results

This section presents detailed performance metrics for the IC-RTL benchmark. Results are organized across six tables, arranged in parallel for space efficiency.

  • The section reports detailed performance metrics for the IC-RTL benchmark.
  • The tables are arranged in parallel to maximize space efficiency.
  • Six tables cover Q1_LBP, Q2_GEMM, Q3_CONV, Q4_JAM, Q5_HC, and Q6_DT results.
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