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Computing with many encoded logical qubits beyond break-even

Shival Dasu, Matthew DeCross, Andrew Y. Guo, Ali Lavasani, Jan Behrends, Asmae Benhemou, Yi-Hsiang Chen, Karl Mayer, Chris N. Self, Selwyn Simsek, Basudha Srivastava, M. S. Allman, Jake Arkinstall, Justin G. Bohnet, Nathaniel Q. Burdick, J. P. Campora, Alex Chernoguzov, Samuel F. Cooper, Robert D. Delaney, Joan M. Dreiling, Brian Estey, Caroline Figgatt, Cameron Foltz, John P. Gaebler, Alex Hall, Craig A. Holliman, Ali A. Husain, Akhil Isanaka, Colin J. Kennedy, Yuga Kodama, Nikhil Kotibhaskar, Nathan K. Lysne, Ivaylo S. Madjarov, Michael Mills, Alistair R. Milne, Brian Neyenhuis, Annie J. Park, Anthony Ransford, Adam P. Reed, Steven J. Sanders, Charles H. Baldwin, David Hayes, Ben Criger, Andrew C. Potter, David Amaro

arXiv:2602.22211v1quant-ph

TL;DR

The paper addresses how to prepare and operate high-rate encoded states while controlling faults and postselection across increasingly general logical tasks. It develops fault-tolerant preparation and encoded-operation techniques, reports break-even behavior in quantum-simulation configurations, and shows analytically consistent QEC-cycle scaling and constant-overhead gate extensions.

  • Problem

    Preparing resource states and entangled logical states for high-rate QEC is important because they support error correction, long-range interactions, non-Clifford gates, and addressability.

  • Method

    The paper develops alternative fault-tolerant resource-state preparation methods, analyzes bipartite CSS-state circuits, and introduces constant-overhead extensions of the FANOUT gate.

  • Results

    The first two XY-model configurations demonstrated break-even performance across the studied Trotter-step range, while the selected midpoint-SE configuration improved acceptance rate by approximately a factor of two over the first configuration.

  • Takeaways & Limitations

    Concatenation and tailored encoded-operation gadgets provide routes to controlling rejection rates and extending fault-tolerant operations as code blocks grow.

Abstract

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High-rate quantum error correcting (QEC) codes encode many logical qubits in a given number of physical qubits, making them promising candidates for quantum computation. Implementing high-rate codes at a scale that both frustrates classical computing and improves performance by encoding requires both high fidelity gates and long-range qubit connectivity -- both of which are offered by trapped-ion quantum computers. Here, we demonstrate computations that outperform their unencoded counterparts in the high-rate $[[ k+2,\, k,\, 2 ]]$ iceberg quantum error detecting (QED) and $[[ (k_2 + 2)(k_1 + 2),\, k_2k_1,\, 4 ]]$ two-level concatenated iceberg QEC codes, using the 98-qubit Quantinuum Helios trapped-ion quantum processor. Utilizing new gadgets for encoded operations, we realize this "beyond break-even" performance with reasonable postselection rates across a range of fault-tolerant (FT) and partially-fault-tolerant (pFT) component and application benchmarks with between $48$ and $94$ logical qubits. These benchmarks include FT state preparation and measurement, QEC cycle benchmarking, logical gate benchmarking, GHZ state preparation, and a pFT quantum simulation of the three-dimensional $XY$ model of quantum magnetism. Additionally, we illustrate that postselection rates can be suppressed by increasing the code distance via concatenation. Our results represent state-of-the-art logical component and state fidelities and provide evidence that high-rate QED/QEC codes are viable on contemporary quantum computers for near-term beyond-classical-scale computation.

A. Hardware specifications

Helios is a 98-qubit trapped-ion processor with QCCD-based transport and long-range operation capabilities. Its hardware supports software-defined one-qubit gates, Mølmer–Sørensen two-qubit gates, and protected batch measurements.

  • Processor architecture: 98 qubits: Helios uses 137Ba+ hyperfine qubits in a QCCD architecture with transport through a ring, X-junction, cache region, and two operational legs.The architecture physically transports ions for cooling, logic operations, and temporary storage.
  • Quantum operations: Arbitrary one-qubit gates are decomposed into U1Q(θ, ϕ) operations implemented as software phase updates.
  • Quantum operations: The two-qubit gate uses a phase-insensitive Mølmer–Sørensen interaction with user-specified angle θ.The gate error scales linearly with angle up to the maximal entangler θ = π/2.
  • Measurement: Protected batch measurements reduce crosstalk, while ternary-valued measurement provides an additional measurement mode.
  • Hardware benchmarks: 4.8(6) × 10^-4: standard-measurement SPAM error per qubit; 8(2) × 10^-4: 2Q gate error at the maximum gate angle.Full-circuit effective 2Q gate infidelity includes memory and other circuit overheads.

B. QEC benchmarking

The QEC benchmarking analysis models repeated logical-memory operations with stochastic Pauli channels and estimates cycle infidelities from survival-probability fits. Comparisons use cycle rejection rates and a physical linear-memory baseline, with leakage-heralded postselection in the reported experiments.

  • Channel model: Repeated QEC/QED operations are modeled as stochastic logical Pauli channels, with single-qubit reduced channels used for k = 4 experiments.Repeated Pauli errors can cancel, so the analysis marginalizes over all but one logical qubit.
  • Infidelity estimation: Survival probabilities after c QEC rounds are fitted to estimate logical error probabilities and QEC-cycle infidelity per logical qubit.Maximum-likelihood fitting and Markov Chain Monte Carlo sampling provide estimates and uncertainties.
  • Comparison baseline: 1.1(3) × 10^-4: non-leakage component of the depth-1 linear memory error used as the physical comparison baseline.The baseline is obtained from transport-1QRB benchmarking data.
  • Acceptance analysis: QEC/QED cycle rejection rates are fitted to (1 − r)^c across c ∈ {1, 2, 4, 8} cycles.The reported fits distinguish rejection behavior across d = 2 and d = 4 experiments and measurement bases.
  • Leakage handling: Leakage-heralded measurement is used to postselect leakage because leakage can violate fault tolerance without additional gadgets.Leakage repumping is identified as an alternative that converts leakage into depolarizing noise.

C. Logical gate benchmarking

Logical gate benchmarking combines Pauli-twirled cycles, randomized eigenstate preparation, and exponential decay fits to estimate logical fidelities. The section also describes GHZ preparation across iceberg blocks, including repeated ancilla measurements and postselection for fault tolerance.

  • Logical gate benchmarking: Logical cycle benchmarking samples random logical Pauli strings and initializes corresponding logical eigenstates, using length-8 strings for inter-block I4 gates.The longer strings reflect fault propagation across both code blocks through nonlocal syndrome-extraction gadgets.
  • Logical gate benchmarking: Pauli twirling converts the aggregate logical-gate error channel into a stochastic Pauli channel whose fidelities are estimated from exponential expectation-value decay.Maximum-likelihood fits yield Pauli fidelities that are averaged into process fidelity.
  • Logical gate benchmarking: F_avg = (4F_pro + 1)/5 converts process fidelity to gate-averaged fidelity for a single logical 2Q gate per cycle.The resulting fidelities are reported with 1σ confidence intervals.
  • Logical GHZ preparation: Logical GHZ states across multiple I4 blocks are extended using a logical FANOUT gate that maps |GHZ_k1⟩⊗|0⟩⊗k2 to |GHZ_k1+k2⟩.The protocol begins with one prepared code block and proceeds analogously to tree-based GHZ preparation.
  • Logical GHZ preparation: Both detailed GHZ preparation protocols are fully fault tolerant to single weight-2 faults, despite many iceberg-code applications using partially fault-tolerant gates.
  • Logical GHZ preparation: Two repeated ancilla-mediated measurements protect GHZ preparation against measurement errors, and postselection on differing measurements prepares logical error rate O(p^3) with probability O(p^2).The stated scaling applies when a single error is corrected during preparation and two-fault discrepancies are postselected.

I: State preparation and error mitigation techniques

Iceberg logical-zero states are prepared with branching CX trees whose branch-parity checks detect faults, while concatenated codes extend the same strategy to logical blocks. Repeat-until-success, dynamical decoupling, and DFS-inspired pulses mitigate detected errors and coherent memory errors.

  • State preparation: The logical zero state |0⟩^k = |GHZ_k⟩ is prepared from |+⟩ and |0⟩ inputs using a CX tree with up to n/2 branches and log-depth execution.Branch pairs are coupled to ancillas that measure ZZ operators, requiring up to n/4 ancillas and n/2 additional CX gates.
  • Fault tolerance: Single faults in the two-branch gadget are detectable or act only as code stabilizers, establishing fault-tolerant state preparation.Errors can flip branch ZZ checks, propagate in constrained ways, or reduce to stabilizer operations.
  • Fault tolerance: A balanced log-depth tree pairs terminal nodes across branches so measured ZZ operators retain fault-detection coverage.The construction balances descendants of q1 and the complementary branch, allowing at most one leftover node in the stated procedure.
  • Error handling: Detected errors trigger reset and reinitialization through a repeat-until-success protocol rather than simple postselection.The protocol aggregates iteration statistics across SPAM, GHZ preparation, and XY-model experiments.
  • Error mitigation: Log-depth preparation leaves qubits idling, creating a risk of coherent dephasing that can grow quadratically at short idle times.Additional mitigation is therefore applied specifically to the log-depth gadget.
  • Error mitigation: DFS-inspired Pauli-X insertions create equal mixtures of computational-basis states during tree layers, reducing sensitivity to spatially uniform coherent memory errors.The net effect can be accounted for by flipping relevant bits in postprocessing, with a stated code-space adjustment for certain n values.
  • Concatenated preparation: The concatenated-code gadget initializes lower-level blocks and uses transversal CX operations with a logical ancilla to measure logical ZZ operators.Additional syndrome gadgets catch cascading logical X errors and constrain weight-two faults.

II: Data from SPAM experiments

The distance-4 concatenated iceberg SPAM experiment combines substantial leakage and preparation acceptance with very low logical error. Across 4000 shots, no logical errors were observed after acceptance.

  • Acceptance and fidelity: 0.654(8) was the pre-acceptance rate, while 0.987(2) was the post-acceptance rate.The two rates distinguish passing state preparation from passing the remaining postselection stage.
  • Acceptance and fidelity: 8.3 × 10^-6 was the upper bound on SPAM infidelity per logical qubit after 4000 shots with no recorded logical errors.The bound uses a Wilson 68% confidence interval.

III: GHZ-state based syndrome extraction and readout in Ik codes

GHZ-state ancillas parallelize syndrome extraction and support specialized readout gadgets for iceberg codes. The designs trade larger ancilla states and greater parallelism against transport, encoding, and coherent-idling costs, while concatenated codes combine high- and low-level syndrome checks.

  • Syndrome extraction: Standard distance-2 syndrome gadgets use ancillas as mutual flags, but surplus hardware permits separate flag qubits and greater gate parallelization.Assigning a dedicated flag to each ancilla allows twice as many gates to run in parallel.
  • Syndrome extraction: Four-qubit GHZ ancillas broadcast syndrome-extraction gates across qubits, with one qubit recording the syndrome and others flagging hook errors.X-basis GHZ states detect X errors through SZ, while Z-basis GHZ states detect Z errors through SX.
  • Syndrome extraction: Larger GHZ ancillas may require additional transport rounds and increase encoding, decoding, and coherent-dephasing sensitivity.The device is already fully parallelized when eight gates run simultaneously, motivating a near-optimal intermediate GHZ size on Helios.
  • Readout: Readout reconstructs SZ destructively in the Z basis and extracts SX non-destructively with a four-qubit Z-basis GHZ state.The paper cautions that end-of-circuit SX extraction can introduce coherent idling errors in the Z basis.
  • Readout: Leakage-heralded measurement slightly increases logical error and discard rates in short circuits because it carries larger physical SPAM error.The same measurement substantially improves the results for the larger GHZ experiments.
  • Readout: In I94 GHZ preparation, limited qubits prevent simultaneous use of log-depth initialization and GHZ-based readout, so two-branch initialization and a one-ancilla readout are used.The readout gadget further improves on the cited prior gadget while requiring only one ancilla.
  • Concatenated QEC: Concatenated-code QEC combines high-level stabilizer extraction through an encoded ancilla with low-level Bell-pair syndrome extraction.The cycle repeats the structure in the conjugate basis to extract both X- and Z-type high- and low-level syndromes.
  • Concatenated QEC: Generalized weight-two error strings are identified through multiple coordinate values and distinguished from correctable errors using the syndrome structure.Their support intersects any weight-four logical operator on at most two vertices.

EDZ EDX

The two-level concatenated iceberg QEC cycle is analyzed through generalized-weight fault conditions, ExRec criteria, and experimental acceptance measurements. The analysis establishes when computations correct errors, halt safely, or avoid undetectable logical errors.

  • ExRec fault conditions: At most one fault per ExRec suffices for successful d = 3 computation, whereas at most two faults for d = 4 guarantee success or halting without an undetectable logical error.An ExRec is defined as two consecutive QEC cycles; the d = 4 condition permits more general output errors but prevents undetectable logical failure.
  • QEC-cycle properties: The QEC cycle corrects generalized weight-1 inputs without faults, while generalized weight-2 inputs cause the computation to halt.With one internal fault, fault-free inputs produce at most generalized weight-1 output, while weight-1 inputs remain correctable or trigger a later halt.
  • Fault analysis: Two internal faults produce at most generalized weight-2 output or halt the computation, supporting the d = 4 ExRec analysis.The proof treats X and Z errors analogously and uses flags and subsequent syndrome extraction to identify hazardous fault patterns.
  • Scaling: The I2 ◦I2 QEC-cycle simulation exhibits O(p^3) infidelity and O(p^2) rejection-rate scaling, matching fitted numerical slopes.These scalings follow from the stated proposition for the circuit-level QEC cycle.
  • Experiments: The experiments use 1, 2, 4, and 8 QEC or QED cycles, with leakage, preacceptance, and QEC/QED acceptance rates recorded for four-logical-qubit memories.For the I8 ◦I6 experiment, 708 X-basis and 958 Z-basis shots were accepted, with no errors observed among accepted shots.

V: Logical gate benchmarking analysis and statistical procedure

Logical cycle benchmarking samples Pauli observables across randomized, syndrome-extracted circuits and fits their expectation-value decays to estimate logical process and gate fidelities. The analysis also reports acceptance rates and bootstrap uncertainties for intra- and inter-block experiments.

  • Protocol: Cycle benchmarking samples logical Pauli observables, initializes matching random eigenstates, applies Pauli-twirled gates with periodic syndrome extraction, and measures final parities.Experiments use 20 sampled observables across four or eight logical qubits, depending on whether gates are intra- or inter-block.
  • Statistical model: Accepted-shot parity outcomes are modeled as Bernoulli trials, with match probabilities related to Pauli expectation values by µP(L) = 2qP(L) − 1.For each Pauli and cycle depth, the analysis records accepted shots and match counts before fitting the decay model.
  • Fitting: The expectation value of each Pauli is fit to an exponential decay across cycle depth, yielding a separate fitted Pauli fidelity fP and SPAM amplitude AP.Maximum-likelihood fits impose constraints ensuring valid binomial probabilities at every fitted depth.
  • Fidelity extraction: Cycle process fidelity is converted to a two-qubit process fidelity as Fpro,2Q = (Fpro)^(1/n), then to average fidelity as Favg = (4Fpro,2Q + 1)/5.Here n = 1 for inter-block gates and n = 2 for intra-block UZZ(π/2); acceptance rates are reported separately.
  • Uncertainty analysis: Gate-average-fidelity uncertainties use 500 bootstrap resamples of binomial outcomes and fitted expectation-value decays, reported with 68% intervals.The corresponding logical cycle-benchmarking results are summarized in the gate-fidelity and acceptance-rate tables.

VI: Partially fault-tolerant gates between Ik code blocks

The paper develops partially fault-tolerant inter-block gates for iceberg codes by relocating non-fault-tolerant rotations across code blocks and introducing a constant-overhead FANOUT construction. These gadgets trade complete fault tolerance for practical encoded connectivity, while their benefits depend on the device’s error model.

  • Inter-block rotations: Logical UZZ and UXX rotations become four-body operations between disjoint iceberg blocks, motivating CX-based decompositions with SWAP gates.Within one block, paired endpoint operators cancel; across blocks, the corresponding operators do not cancel.
  • pFT gate gadgets: The SWAP-rewritten UZZ and UXX gadgets make the non-fault-tolerant rotation span both blocks, leaving only ZZ errors undetectable on the physical UZZ gate.The original gadget detects any single Pauli error on its CX gates but remains vulnerable to weight-2 errors on the rotation.
  • Device dependence: On Helios, weight-2 gate errors are essentially ZZ-type, so the rewritten gadgets may not substantially improve practical fault tolerance there.The construction may be more useful on devices with different Pauli error models.
  • FANOUT: The FANOUT gate is fully fault tolerant against all single weight-2 gate errors and distributes inter-block entanglement with four gates independent of code-block size.Its entanglement pattern aligns with efficient logical GHZ-state preparation.
  • Extensions: Constant-overhead FANOUT extensions can control on or target selected subsets of qubits through modified CX-gate choices.The paper identifies these extensions as possible constructions rather than providing them in detail.

VIII: Logical GHZ state preparation in d = 2 iceberg codes

The section develops fault-tolerant preparation and measurement procedures for logical GHZ states in iceberg codes, including the 48-logical-qubit d = 4 concatenated case. The experiments and simulations evaluate fidelity, acceptance, and error-scaling behavior.

  • State preparation: A global logical GHZ state is prepared by independently generating a Bell pair on q0 and qn−1 and a physical GHZ state on the remaining qubits.The construction has log-depth and is fault-tolerant because undetectable weight-2 CX errors stabilize the Bell pair.
  • Measurement and estimation: Fault-tolerant GHZ fidelity estimation repeats nondestructive logical measurements, discards parity-inconsistent shots, and postselects on required stabilizer outcomes.The protocol measures logical X and Z stabilizers while correcting single errors across the full circuit volume.
  • State preparation: The 48-logical-qubit GHZ state in I8 ◦ I6 is completed by fault-tolerantly measuring a global logical X operator and applying a virtual Pauli-frame correction when needed.An I8 GHZ ancilla is used to measure the corresponding I8 ◦ I6 operator.
  • Fault tolerance: Non-fault-tolerant coupling of an I6 GHZ ancilla can spread a single X error into an undetectable weight-2 data error, motivating extraction of the ancilla’s Z stabilizers.The stabilizer measurements locate single-qubit X errors and convert generalized weight-two errors into generalized weight-one errors.
  • Experimental results: In the d = 4 GHZ experiment, 790 accepted X-basis shots and 1233 accepted Z-basis shots contained no errors.Each basis received 4000 submitted shots, with leakage and overall acceptance rates reported separately.

X: Data from preliminary XY model experiments in the I50 code

Preliminary I50 experiments compared syndrome-extraction configurations for encoded XY-model simulation. Two configurations reached break-even performance, and the selected midpoint configuration improved acceptance by approximately a factor of two.

  • Experimental setup: The I50 study used a 2 × 5 × 5 periodic lattice and assessed fidelity and acceptance as functions of total Trotter steps.The lattice geometry and benchmarking quantities are shown in the supplementary figure and tables.
  • Configuration comparison: Two of three I50 syndrome-extraction configurations demonstrated break-even performance across the studied Trotter-step range.The third performed similarly for s = 2 to s = 6 but showed no clear fidelity improvement at s = 8 and s = 10.
  • Configuration comparison: The midpoint syndrome-extraction configuration was selected for I64 experiments because it preserved similar performance while improving acceptance by approximately a factor of two.The comparison was against the configuration combining SX extraction with midpoint syndrome extraction.

XI: Data from I64 XY model experiments

The I64 XY-model experiments quantify encoded simulation fidelity, acceptance, and effective two-qubit gate errors over circuit depth. The analysis treats exponential survival fits as an empirical metric while noting their theoretical limitations.

  • Gate-error analysis: The survival probability is empirically well modeled by exponential decay, although logical errors need not arise from independent gate errors.The extracted ˜ϵ2Q is treated as an informative effective-gate-error metric rather than a theoretically exact decay parameter.
  • Acceptance behavior: At the deepest I64 circuits, acceptance approaches a plateau around 12.5%.The plateau is discussed in connection with multiple faults and effectively random syndromes.
  • Gate-error analysis: Effective average two-qubit gate fidelities are obtained by fitting survival probability as a function of the number of logical two-qubit gates.The fitted model uses parameters A and ˜ϵ2Q.
  • Measurement caveat: Leakage acceptance rates are computed only from shots that survive midcircuit postselection and reach terminal measurement.Early-terminated shots lack data-qubit leakage information and are excluded from those rates.
  • Experimental results: I64 experiments report fidelity, shot counts, leakage acceptance, and overall acceptance across five total-Trotter-step settings.The corresponding tables distinguish leakage-heralded measurement from other experimental conditions.

XII: Alternative fault-tolerant preparation of resource states

The section compares several fault-tolerant preparation methods for logical resource states, evaluating logical errors and discard rates across state types and measurement bases. The methods trade computational cost, generality, logical-error performance, and pre-discard behavior.

  • Benchmarks: Three logical resource-state families are benchmarked: |¯0⟩⊗48, random products of |¯0⟩ and |¯+⟩, and random CSS states.The benchmarks report logical error, post-discard, and pre-discard rates under circuit-level noise.
  • Scaling behavior: The expected asymptotic scalings are observed for all preparation methods and states.For distance-4 preparation, pre-discard events scale as O(p), while post-discard events are expected to scale as O(p2).
  • Method comparison: For |¯0⟩⊗48, the ILP method gives the best logical-error and post-discard rates, followed by Goto’s method.F@O is comparable to Projective in logical error and pre-discard rate but has better post-discard performance.
  • Method comparison: Projective preparation performs better in the Z basis for random product and GHZ states, while F@O has worse logical-error and post-discard rates but a significantly better pre-discard rate.The basis dependence reflects the natural bias of the Projective method.
  • Practical trade-offs: ILP performs well but requires solving a large computational problem for each state, whereas F@O and Projective apply in polynomial time to arbitrary CSS states.F@O is favored when avoiding pre-discarded attempts is more important than minimizing logical error.

1. Projective preparation

Projective preparation fault-tolerantly prepares encoded CSS states by initializing a product state, measuring commuting checks, and postselecting desired outcomes. The section also develops flagged circuits and concatenated-code schedules to control logical errors and hardware overhead.

  • Projective preparation: Projective preparation initializes data qubits in a product basis state, then repeatedly measures commuting parity checks to project onto a desired logical state.For concatenated iceberg codes, stabilizers are measured in the basis opposite to the initial product state, with additional logical-operator measurements selecting the target sector.
  • Projective preparation: Single-fault events are either flagged and rejected or remain correctable, suppressing accepted logical failure to O(p^2).Distance-4 preparation does not require individually detecting every two-fault event.
  • Projective preparation: Zigzag syndrome-ancilla ordering spreads hook-error endpoints across blocks, preventing unflagged two-fault events from mimicking a correctable single-qubit error.The schedule supports fault-tolerant syndrome extraction with a single flag ancilla for representative outer stabilizers.
  • Projective preparation: Simulation benchmarks logical state preparation under depolarizing noise using flagged stabilizer and logical-operator measurements followed by syndrome postselection.The benchmark compares flag-at-origin and projective preparation in X and Z bases, including conditioned logical error and pre- versus post-discard probabilities.
  • Projective preparation: The flag-at-origin method provides an alternative concatenated-iceberg preparation approach, optimized through selective flagging, serial gadget execution, and joint circuit-ordering searches.These optimizations account for Helios’s available qubits and avoid flagging fault pairs that the ideal decoder would already discard.
  • Projective preparation: Flag-based fault tolerance converts a non-fault-tolerant preparation circuit into an equivalent FT circuit for the I8◦I6 code.The reported FT circuit uses 344 CX gates and 67 measurements, while the associated non-FT circuit has depth 9.

XIII: Decoding Goto’s state preparation

This section decodes concatenated-iceberg state preparation by classifying measured syndromes and logical equivalence classes under circuit-level depolarizing noise. The decoder avoids correcting ambiguous weight-two syndromes and uses postselection to retain higher-confidence outcomes.

  • Decoding Goto’s state preparation: The decoder reconstructs each final state’s syndrome s and logical equivalence class q across 2^16 syndromes and 2^48 equivalence classes.Stim simulations apply two-qubit depolarizing noise after gates and equal initialization and measurement error rates.
  • Decoding Goto’s state preparation: Syndrome probabilities are grouped by minimum-weight errors, while higher-weight errors can share syndromes through logical and stabilizer equivalence.The analysis samples 10^10 circuits for each physical error rate p.
  • Decoding Goto’s state preparation: For most two-qubit errors, the maximum-likelihood equivalence class has probability P_qmax,s/P(s) ≲ 1/2, making correction ambiguous.At least two same-weight errors in different equivalence classes contribute to these syndromes under comparable circuit-level noise probabilities.
  • Decoding Goto’s state preparation: The decoder therefore postselects away syndromes compatible with weight-two-and-higher errors, retaining only the postselected fraction for state preparation.Flagged circuit runs are discarded first, and the remaining discard rate is tracked separately from the final logical error rate.
  • Decoding Goto’s state preparation: The resulting logical error rate scales as p^3 because three-qubit errors can share a syndrome with a one-qubit error in another equivalence class.This scaling describes the final logical error rate after flagging and syndrome postselection.
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