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No More Hooks in the Surface Code: Distance-Preserving Syndrome Extraction for Arbitrary Layouts at Minimum Depth

Yuga Hirai, Shota Ikari, Yosuke Ueno, Yasunari Suzuki

arXiv:2603.01628v2quant-ph

TL;DR

Hook errors can reduce the surface code’s fault distance, and minimum-depth extraction for layouts used in logical operations has remained unresolved. The paper introduces ZX interleaving syndrome extraction for regular stabilizer layouts. Simulations report full fault distance in memory and lattice-surgery experiments, with a threshold trade-off and a scope limited to regular tiles.

  • Problem

    Hook errors can lower fault distance, while extraction circuits for logical-operation layouts such as lattice surgery have not been proposed without the overheads of existing approaches.

    Source: B. Syndrome Extraction and Hook Errors · p. 3, A. Problem setting · p. 5

  • Method

    ZX interleaving syndrome extraction adapts Z- and X-tile movement to arbitrary regular layouts, using boundary measurement qubits to accommodate opposite-Pauli boundary moves.

    Source: §I · pp. 1–2, §IV · p. 7

  • Results

    The method preserves full fault distance at minimum depth in memory and lattice-surgery experiments, and has the lowest logical error rates among minimum-depth methods for lattice surgery.

    Source: §I · p. 2, B. Memory-experiment layout · p. 8, C. Lattice-surgery layout · p. 10

  • Takeaways & Limitations

    The method avoids additional circuit depth and simultaneous measurement or reset with CNOT gates, while requiring each measurement qubit to couple to only three neighboring data qubits.

    Source: §I · p. 2, §VI · p. 11

    The method addresses regular square-tile layouts; rectangular stabilizers and stabilizers acting on more than four data qubits are beyond scope.

    Source: A. Problem setting · p. 6

Abstract

from arXiv · show

Hook errors are a major challenge in implementing logical operations with the surface code, because they can reduce the fault distance below the code distance. This motivates syndrome-extraction circuits that suppress hook-error effects for the stabilizer layouts that appear during logical operations. However, the existing methods either increase circuit depth or require simultaneous execution of measurements and CNOT gates, both of which introduce additional overheads and degrade the threshold. We propose the ZX interleaving syndrome extraction, which preserves the full fault distance $d$ for any surface-code layout with regular stabilizer tiles at minimum depth, i.e., four layers of CNOT gates, without requiring additional circuit depth or simultaneous execution of measurements and CNOT gates. The key idea is to interleave the Z and X stabilizer tiles so that hook-error edges in the decoding graph are shortened and effectively eliminated. Numerical simulations under uniform depolarizing noise for memory and lattice-surgery experiments confirm that the proposed method achieves a full fault distance of $d$, whereas the best existing minimum-depth approach achieves $d-1$. Since the full fault distance is achievable for any regular tiling layout of the surface code, the proposed method may serve as an indispensable technique for practical fault-tolerant quantum computation.

I. INTRODUCTION

Hook errors can reduce surface-code fault distance, and existing approaches for logical-operation layouts carry depth, timing, or CNOT-ordering overheads. The paper proposes a minimum-depth method and evaluates it in memory and lattice-surgery experiments.

I. INTRODUCTION

  • Hook errors can reduce fault distance, and extraction circuits for stabilizer layouts used in logical operations such as lattice surgery had not yet been proposed.Surface codes support logical operations through approaches including lattice surgery, code deformation, and magic-state methods [7] [11] [12].Source: §I · p. 1
  • Existing methods trade hook-error suppression for extra circuit depth, simultaneous measurement and CNOT execution, or non-uniform CNOT ordering.Extra depth increases syndrome-extraction time and effective physical error rates per cycle, degrading the threshold; mismatched measurement and CNOT durations can also increase cycle time.Source: §I · p. 1
  • The method adapts tile motion to layouts where Z and X tiles move toward opposite-Pauli boundaries, using additional measurement qubits along those boundaries.The underlying dynamic-surface-code scheme shortens hook-error propagation edges, but is specific to memory layouts.Source: §I · pp. 1–2
  • The proposed method alone preserves full fault distance at minimum depth in both memory and logical Pauli-XX lattice-surgery experiments, with a slight threshold trade-off.It is less advantageous near threshold; in lattice surgery it has the lowest logical error rates among minimum-depth methods.Source: §I · p. 2
  • Measurement qubits in the proposed method couple to only three neighboring data qubits.The paper notes that reduced connectivity may suppress circuit-level physical error rates, potentially offsetting the threshold trade-off.Source: §I · p. 2

II. PRELIMINARIES

The preliminaries introduce the surface-code structures and logical operations needed for the paper. They define tiles, patches, boundaries, code distance, and the connected-boundary layout used for a logical Pauli-XX measurement.

II. PRELIMINARIES

  • The preliminaries review rotated surface codes, logical operations, hook errors, decoding graphs, and detector diagrams as foundations for the paper.The authors refer readers to Refs. for further details on QEC codes and fault distances.Source: §II · p. 2

A. Surface Code and Logical Operations

  • Surface codes support universal logical operations using nearest-neighbor interactions, and lattice surgery performs a logical Pauli-XX measurement by temporarily connecting patch boundaries.Stabilizers are measured repeatedly in the connected layout before the patches are separated again; patch movement, rotation, and other operations can also use changed tiles and boundaries.Source: A. Surface Code and Logical Operations · pp. 2–3
  • Rotated surface codes use data qubits to store information and measurement qubits to extract syndromes; tile-like stabilizers define Z and X boundaries, and code distance is the lattice side length.The paper calls the whole code block a patch and its square stabilizers tiles; Fig. 1 has d = 5.Source: A. Surface Code and Logical Operations · p. 2

B. Syndrome Extraction and Hook Errors

Hook errors arise when a single-qubit Pauli error propagates to multiple data qubits during syndrome extraction, potentially lowering fault distance. CNOT ordering can preserve distance in memory layouts, but must be designed carefully.

B. Syndrome Extraction and Hook Errors

  • A single-qubit Pauli error can propagate to multiple physical qubits during syndrome extraction, and may lower fault distance below code distance.If hook errors span a logical operator's support, the fault distance decreases.Source: B. Syndrome Extraction and Hook Errors · p. 3
  • In the Z-stabilizer circuit, an error on the measurement qubit after two CNOTs propagates to two data qubits.A CNOT copies a Z error from the target to control qubits; X errors propagate similarly in X-stabilizer circuits.Source: B. Syndrome Extraction and Hook Errors · p. 3, Figure 3 · p. 3
  • For memory layouts, an N-shaped ordering for Z stabilizers and a Z-shaped ordering for X stabilizers makes hooks propagate perpendicular to logical operators, preserving fault distance at four CNOT layers.This ordering is known to preserve memory-layout fault distance at minimum depth.Source: B. Syndrome Extraction and Hook Errors · p. 3, Figure 4 · p. 3

C. Decoding Graph and Detector Diagrams

Decoding graphs and detector diagrams provide tools for tracking error propagation and fault distance in syndrome-extraction circuits. In a decoding graph, detectors are nodes and graphlike errors become edges or boundary connections.

C. Decoding Graph and Detector Diagrams

  • Decoding graphs and detector diagrams help monitor error propagation and fault distance in complicated syndrome-extraction circuits.The discussion focuses on rotated surface codes, though these models apply to any QEC code.Source: C. Decoding Graph and Detector Diagrams · p. 3

1. Decoding Graph

  • A decoding graph maps detectors to nodes, graphlike errors flipping two detectors to edges, and errors flipping one detector to a boundary connection.Fault distance can be bounded by the number of edges connecting opposing boundaries.Source: §1 · p. 4
  • In the illustrated Z-detector graph, light-blue spacelike edges represent data-qubit errors and dark-blue timelike edges represent measurement-qubit errors; five edges connect opposing Z boundaries.The graph omits hook-error edges.Source: §1 · p. 4
  • Hook-error edges connect detectors separated by a tile, creating shortcut paths that may reduce fault distance, though the illustrated shortcut does not reduce it.In the example, the hook edges run left to right while the logical Z support spans front to back.Source: §1 · p. 4

2. Detector Diagram

Detector diagrams visualize the regions of a circuit where errors flip detectors, and can represent logical operations as three-dimensional spacetime diagrams. Their boundary geometry relates to preserving fault distance.

2. Detector Diagram

  • A detecting region is a circuit region where errors flip a detector, and detector diagrams sequence these regions across time.In a single syndrome-extraction round, blue regions detect X errors and red regions detect Z errors; an error within a region flips the opposite-type detector.Source: §2 · pp. 4–5, Figure 8 · p. 5
  • A 3D spacetime diagram represents logical operations with time along the Z-axis; for memory, colored walls extend code boundaries through time and purple lines mark twist defects.The memory diagram can also be shown with its front walls transparent.Source: §2 · p. 5, Figure 9 · p. 5
  • To preserve fault distance in a 3D diagram, distinct walls of the same color must remain at least one code distance apart, measured in decoding-graph edges.An error chain connecting distinct Z or X walls acts as a logical Pauli Z or X error, respectively.Source: §2 · p. 5

III. MOTIVATION: DISTANCE-PRESERVING SYNDROME EXTRACTION CIRCUITS FOR ARBITRARY TILE LAYOUTS

Existing minimum-depth CNOT orderings for memory layouts can create shortcut paths that reduce fault distance in arbitrary tile layouts. The section motivates a general ordering method that preserves distance without changing syndrome-extraction round length.

III. MOTIVATION: DISTANCE-PRESERVING SYNDROME EXTRACTION CIRCUITS FOR ARBITRARY TILE LAYOUTS

  • In the example arbitrary layout, shortcut paths in the X-stabilizer decoding graph reduce fault distance, and N/Z-shaped orderings or their simple transformations halve it.The paper identifies a need for a systematic construction of CNOT orderings for arbitrary tile layouts.Source: A. Problem setting · pp. 5–6, Figure 11 · p. 6
  • The desired ordering should follow a simple rule from the tile layout, preserve fault distance equal to code distance, and leave syndrome-round length unchanged.The section states that, to the authors' knowledge, no existing method meets all these requirements.Source: A. Problem setting · p. 6
  • The paper's scope is regular tile layouts: square, tile-like stabilizers with appropriate two-qubit stabilizers at boundaries.Rectangular stabilizers and stabilizers acting on more than four data qubits are beyond scope, with support left for future work.Source: A. Problem setting · p. 6

B. Existing work

Prior distance-preserving syndrome-extraction methods for arbitrary layouts trade off circuit depth, simultaneous operations, or fault distance. Existing approaches also have limitations in scalability or layout scope.

B. Existing work

  • Alternating CNOT orderings achieve depth four but reduce fault distance to d−1 [27] [28].Refs. [28] reverse N/Z ordering across even and odd cycles; Ref. [27] alternates Z- and N-shaped ordering.Source: B. Existing work · p. 6
  • Ref. flexibly assigns N/Z shapes to avoid hook-error shortcuts, but increases depth to prevent simultaneous CNOTs on a data qubit.Source: B. Existing work · p. 6
  • Ref. [17] avoids hook errors with idling depth or diagonal ordering; the latter uses CNOT depth four but requires simultaneous measurement and CNOT execution.Without that simultaneity, its CNOT depth rises to seven.Source: B. Existing work · p. 6, Figure 12 · p. 6
  • Ref. preserves full fault distance for standard memory layouts, but its tile movements do not cover arbitrary layouts such as lattice surgery.Heuristic solver approaches [30] [31] apply broadly, but distance calculation is NP-hard and expected to be prohibitively slow for large layouts.Source: B. Existing work · p. 7

IV. ZX INTERLEAVING SYNDROME EXTRACTION

ZX interleaving uses tile movement and CNOT ordering to shorten hook-error edges while retaining minimum depth. Combining two movement patterns extends the construction to arbitrary surface-code layouts.

IV. ZX INTERLEAVING SYNDROME EXTRACTION

  • The proposed ZX interleaving syndrome extraction constructs circuits for any surface-code layout at CNOT depth four.The design was constructed using Crumble and Stim.Source: §IV · p. 7
  • Interleaved Z and X tiles move toward their respective boundaries, and the last two CNOT gates prevent hook errors from contaminating logical operators.The ordering is neither N-shaped nor Z-shaped.Source: §IV · p. 7
  • Moving tiles parallel to hook errors but in the opposite direction shortens hook-error edges, making them harmless regardless of their direction.Source: §IV · p. 7
  • For layouts requiring tiles to move toward opposite-type boundaries, the construction preserves fault distance at minimum depth by using additional boundary measurement qubits.Source: §IV · p. 7
  • Combining the movement patterns supports arbitrary layouts with uniform CNOT ordering, no extra depth, and no simultaneous measurement or reset with CNOT gates.The method uses only three neighboring data-qubit couplings and retains the logical-qubit density of N/Z ordering.Source: §IV · p. 7

A. Benchmark settings

The memory experiments compare ZX interleaving with minimum-depth alternatives under circuit-level depolarizing noise. ZX interleaving preserves full fault distance, while logical-error-rate comparisons vary by tile-movement variant and noise regime.

A. Benchmark settings

  • The benchmark compares four-layer CNOT circuits using N/Z and alternating orderings with ZX interleaving under one- and two-qubit uniform depolarizing noise.It covers memory experiments and lattice surgery for Pauli-XX measurements; memory circuits use d syndrome-extraction rounds.Source: A. Benchmark settings · p. 7, B. Memory-experiment layout · p. 8

B. Memory-experiment layout

  • Both ZX-interleaving movement patterns achieve full fault distance for memory layouts, and their logical-error scaling matches the full-distance hook-avoiding N/Z ordering.Source: B. Memory-experiment layout · pp. 8–9
  • The Z→Z/X→X variant has the lowest logical error rate across code distances; Z→X/X→Z beats alternating ordering at small distances or low physical error rates, but not at large distances or high rates.The paper attributes the crossover to measurement-error events that matter when tiles shift toward logical operators; the Z→X/X→Z threshold is slightly lower than the other methods.Source: B. Memory-experiment layout · p. 9
  • At high physical error rates, additional error events involving tile movement and measurement errors become non-negligible.The authors expect fidelity improvements from hexagonal-grid qubit allocation may compensate for this drawback.Source: B. Memory-experiment layout · p. 10

C. Lattice-surgery layout

For lattice-surgery Pauli-XX measurements, ZX interleaving preserves full fault distance for both error types. Its logical-error-rate advantage over alternating ordering depends on physical error rate and code distance.

C. Lattice-surgery layout

  • All methods achieve full fault distance for Z errors; for X errors, ZX interleaving achieves full distance while N/Z is halved and alternating ordering loses one.The authors report this as the first full-fault-distance result without overhead in syndrome-extraction circuit length.Source: C. Lattice-surgery layout · p. 10
  • For X errors, ZX interleaving has lower logical error rates than alternating ordering at sufficiently low physical error rates or small distances, while alternating ordering performs better at high rates or large distances.The crossover is attributed to the same mechanism as in the memory experiments; the regime favoring ZX interleaving is broader here.Source: C. Lattice-surgery layout · p. 11

VI. CONCLUSION

ZX interleaving preserves the surface code’s fault distance for arbitrary layouts with regular stabilizer tiles at minimum depth. Simulations confirm full fault distance for memory and lattice-surgery experiments.

VI. CONCLUSION

  • Simulations confirm full fault distance for memory experiments and lattice-surgery operations, with the lowest logical error rate among existing methods when physical error rates are sufficiently low.The method requires no additional circuit depth, non-uniform CNOT ordering, or simultaneous measurement or reset operations alongside CNOT gates.Source: §VI · p. 11
  • At higher physical error rates or larger code distances, additional measurement qubits and their error events produce higher logical error rates than existing methods.Modified constructions to mitigate these additional error events remain a direction for future work.Source: §VI · p. 11
  • The method applies to layouts in Refs. [35] [36] while preserving fault distance at minimum depth, but application to irregular stabilizers such as bulk twist defects remains future work.The authors expect logical error rates in those layouts to improve when physical error rates are sufficiently small.Source: §VI · p. 11
  • Compared with enlarging the layout by one unit, ZX interleaving uses nearest-unused measurement qubits and preserves higher logical-qubit density per unit area on hexagonal or square grids.A same-qubit-count flag-qubit approach might be superior, but the authors do not yet know how to construct it explicitly.Source: §VI · p. 11
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