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Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification

Samar Ansari

arXiv:2604.04712v1cs.CRcs.CY

TL;DR

Frontier AI governance increasingly depends on compute controls, but the hardware mechanisms proposed for enforcement and treaty verification remain insufficiently assessed and unevenly mature. The paper develops a 20-mechanism feasibility taxonomy, maps mechanisms to governance scenarios, and finds that treaty-critical mechanisms are among the least mature while the implementation window is narrowing. It therefore identifies a time-bounded R&D agenda for hardware-level governance.

  • Problem

    Hardware-level mechanisms in compute-governance proposals remain largely unexamined from an engineering perspective, leaving their feasibility, vulnerabilities, and deployment requirements unclear.

    Source: §1 · p. 2, §2.1 · p. 3

  • Method

    The paper classifies 20 hardware-level mechanisms by monitoring, verification, and enforcement, rates them on a four-point feasibility scale, and maps them to four governance scenarios.

    Source: §1 · p. 2

  • Results

    Mechanisms most needed for international treaty verification, including on-chip metering, proof-of-training, and hardware enforcement, remain in the R&D stage while monitoring and administrative enforcement mechanisms are more feasible.

    Source: §3.4 · p. 10, §6.5 · p. 20

  • Takeaways & Limitations

    Hardware-level governance could support verifiable international agreements only if critical mechanisms are developed and deployed before semiconductor-manufacturing leverage narrows.

    Source: §6.1 · p. 19, §6.5 · p. 20

    The assessments rely on public literature and specifications, may omit classified or proprietary advances, and do not systematically address neuromorphic, quantum, or optical hardware.

    Source: §6.4 · p. 20

Abstract

from arXiv · show

The governance of frontier AI increasingly relies on controlling access to computational resources, yet the hardware-level mechanisms invoked by policy proposals remain largely unexamined from an engineering perspective. This paper bridges the gap between AI governance and computer engineering by proposing a taxonomy of 20 hardware-level governance mechanisms, organised by function (monitoring, verification, enforcement) and assessed for technical feasibility on a four-point scale from currently deployable to speculative. For each mechanism, we provide a technical description, a feasibility rating, and an identification of adversarial vulnerabilities. We map the taxonomy onto four governance scenarios: domestic regulation, bilateral agreements, multilateral treaty verification, and industry self-regulation. Our analysis reveals a structural mismatch: the mechanisms most needed for treaty verification, including on-chip compute metering, cryptographic proof-of-training, and hardware-embedded enforcement, are also the least mature. We assess principal threats to compute-based governance, including algorithmic efficiency gains, distributed training methods, and sovereignty concerns. We identify a temporal constraint: the window during which semiconductor manufacturing concentration makes hardware-level governance implementable is narrowing, while R&D timelines for critical mechanisms span years. We present an adversary-tiered threat analysis distinguishing commercial, non-state, and nation-state actors, arguing the appropriate security standard is tamper-evident assurance analogous to IAEA verification rather than absolute tamper-proofing. The taxonomy, feasibility classification, and mechanism-to-scenario mapping provide a technical foundation for policymakers and identify the R&D investments required before hardware-level governance can support verifiable international agreements.

1 Introduction

Frontier AI governance increasingly targets compute because it is detectable, excludable, and quantifiable, but hardware-level proposals lack detailed engineering assessment. This paper addresses that gap with a feasibility-oriented taxonomy and governance-scenario mapping.

1 Introduction

  • The paper bridges policy and engineering literatures by evaluating whether hardware-level governance mechanisms can be built, at what cost and timeline, and against which adversaries.Existing proposals invoke on-chip metering, cryptographic attestation, hardware kill switches, and trusted execution environments without assessing their technical feasibility.Source: §1 · p. 2
  • It proposes a taxonomy of 20 mechanisms organised by monitoring, verification, and enforcement, with feasibility ratings ranging from currently deployable to speculative.Each mechanism receives a technical description, feasibility assessment, governance-scenario relevance, and adversarial-vulnerability analysis.Source: §1 · p. 2
  • The taxonomy is mapped onto domestic regulation, bilateral agreements, multilateral treaty verification, and industry self-regulation to identify context-appropriate mechanisms.Source: §1 · p. 2
  • The paper distinguishes commercial, non-state, and nation-state threats and argues for tamper-evident assurance analogous to IAEA verification rather than absolute tamper-proofing.Source: §1 · p. 2
  • Treaty-relevant mechanisms are least mature, with 18 months to 4 years of R&D followed by about 4 years of widespread deployment, creating a time-bounded agenda.Source: §1 · p. 2
  • Feasibility ratings are based on a systematic review of 2022–2026 governance and engineering literature, using a conservative four-level scale adapted from technology-readiness frameworks.Source: §1 · p. 2

2 The Compute Governance Landscape

Existing compute-governance instruments rely on technical assumptions that are rarely independently verified. International proposals demand governance-grade hardware mechanisms that remain unavailable, motivating the paper’s feasibility taxonomy.

2 The Compute Governance Landscape

  • Existing compute-governance policy treats compute as a detectable, excludable, and quantifiable regulatory proxy, while leaving its technical assumptions largely untested.Source: §2 · p. 2

2.1 Compute Thresholds in Existing Regulation

  • EU threshold regulation assumes reliable compute measurement and a durable risk boundary, but frontier training compute has doubled about every six months, making static thresholds problematic.The EU AI Act uses a 10^25 FLOPs threshold and permits updates without specifying an automatic adjustment formula.Source: §2.1 · p. 3
  • US reporting requirements showed that cloud-provider reporting is administratively feasible, although accuracy and completeness remain untested under adversarial conditions.Source: §2.1 · p. 3
  • Across jurisdictions, self-reported compute figures lack independent verification and can potentially be circumvented through distillation, fine-tuning, or distributed training across reporting boundaries.Source: §2.1 · p. 3

2.2 Export Controls and Supply Chain Instruments

  • Export controls assume post-sale end-use verification, diversion detection, and prevention of equivalent cloud or aggregated-chip access, capabilities they do not currently provide.Source: §2.2 · p. 3

2.3 International Proposals

  • International proposals include IAEA-like institutions, chip agreements, compute pauses, licensing, registries, and mutual verification, but depend on mechanisms that do not yet exist at governance grade.These include on-chip compute metering, cryptographic proof of training compliance, hardware-enabled enforcement, and privacy-preserving verification.Source: §2.3 · pp. 3–4

3 Taxonomy of Hardware-Level Governance Mechanisms

The taxonomy organizes 20 hardware-level governance mechanisms into monitoring, verification, and enforcement, then classifies their feasibility across implementation variants. It shows that mechanisms most needed for international treaty verification remain less mature than many monitoring and administrative enforcement tools.

3 Taxonomy of Hardware-Level Governance Mechanisms

  • The taxonomy groups 20 mechanisms by monitoring, verification, and enforcement and assigns identifiers for cross-referencing across the paper.Figure 1 visualizes the categories and feasibility tiers; some mechanisms span multiple tiers depending on implementation.Source: §3 · p. 4, Figure 1 · p. 4

3.1 Monitoring Mechanisms

  • Cloud metadata, workload classification, KYC, power monitoring, chip registries, and location tracking provide deployable or near-term monitoring capabilities, but coverage and adversarial robustness remain limited.Provider metadata excludes on-premises and cross-provider compute; workload classification has achieved 95% accuracy in cooperative environments, while power monitoring is nonspecific without supplementary signals.Source: §3.1 · pp. 4–6
  • On-chip compute metering could support threshold governance, but proposed architectures remain at the R&D stage, with estimated development and deployment timelines spanning several years.Repurposed performance counters offer a lower-cost but weaker approach, whereas enclosed guarantee processors provide higher assurance with unresolved I/O mediation costs.Source: §3.1 · pp. 5–6

3.2 Verification Mechanisms

  • TEEs can attest bounded workload properties without exposing model details, but side channels, hardware replacement constraints, and absent multi-GPU support limit governance-grade deployment.The H100 provides the most relevant current accelerator substrate, yet frontier training typically spans hundreds or thousands of accelerators.Source: §3.2 · pp. 6–7
  • Verification mechanisms must demonstrate compliance while preserving confidentiality, making physical inspection currently deployable but limited by labor intensity and lack of continuous monitoring.TEEs, cryptographic proof-of-training, FlexHEG verifiable claims, and governance-grade remote attestation require further R&D, while existing GPU confidential computing does not yet support multi-GPU frontier training.Source: §3.2 · pp. 6–8

3.3 Enforcement Mechanisms

  • Enforcement ranges from deployable cloud access controls, export controls, licensing, and supply-chain restrictions to speculative chip-level networking limits and hardware off-switches.Cloud and export controls remain jurisdictionally vulnerable, while distributed training reduces the long-term utility of bandwidth restrictions and hardware enforcement requires years of development.Source: §3.3 · pp. 8–9
  • Remote performance degradation and disablement are technically plausible but politically constrained because centralized authority over chip operation creates sovereignty concerns.Distributed authorization among independent jurisdictions has been proposed conceptually but not designed in detail.Source: §3.3 · p. 9

3.4 Feasibility Summary

  • The feasibility distribution reveals a structural mismatch: monitoring and administrative enforcement are comparatively mature, while M5 on-chip metering, V2 proof-of-training, and E3 hardware off-switches needed for treaty verification remain in R&D.Near-term R&D priorities include M5, V2, V3 FlexHEG-based verifiable claims, and E6 hardware-embedded licensing.Source: §3.4 · pp. 9–10, Table 1 · p. 10

4 Feasibility Constraints and Adversarial Considerations

Compute-based governance faces interacting technical, adversarial, political, and temporal constraints. Algorithmic efficiency, decentralised training, physical attacks, sovereignty concerns, manufacturing diffusion, and inference-time scaling all weaken mechanisms built around centralised training compute.

4.1 Algorithmic Efficiency and the Erosion of Compute Thresholds

  • Algorithmic efficiency, distillation, model reuse, and low-cost fine-tuning can produce capable systems below training-compute thresholds.Inference-time scaling can also change risk without additional training compute, while fine-tuning typically requires less than 1% of pre-training compute.Source: §4.1 · pp. 10–11

4 Feasibility Constraints and Adversarial Considerations

  • Treaty-relevant mechanisms are predominantly immature, while currently deployable mechanisms have limited treaty applicability.Figure 2 compares treaty-verification importance with feasibility tiers, showing a readiness gap between governance need and technical maturity.Source: Figure 2 · p. 11

4.2 Distributed and Decentralised Training

  • Distributed training enables threshold evasion by splitting workloads across providers, removing centralised off-switches, and obscuring communication signatures.BLOOM’s 5.8 × 10^23 FLOPs could theoretically be hidden as 58 instances of 10^22 FLOPs, while detection is difficult without provider information sharing.Source: §4.2 · p. 12
  • Networking restrictions are increasingly questionable because large-scale training can use two orders of magnitude less interconnect bandwidth.This weakens governance mechanisms that depend on cluster-level visibility and could erode the physical detectability of frontier training within a decade.Source: §4.2 · p. 12

4.3 Physical and Side-Channel Attacks on Hardware Mechanisms

  • Hardware mechanisms face logical flaws, glitching, probing, side channels, supply-chain compromise, and cryptographic attacks because adversaries possess the devices.Small distributed security blocks may lack sufficient area for constant-time cryptography, glitch detection, and masking; enclosure-based designs reduce exposure but do not eliminate sophisticated physical attacks.Source: §4.3 · p. 12, Adversary-Tiered Threat Model for… · p. 13

Adversary-Tiered Threat Model for Hardware Governance

  • Adversary tiering supports tamper-evident assurance rather than absolute tamper-proofing: raise circumvention costs for Tiers 1–2 and expose Tier 3 attacks.Nation-state attacks may not scale chip-by-chip, but supply-chain backdoors can propagate across production runs; the proposed analogy is IAEA verification.Source: §4.3 · p. 12, Adversary-Tiered Threat Model for… · p. 13, Figure 3 · p. 13

4.4 Privacy, Sovereignty, and Political Feasibility

  • Monitoring and embedded enforcement create privacy, sovereignty, regulatory-capture, and distributional risks that engineering alone cannot resolve.Remote disablement and location-based locking can concentrate geopolitical leverage, while centralised compute control may entrench power asymmetries and constrain less-resourced countries.Source: §4.4 · p. 14

4.5 The Concentration Dependency

  • Hardware governance has a narrowing implementation window because critical mechanisms must be deployed before advanced-chip manufacturing concentration diffuses.The longest-timeline mechanisms include on-chip metering, FlexHEGs, and hardware-embedded licensing; otherwise manufacturing leverage may no longer support mandated adoption.Source: §4.5 · pp. 14–15

5 Mapping Mechanisms to Governance Scenarios

This section maps hardware-level governance mechanisms onto domestic, bilateral, multilateral, and industry scenarios, then compares layered institutional designs with existing verification regimes. It finds that domestic measures are most deployable, while treaty verification requires the least mature mechanisms and should be developed incrementally.

5.1 Governance Scenarios

  • The paper considers domestic regulation, bilateral agreements, multilateral treaty verification, and industry self-regulation as distinct governance scenarios.These scenarios differ in legal authority, jurisdictional reach, verification requirements, and dependence on voluntary cooperation.Source: §5.1 · p. 15

5.2 Mechanism–Scenario Mapping

  • Table 2 rates mechanisms as strong fits (++), applicable with caveats (+), or limited or infeasible (−) by combining feasibility, adversarial robustness, and institutional constraints.The mapping therefore evaluates both technical suitability and institutional alignment.Source: §5.2 · pp. 15–16, Table 2 · p. 16
  • Domestic regulation is best served by deployable mechanisms such as cloud metadata, KYC, workload classification, TEE attestation, and compute licensing.These mechanisms operate within domestic jurisdictional reach, but cannot govern foreign or non-cloud compute.Source: §5.2 · p. 16
  • Bilateral agreements require mechanisms verifiable without full trust, including chip-location tracking, remote attestation, export controls, and upstream supply-chain controls.Remote disablement offers continued leverage beyond sale, but its political feasibility depends on bilateral authority rather than unilateral control.Source: §5.2 · p. 16
  • Multilateral treaty verification has the most demanding requirements and depends on comparatively immature mechanisms such as on-chip FLOP metering, proof-of-training, physical inspection, hardware off-switches, and multiparty cryptographic control.Multiparty cryptographic control supports a hardware-level two-person rule against unilateral action.Source: §5.2 · p. 16
  • Industry self-regulation is limited to voluntary mechanisms such as cloud metadata, TEE attestation, internal compute licensing, and cloud access control.Mechanisms requiring hardware modification or coordination across firms are effectively unavailable without legal mandates.Source: §5.2 · p. 16

5.3 Lessons from Existing Verification Regimes

  • The IAEA model offers the closest structural precedent for treaty verification because both nuclear materials and advanced AI chips are dual-use, capital-intensive, quantifiable, and produced through concentrated supply chains.Analogous mechanisms include chip registries, physical inspection, power monitoring, and upstream supply-chain controls.Source: §5.3 · p. 17
  • The nuclear analogy is constrained because AI chips lack radioactivity, the IAEA depends on state consent, institutions took decades to build, and model weights can be digitally copied.These differences make passive detection, enforcement, and institutional timing harder for AI governance.Source: §5.3 · p. 17

6 Discussion and Implications

The paper finds a structural mismatch between governance needs and hardware readiness, intensified by a narrowing semiconductor-manufacturing window. It identifies research priorities, policy actions, and limitations for developing verifiable hardware-level AI governance.

6.1 The Readiness Gap and the Closing Window

  • Domestic regulation can use deployable mechanisms, but bilateral enforcement and multilateral treaty verification require early-stage technologies such as on-chip metering, proof-of-training, and hardware-embedded enforcement.The readiness gap separates currently usable domestic controls from mechanisms needed for higher-stakes international governance.Source: §6.1 · pp. 18–19
  • Critical mechanisms face a 6-to-8+-year development and deployment timeline while distributed training, algorithmic efficiency, and manufacturing diffusion narrow the implementation window.The paper concludes that delayed development could leave essential mechanisms ready only after the structural leverage for adoption has eroded.Source: §6.1 · p. 19, Figure 5 · p. 19

6.2 Implications for Research

  • On-chip metering and proof-of-training require functional, secure, scalable implementations beyond current conceptual and heuristic designs.FlexHEG, embedded off-switch, Proof-of-Learning, and Proof-of-Training-Transcript provide starting points, but physical-attack testing, provable security, and frontier-scale operation remain unresolved.Source: §6.2 · pp. 19–20
  • Inference-time governance is largely unexplored, even as inference scaling, mixture-of-experts systems, and post-training enhancement blur training-deployment boundaries.The paper identifies extending FlexHEG verification and proof-of-training concepts to inference as a necessary research direction.Source: §6.2 · p. 20
  • Hardware-embedded enforcement must combine cryptographic design with institutional arrangements that distribute authority and address sovereignty and legitimacy concerns.The paper highlights multiparty control and majority-government approval as possible foundations for distributed governance architectures.Source: §6.2 · p. 20

6.3 Implications for Policy

  • Policymakers should avoid mandates based on immature mechanisms, build layered governance using deployable domestic controls, and begin coordinating standards and provider requirements now.The recommended early coordination covers chip registries, compute-provider KYC, and hardware-security specifications.Source: §6.3 · p. 20

6.4 Limitations

  • The conclusions are limited by reliance on public literature, exclusion of several non-neural hardware paradigms, absent political-economy modeling, unassessed adoption costs, and non-independent feasibility ratings.Reported engineering parameters are drawn from cited sources and are not independently verified by the paper.Source: §6.4 · p. 20

6.5 Conclusion

  • Hardware-level governance is feasible in principle but unevenly mature, and developing it within the closing manufacturing window could support verifiable international agreements.Failure to close the readiness gap would leave governance instruments without technical means of verification and enforcement.Source: §6.5 · p. 20
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